M2 – Instruction Set...

M2 – Instruction Set Architecture

Module Outline● Addressing modes. Instruction classes.● MIPS-I ISA.● High level languages, Assembly languages

and object code.● Translating and starting a program.● Subroutine and subroutine call. Use of stack

for handling subroutine call and return.

MIPS-I Arithmetic Instructions

Mnemonics Example Meaning

Add, Subtract

ADD, ADDU, ADDI, ADDIU, SUB, SUBU

ADD R1, R2, R3ADDU R1, R2, R3ADDI R1, R2, 6

R1 ← R2 + R3R1 ← R2 + R3

6 bits 5 bits 5 bits 5 bits 6 bits5 bits

op rs rt rd sh_amt funct

op: Opcode (class of instruction). Eg. ALUfunct: Which subunit of the ALU to activate?ADD – op/funct = 0x0/0x20

OP rd, rs, rt

R Format

sh_amt: Shift Amount. For Shift Instructions – SLL, SRL.

MIPS-I Arithmetic InstructionsMnemonics Example Meaning

Add, Subtract


ADD R1, R2, R3ADDI R1, R2, 6

R1 ← R2 + R3

Multiply, Divide

MULT, DIV, MULTU, DIVU

MULT R1, R2 LO ← lsw (R1 * R2)

R1 ← R2 + 6

HI ← msw (R1 * R2)


Add, Subtract



R1 ← R2 + R3

Multiply, Divide



R1 ← R2 + 6

HI ← msw (R1 * R2)

● Product of two 32-bit numbers is a 64-bit quantity. HI and LO contain the MSW and LSW of the Product


Add, Subtract



R1 ← R2 + R3

Multiply, Divide



R1 ← R2 + 6

HI ← msw (R1 * R2)

● Divide Operation– Quotient in LO, Remainder in HI


Add, Subtract



R1 ← R2 + R3

Multiply, Divide



R1 ← R2 + 6

HI ← msw (R1 * R2)

Logical AND, ANDI, OR, ORI, XOR, XORI, NOR

OR R1, R2, 0xF R1 ← R2 | SE(0xF)

MIPS-I Control Transfer InstructionsMnemonics Example Meaning

ConditionalBranch

BEQ, BNE

Jump J, JR

Jump and Link

JAL, JALR

System Call

SYSCALL


ConditionalBranch

BEQ, BNE

Jump J, JR

Jump and Link

JAL, JALR

System Call

SYSCALL

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16


ConditionalBranch

BEQ, BNE

Jump J, JR J target26PC ← PC31-28 ||

target26 || 00

Jump and Link

JAL, JALR

System Call

SYSCALL

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16


ConditionalBranch

BEQ, BNE


target26 || 00

Jump and Link

JAL, JALR JALR R2 R31 ← PC + 4PC ← R2

System Call

SYSCALL

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16


ConditionalBranch

BEQ, BNE


target26 || 00

Jump and Link

JAL, JALR JALR R2 R31 ← PC + 4PC ← R2

System Call

SYSCALL SYSCALL

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16


ConditionalBranch

BEQ, BNEBGEZ, BLEZBLTZ, BGTZ

BEQ R2, R3, -16 If R2 == R3;PC ← PC + 4 -16


ConditionalBranch

BEQ, BNEBGEZ, BLEZBLTZ, BGTZ

BEQ R2, R3, -16 If R2 == R3;PC ← PC + 4 -16

PC Relative Addressing


ConditionalBranch

BEQ, BNE


target26 || 00

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16

J 0x475


ConditionalBranch

BEQ, BNE


target26 || 00

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16

J 0x475

6 bits 26 bits

op Offset added to PC

J Format


ConditionalBranch

BEQ, BNE


target26 || 00

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16

J 0x475

0 1 0 1 0 0 ... ... ... ... .... .... ... 0 1 0 0 0 1 1 1 0 1 0 1

22831

0 1 0 1PC before J

PC after J 0 0

27 1 0


ConditionalBranch

BEQ, BNE


target26 || 00

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16

J 0x475

JR R2 PC ← R2


ConditionalBranch

BEQ, BNE


target26 || 00

Jump and Link

JAL, JALR JAL target26 R31 ← PC + 4PC ← R2

System Call

SYSCALL SYSCALL

If R2 == R3;PC ← PC + 4 -16

BEQ R2, R3, -16

JALR R2

MIPS Instruction Formats

● R-type.

● I-type.

● J-type

6 bits 5 bits 5 bits 5 bits 6 bits5 bits

op rs rt rd shamt funct

6 bits 5 bits 5 bits 16 bits

op rs rt immediate

6 bits 26 bits

op Offset added to PC

op: Opcode (class of instruction). Eg. ALUfunct: Which subunit of the ALU to activate?

OP rt, rs, IMM

OP rd, rs, rt

OP LABEL

Addressing Modes● How are the locations of operands and results

specified in instructions?

MIPS-I Instruction Set● Addressing Modes

– Immediate, Register (for Arithmetic and Logic instructions)

– Absolute (for Jumps)

– Base-displacement (for Loads, Stores)

– PC relative (for conditional branches)

Addressing Mode Examples

Addressing Modes

ADD R3, R1, R2ADD R3, R1, R2 R3 = R1 + R2

12421

...

R0R1

R2

145R3R4

R5

Register File

Addressing Modes

● Register Addressing Mode– Operand is in the specified general purpose

register

ADD R3, R1, R2ADD R3, R1, R2 R3 = R1 + R2

12421

...

R0R1

R2

145R3R4

R5

Register File

Addressing Modes

ADD R3, R1, #13ADD R3, R1, #13 R3 = R1 + 13

12421

...

R0R1

R2

137R3R4

R5

Register File

Addressing Modes

ADD R3, R1, #13ADD R3, R1, #13 R3 = R1 + 13

● Immediate Addressing Mode– Operand is a constant value specified inside the

instruction.

12421

...

R0R1

R2

137R3R4

R5

Register File

Addressing Modes

ADD R3, R1, (R2)ADD R3, R1, (R2) R3 = R1 + M(0x104)

1240x104

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, R1, (R2)ADD R3, R1, (R2) R3 = R1 + M(0x104)

● Register Indirect Addressing Mode– Memory address of operand is in the specified

general purpose register.

1240x104

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, R1, 4(R2)ADD R3, R1, 4(R2) R3 = R1 + M(0x100 + 4)

1240x100

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, R1, 4(R2)ADD R3, R1, 4(R2) R3 = R1 + M(0x100 + 4)

● Base Displacement Addressing Mode– Memory address of operand is calculated as the

sum of value in specified register and specified displacement

1240x100

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Can be used instead of Register indirect addressing mode.

Addressing Modes

ADD R3, R1, (104)ADD R3, R1, (104) R3 = R1 + M(0x104)

1240x100

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, R1, (104)ADD R3, R1, (104) R3 = R1 + M(0x104)

● Absolute Addressing Mode– Memory address of operand is specified directly in

the instruction

1240x100

...

R0R1

R2

168R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, R1, (R2, R4)ADD R3, R1, (R2, R4) R3 = R1 + M(R2+R4)

1240x100

...

R0R1

R2

0x08

379R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

R2: Base of an arrayR4: Index

Addressing Modes

ADD R3, R1, (R2, R4)ADD R3, R1, (R2, R4) R3 = R1 + M(R2+R4)

● Indexed Addressing Mode– Memory address of operand is calculated as sum

of contents of 2 registers

1240x100

...

R0R1

R2

0x08

379R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

R2: Base of an arrayR4: Index

Addressing Modes

ADD R3, R1, @(R2)ADD R3, R1, @(R2) R3 = R1 + M(M(R2))

1240x40

...

R0R1

R2

0x08

379R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

0x104 0x40

Addressing Modes

ADD R3, R1, @(R2)ADD R3, R1, @(R2) R3 = R1 + M(M(R2))

● Memory Indirect Addressing Mode– A memory location is used as a pointer to the

value in another location in memory

1240x40

...

R0R1

R2

0x08

379R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

0x104 0x40

Addressing Modes

ADD R3, (R1)+ADD R3, (R1)+R3 = R3 + M(R1)R1 = R1 + d

0x1000x104

...

R0R1

R2

17R3R4

R5

Register File

199

172

44255 0x108

0x104

0x100...

...MEMORY

Addressing Modes

ADD R3, (R1)+ADD R3, (R1)+R3 = R3 + M(R1)R1 = R1 + d

● Auto-Increment Addressing Mode– Increment the value inside a register after the

operation is completed.

0x1000x104

...

R0R1

R2

17R3R4

R5

Register File

199

172

44255 0x108

0x104

0x100...

...MEMORY

Useful for stepping through arrays within a loop.

Addressing Modes

ADD R3, -(R1) ADD R3, -(R1) R1 = R1 – dR3 = R3 + M(R1)

-

0x1000x104

...

R0R1

R2

99R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

271

Addressing Modes

ADD R3, -(R1) ADD R3, -(R1) R1 = R1 – dR3 = R3 + M(R1)

-

● Auto-Decrement Addressing Mode– Decrement the value inside a register before the

operation is completed.

0x1000x104

...

R0R1

R2

99R3R4

R5

Register File

172

44255 0x108

0x104

0x100...

...MEMORY

PUSH/POP operations 271

Addressing Modes

ADD R3, 100(R1)[R3]ADD R3, 100(R1)[R3] R3 = R3 + M(100 + R1 + R3*d)

0x40

...

R0R1

R2

3R3R4

R5

Register File

172

44255 0x108

10

0x104

0x100...

...MEMORY

0x100 0x40

0x10C

13

Addressing Modes

ADD R3, 100(R1)[R3]ADD R3, 100(R1)[R3] R3 = R3 + M(100 + R1 + R3*d)

● Scaled Addressing Mode– Memory address of operand is calculated as sum

of contents of 2 registers

0x40

...

R0R1

R2

3R3R4

R5

Register File

172

44255 0x108

10

0x104

0x100...

...MEMORY

0x100 0x40

0x10C

13

Addressing Modes

JMP loopJMP loop PC = PC – 16

Loop: ADD ... XOR ... AND ... SUB ... JMP

0x100

0x104

0x108

0x112

0x116

Addressing Modes

JMP loopJMP loop PC = PC – 16

● PC Relative Addressing Mode– The operand address is specified as a

displacement from the PC value (i.e., from the address of the instruction itself)

Loop: ADD ... XOR ... AND ... SUB ... JMP

0x100

0x104

0x108

0x112

0x116

Addressing ModesAdd R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2]

Addressing ModesAdd R1, R2, R3 Regs[R4] <- Regs[R3] + Regs[R2] Register


Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5


Add R4, R3, #5 Regs[R4] <- Regs[R3] + 5 Immediate



Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1]]

Add R4, R3, 100(R1)




DisplacementAdd R4, R3, 100(R1)





Regs[R4] <- Regs[R3] + Mem[Regs[R1]]

Add R4, R3, (R1)






Register IndirectAdd R4, R3, (R1)







Regs[R4] <- Regs[R3] + Mem[0x475]Add R4, R3, (0x475)







Regs[R4] <- Regs[R3] + Mem[0x475] AbsoluteAdd R4, R3, (0x475)








Regs[R4] <- Regs[R3] + Mem[Mem[R1]]

Add R4, R3, @(R1)









Memory IndirectAdd R4, R3, @(R1)










Regs[R4] <- Regs[R3] + Mem[100 + PC]

Add R4, R3, 100(PC)











PC relativeAdd R4, R3, 100(PC)












Regs[R4] <- Regs[R3] + Mem[100 + Regs[R1] + Regs[R5] * 4]

Add R4, R3, 100(R1)[R5]













ScaledAdd R4, R3, 100(R1)[R5]














Regs[R4] <- Regs[R4] + Mem[R3]Regs[R3] <- Regs[R3] + d

Add R4, (R3)+















Auto IncrementAdd R4, (R3)+
















Regs[R3] <- Regs[R3] - dRegs[R4] <- Regs[R4] + Mem[R3]

Add R4, -(R3)
















Regs[R3] <- Regs[R3] - dRegs[R4] <- Regs[R4] + Mem[R3]

Auto DecrementAdd R4, -(R3)

Addressing Modes● Which ones should a new architecture support?● What should be size of the displacement?● What should be size of the immediate field?

Addressing Modes● Which ones should a new architecture support?● What should be size of the displacement?● What should be size of the immediate field?● Benchmarks: GCC, Particle simulations

(Physics, Chemistry), Large databases, Video encoding/decoding

● Popular Choices:– Displacement, Immediate, Register Indirect

– 12 – 16b

Module Outline● Instruction classes.● MIPS-I ISA.● Addressing modes● High level languages, Assembly languages

and object code.● Subroutine and subroutine call.● Translating and starting a program.

Extra Slides

MIPS-I Data Transfer Instructions


Load LB, LBU, LH, LHU, LW, LUI

LB R2, 4(R3)

LH R2, 4(R3)

LW R2, 4(R3)

LBU R2, 4(R3)

LUI R2, 4(R3)

.........

...0x2D8A107F 0x104

Memory

0x100R3

0x0000 107FR2

0000 0000 0000 0000 0001 0000 0111 1111

R215-0← Mem(R3 + 4)15-0

R231-16← Sign Extension

MIPS-I Data Transfer Instructions

● L: Load● S: Store● M: Move from/to HI/LO


Load LB, LBU, LH, LHU, LW, LUI

LW R2, 4(R3) R2 ← Mem(R3 + 4)

Store SB, SH, SW SB R2, -8(R4) Mem(R4 - 8) ← R2

Move MFHI, MFLO, MTHI, MTLO

MFHI R1 R2 ← HI

● B: Byte (8b), H: Half Word (16b), W: Word (32b)

● U: Upper● I: Immediate


Add, Subtract



R1 ← R2 + R3

Multiply, Divide



R1 ← R2 + 6

HI ← msw (R1 * R2)

● Divide Operation– Quotient in LO, Remainder in HI

x86 (IA-32) Instruction Encoding

InstructionPrefix

Opcode ModR/MScale,Index

BaseDisplace

mentImmediate

Up to four prefixes

(1 byte each)

1, 2 or 3B 1B(if needed)

1B(if needed)

0,1,2, or 4B(if needed)

0,1,2, or 4B(if needed)

x86 and x86-64 instruction formatPossible instructions 1 to 18 bytes long

REP MOVSB

ISA – Examples

Arithmetic Example● C code:

f = (g + h) - (i + j);

– {f,g,h,i,j} in {$s0,$s1,$s2,$s3,$s4}

● Compiled MIPS code:

add $t0, $s1, $s2

add $t1, $s3, $s4

sub $s0, $t0, $t1

R-format Example

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

op rs rt rd shamt funct

6 bits 6 bits5 bits 5 bits 5 bits 5 bits

I-format Example

addi $t0, $s1, 10

addi $s1 $t0 10

0 17 8 10

001000 10001 01000 0000 0000 0000 1010

001000100010100000000000000010102 = 2228000A16

op rs rt constant or address

6 bits 5 bits 5 bits 16 bits

M2 – Instruction Set...

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