8085 INTERRUPTS

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INTERRUPTS When a microprocessor is interrupted, it stops

executing its current program and calls a special routine which “services” the interrupt

The event that causes the interruption is called Interrupt

The special routine executed to service the interrupt is called ISR - Interrupt Service Routine/Procedure

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INTERRUPT CLASSIFICATION

Hardware Interrupt An interrupt caused by an “External signal ”

Software Interrupt An interrupt caused by “Special Instruction”

Maskable Interrupts Can be delayed or Rejected Non-Maskable Interrupts Can not be delayed or Rejected

(Service must) Vectored Where the subroutine starts is referred to as

Vector Location Non-vectored The address of the service routine needs to

be supplied externally by the device3

8085 INTERRUPTS

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8085

TRAPRST7.5

RST6.5

RST 5.5INTR

INTA

The ‘EI’ instruction is a one byte instruction and is used to Enable the non-maskable interrupts.The ‘DI’ instruction is a one byte instruction and is used to Disable the non-maskable interrupts.

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Interrupt Name Maskable Vectored

INTR Yes No

RST 5.5 Yes Yes

RST 6.5 Yes Yes

RST 7.5 Yes Yes

TRAP No Yes

INTERRUPT VECTORS & THE VECTOR TABLE

An interrupt vector is a pointer to where the ISR is stored in memory.

All interrupts (vectored or otherwise) are mapped onto a memory area called the Interrupt Vector Table (IVT). The IVT is usually located in (0000H - 00FFH).

Vector Address = Interrupt number * 8

6

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Interrupt Name Calculation Vector

Address

INTR -- --

TRAP ( RST 4.5) 4.5x8=36 0024H

RST 5.5 5.5x8=44 002CH

RST 6.5 6.5x8=52 0034H

RST 7.5 7.5x8=60 003CH

8085 INTERRUPTS SUMMARY

Interrupt Name

Triggering Method

Priority

Maskable

Masking Method

Vector Address

TRAPRST 4.5

Edge & Level

Sensitive

1st Highes

tNo None 0024H

RST 7.5Edge

Sensitive2nd Yes

DI / EISIM

003CH

RST 6.5 Level

Sensitive3rd Yes

DI / EISIM

0034H

RST 5.5Level

Sensitive4th Yes

DI / EISIM

002CH

INTRLevel

Sensitive5th

LowestYes

Pin

( INTR & INTA)

--

8

SOFTWARE INTERRUPT

The 8085 recognizes 8 RESTART instructions: RST n ( RST0 - RST7)

Each of these would send the execution to a redetermined hard-wired memory location:

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Restart Instruction

Vector Address

RST 0 CALL 0000H

RST 1 CALL 0008H

RST 2 CALL 0010H

RST 3 CALL 0018H

RST 4 CALL 0020H

RST 5 CALL 0028H

RST 6 CALL 0030H

RST 7 CALL 0038H

THE 8085 MASKABLE/VECTORED INTERRUPT PROCESS

1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every instruction.

3. If there is an interrupt, and if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop.

4. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.

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THE 8085 MASKABLE/VECTORED INTERRUPT PROCESS

5. When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack.

6. The microprocessor jumps to the specific service routine.

7. The service routine must include the instruction EI to re-enable the interrupt process.

8. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted. 11

SIM VALUE MUST BE LOADED IN ACCUMULATOR 12

SD

OS

DE

XX

XR

7.5

MS

EM

7.5

M6.

5M

5.5

01234567

RST5.5 Mask

RST6.5 MaskRST7.5 Mask

} 0 - Available1 - Masked

Mask Set Enable0 - Ignore bits 0-21 - Set the masks according to bits 0-2

Force RST7.5 Flip Flop to resetNot Used

Enable Serial Data0 - Disable1 - Enable

Serial Data OutEither 0 or 1

SIM – SERIAL INTERRUPT MASK

ExampleMSE Mask Set EnableRST 6.5 MaskRST 5.5 & 7.2 UnmaskRST FF Don’t ResetSerial Data Igonered

13S

DO

SD

EX

XX

R7.

5M

SE

M7.

5M

6.5

M5.

5

0 1 00000 1

Contents of accumulator are: 0AH

EI ; Enable interrupts including INTRMVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5SIM ; Apply the settings RST masks

ExampleMSE Mask Set DisableRST FF ResetSerial Data EnableSerial Data output is 0

14S

DO

SD

EX

XX

R7.

5M

SE

M7.

5M

6.5

M5.

5

1 0 01010 0

Contents of accumulator are: 54H

15

SD

IP

7.5

P6.

5P

5.5

IEM

7.5

M6.

5M

5.5

01234567

RST5.5 Mask

RST6.5 MaskRST7.5 Mask

} 0 - Available1 - Masked

Interrupt EnableValue of the Interrupt EnableFlip Flop

Serial Data In

RST5.5 Interrupt Pending

RST6.5 Interrupt PendingRST7.5 Interrupt Pending

RIM – READ INTERRUPT MASK

Set – 1Reset - 0

COPIES THE STATUS OF THE INTERRUPTS INTO THE ACCUMULATOR

ExampleInterrupt EnableRST 5.5 & 6.5 MaskedRST 7.5 Pending Serial Input Data is 0

16S

IDP7.5

P6.5

P5.

5IE

M7.

5M

6.5

M5.

5

0 1 10010 1

Contents of accumulator are: 4BH