DRCLVS20130326
DRC (Design Rule Check)LVS (Layout Versus schematic)Post-Simulation*/61
*/61
DRCDesign Rule CheckLVSLayout Versus Schematic */61
schematicPre-simDRCLVSPost-simlayout*/61
DRC Design Rule Check*/61
DRC DRC DRC
DRC
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Design RuleDesign RuleDesign rulerule*
DRC*
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*
DRCMentor CalibreCadence DraculaSynopsys Hercules*/61
Calibre DRC1.DRC2.3.4.Calibre 5.Check6.7.5*/61
DRCDRCSmicDR2R_cal40_log_ll_sali_p1mx_1tm_121825.drc/home/smic/SMIC40nmPDK/SPDK40LL_1125_CDS_Prev1.3.3/SPDK40LL_1125_1TM_CDS_Prev1.3.3/smic40ll_1125_1tm_cds_1P7M_2011_10_25_Prev1.3.3/Calibre/DRC*/61
Cadence cd fsk ()source /opt/demo/cdsmmsim7_cal11.envicfb&
*/61
*/61ppt
Calibre1/2 */61
Calibre1/2 /home/smic/SMIC40nmPDK/SPDK40LL_1125_CDS_Prev1.3.3/SPDK40LL_1125_1TM_CDS_Prev1.3.3/smic40ll_1125_1tm_cds_1P7M_2011_10_25_Prev1.3.3/Calibre/DRC*/61
Calibre1/2 */61
Calibre1/2 */61
Calibre1/2 */61
RUNDRCCalibre2/2 */61
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LVS Layout Versus schematic*/61
DRCLVS*/61
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LVS LVS LVS */61
LVS1.LVS2.3.Calibre4.5.6.7.5*/61
LVSLVSSmicSP1R_cal40_LL_sali_p1mtx_11182533.lvs/home/smic/SMIC40nmPDK/Calibre/LVS/*/61
CadenceLVS*/61
*/61
Calibre1/2 */61
/home/smic/SMIC40nmPDK/SPDK40LL_1125_CDS_Prev1.3.3/SPDK40LL_1125_1TM_CDS_Prev1.3.3/smic40ll_1125_1tm_cds_1P7M_2011_10_25_Prev1.3.3/Calibre/LVS*/61
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schematicFiles*/61
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RUNLVS*/61
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Post Simulation*/61
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Calibre1/2 */61
/home/pdk/smic40llrf_1125_2tm_cds_1P8M_2012_10_30_v1.4/Calibre/LVS/SmicSP1RR1R_cal40_LLRF_sali_plmtx_11182533_V1.4_1R_XRC.lvs*/61
*/61
netlistspectrenamelayout*/61
RUNPEX*/61
***.netlistincludespectre.scsinclude*/61
*.netlistInclude library *** section ttEnd endsection tt endlibrary *******/61
symbolDesign->Save asView Namespectrepost simulationsymbolmodel.netlist.scs file*/61
symbolCDF */61
Component ParametersAddnameModelpromptModel NameOK*/61
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END*/61
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