设计规则检查 DRC 及一致性检查 LVS 工具
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设计规则检查 DRC 及一致性检查 LVS 工具. 2013 年 03 月 26 日. 主要内容. 设计规则检查 DRC (Design Rule Check) 一致性检查 LVS (Layout Versus schematic) 后仿真（ Post-Simulation ） 演示. 版图绘制要根据一定的设计规则来进行，也就是说一定要通过 DRC （ Design Rule Check ）检查。 - PowerPoint PPT Presentation
Transcript of 设计规则检查 DRC 及一致性检查 LVS 工具
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DRCLVS20130326
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DRC (Design Rule Check)LVS (Layout Versus schematic)Post-Simulation*/61
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DRCDesign Rule CheckLVSLayout Versus Schematic */61
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schematicPre-simDRCLVSPost-simlayout*/61
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DRC Design Rule Check*/61
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DRC DRC DRC
DRC
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Design RuleDesign RuleDesign rulerule*
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DRC*
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DRCMentor CalibreCadence DraculaSynopsys Hercules*/61
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Calibre DRC1.DRC2.3.4.Calibre 5.Check6.7.5*/61
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DRCDRCSmicDR2R_cal40_log_ll_sali_p1mx_1tm_121825.drc/home/smic/SMIC40nmPDK/SPDK40LL_1125_CDS_Prev1.3.3/SPDK40LL_1125_1TM_CDS_Prev1.3.3/smic40ll_1125_1tm_cds_1P7M_2011_10_25_Prev1.3.3/Calibre/DRC*/61
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Cadence cd fsk ()source /opt/demo/cdsmmsim7_cal11.envicfb&
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Calibre1/2 */61
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Calibre1/2 /home/smic/SMIC40nmPDK/SPDK40LL_1125_CDS_Prev1.3.3/SPDK40LL_1125_1TM_CDS_Prev1.3.3/smic40ll_1125_1tm_cds_1P7M_2011_10_25_Prev1.3.3/Calibre/DRC*/61
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Calibre1/2 */61
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LVS Layout Versus schematic*/61
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DRCLVS*/61
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LVS LVS LVS */61
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LVS1.LVS2.3.Calibre4.5.6.7.5*/61
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LVSLVSSmicSP1R_cal40_LL_sali_p1mtx_11182533.lvs/home/smic/SMIC40nmPDK/Calibre/LVS/*/61
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CadenceLVS*/61
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schematicFiles*/61
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RUNLVS*/61
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Post Simulation*/61
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netlistspectrenamelayout*/61
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RUNPEX*/61
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***.netlistincludespectre.scsinclude*/61
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*.netlistInclude library *** section ttEnd endsection tt endlibrary *******/61
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symbolDesign->Save asView Namespectrepost simulationsymbolmodel.netlist.scs file*/61
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symbolCDF */61
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Component ParametersAddnameModelpromptModel NameOK*/61
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END*/61
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