What Is State?

What Is State?

Prof. Chung-Ta KingDepartment of Computer

ScienceNational Tsing Hua University

CS1103 電機資訊工程實習

(Contents from http://ai-depot.com/FiniteStateMachines/FSM-Background.html,www.dcs.shef.ac.uk/~ahw/comp_arch/L3.ppt )

How many “states” can a motorcycle

have?

How many “states” can a motorcycle

have?

這是什麼爛問題 ?這是什麼爛問題 ?

State 有不同的類型 !• 新、舊• 運作良好、堪用、待修、報廢• 停止、行進、牽行• ...

State 有不同的類型 !• 新、舊• 運作良好、堪用、待修、報廢• 停止、行進、牽行• ...

機車的「運作狀態」有幾種 ?機車的「運作狀態」有幾種 ?

A Better Question

熄火靜止、熄火行進、發動靜止、發動行進

熄火靜止、熄火行進、發動靜止、發動行進

5

不同「運作狀態」之間如何轉換 ?

State transition

熄火靜止熄火靜止

熄火行進熄火行進

發動靜止發動靜止

發動行進發動行進

Finite state machineFinite state machine

推動推動

停止停止

發動發動

熄火熄火

啟動啟動

煞車停止煞車停止

發動發動

熄火熄火

6

Outline

What is finite state machine? Finite state machine for program

modeling The important concept of “state”

Finite state machine for circuit control Finite state machine for embedded

control Finite state machine for recognition Modeling with finite state machine

7

Finite State Machines (FSM)

or Finite State Automation (FSA) Models of behaviors of a system or object, with a

limited number of defined conditions or modes, where modes change with circumstance

4 main elements: States: define behavior and may produce actions State transitions: move from one state to

another Rules (or conditions): must be met to allow a

state transition Input events: externally or internally generated;

may trigger rules and lead to state transitions An initial state and a current state

Good for representation and modeling sequences of behaviorsGood for representation and modeling sequences of behaviors

8

Outline





9

Consider the Program

main(){ i=5; j=6; k=0; k=i+j; if (k>0) i=0; else j=0;}

Can this program be modeled with a FSM?

What is its “state”?What is its “state”?

10

Initial State


main(){ i=5; j=6; k=0; k=i+j; if (k>0) i=0; else j=0;} CPUCPU

6

5

0

jj

ii

kk

MemoryMemory

11

State 1



6

5

11

jj

ii

kk

MemoryMemory

12

State 2



6

0

11

jj

ii

kk

MemoryMemory

13

State 3



0

5

11

jj

ii

kk

MemoryMemory

14

FSM Representing the Program

11

22

33

44

k=i+jk=i+j

k>0k>0

k<=0k<=0

VV

15

Compare with Flow Chart

k=i+j

k>0

i=0 j=0

yesyes nono

16

Some Questions

Can FSM be used to represent any program? Any algorithm?

What is the “state” of a program/process? Or a computer? Why is this important?系統更新的回復點電腦休眠之後回復原來畫面 Context switch Interrupt and resume

Is there a machine that can model any computation? Turing machine

17

State of a Procedure?

Fibonacci number (iterative version) unsigned int fib(unsigned int n) { unsigned int i=1, j=0, k, t; for (k=1; k<=n; k++) { t=i+j; i=j; j=t; } return j; }

What need to be stored when the procedure is suspended and later resumed (as if nothinghad happened)?

What need to be stored when the procedure is suspended and later resumed (as if nothinghad happened)?

18

Why Is It Important?

Fibonacci number (recursive version)

unsigned int fib(unsigned int n){ unsigned int i=n-1, j=n-2; if (n<2) return n; else return fib(i) + fib(j); }

What happens when n, i, and j eachrefer to the same memory location across procedure calls?

What happens when n, i, and j eachrefer to the same memory location across procedure calls?

19

How to Solve for Recursion?

If we could save the “state” of the calling procedure in a safe/separate place that the called procedure will not overwrite, then the recursion can be executed correctly

Big idea: “procedure state” in run-time stack Allocate the “state” of each called procedure in

the run-time stack procedure frame All references to the “state” go to the stack Each invocation will push “state” down the stack How to write assembly code to do that?

Memory reference relative to stack pointer Chapter 8 of CS2422

20

Summary: A View of a “State”

Storage contents of the code/system that must be saved away when the code/system is suspended and resumed later, as if nothing had happened State of a procedure on procedure calls State of a thread/process on context switch

make time-sharing possible State of a process on migration to another

PC State of a computer on error recovery State of a computer on hibernation ...

21

Implication of the View

We can do anything as long as we do not disturb the “state”

z = x * 3.1412;if (z > 10) j = j + k;

Since FP multiplication takes a long time, can we execute the addition at the same time? out-of-order, speculative

22

Outline





23

FSM Also Good for Hardware

…

ALU

MemoryRegister

AXBX

address

01 0000001 1000010 11 0000001 1000110

…

a

b

x

01 1000011 0000001

MOV AX, aADD AX, bMOV x, AX

data

PCIR

PC: program counterIR: instruction register

Processor

Controller

clock

24

Step 1: Fetch (MOV AX, a)

…

ALU

MemoryRegister

AXBX

address

01 0000001 1000010 11 0000001 1000110

…

a

b

x

01 1000011 0000001


data

PC

000011101 0000001 1000010

IR

Controller

clock

25

Step 2: Decode (MOV AX,a)

…

ALU

MemoryRegister

AXBX

address

01 0000001 1000010 11 0000001 1000110

…

a

b

x

01 1000011 0000001


data

PCIR

000011101 0000001 1000010

Controller

clock

26

Step 3: Execute (MOV AX,a)

…

ALU

MemoryRegister

AXBX

address

00000000 000000001

01 0000001 1000010 11 0000001 1000110

…

a

b

x

01 1000011 0000001


data

PCIR

000011101 0000001 1000010

Controller

clock

00000000 00000001

27

Computer Hardware = Datapath + Control

RegistersCombinational Functional Units (e.g., ALU)Busses

FSM generating sequences of control signalsInstructs datapath what to do next

Qualifiers

Control

Control

Datapath

State

ControlSignalOutputs

QualifiersandInputs

Concept of the State Machine

28

FSM of the Computer

For this highly simplified computer, the controller can be described by a FSM

FetchFetch

ADDADD MOVMOV JNGJNG......

DecodeDecode

if (ADD)if (ADD) if (MOV)if (MOV) if (JNG)if (JNG)

Each state will generate certain control signalsto control the datapath

Each state will generate certain control signalsto control the datapath

29

Internal Structure of Controller

Instruction RegInstruction Reg EFLAGSEFLAGSALU

zero,carry,overflow,...zero,carry,overflow,...

State RegisterState Register

To datapathTo datapathOutputOutput

Next state (state transition)Next state (state transition)

ControllerController

Combinationalcircuit

Combinationalcircuit

ClkClk

30

Combinational & Sequential Logic

Combinational logic does not have memory It generates output solely according to the

input and does not care about history Often, we need a different reaction on the

same input depending on the current state E.g.

Current state is 7 and input is 1, the new state and output are 8

Current state is 15 and input is 1, the new state and output are

To make the new state depends on the previous state, we need memory

31

Sequential Logic and FSM

Computers are made of sequential logic blocks Truth tables are used to design combinational

logic, but can’t be used for sequential logic Finite state machines (FSM) are used

instead FSM describes a sequential logic block in

terms of: Set of states, State transition function (defined on current

state and input), and Output function (defined on current state and

input, or on current state only)

32

Two Types of FSMs

Differ in how outputs are produced Moore Machine:

Outputs are independent of the inputs, i.e. outputs are produced from within the state of the state machine

Mealy Machine: Outputs can be determined by the present

state alone, or by the present state and the present inputs, i.e. outputs are produced as the machine makes a transition from one state to another

Any Moore machine can be turned into a Mealy machine (and vice versa)

33

Moore Machine

State 2x,y

State 1q,r

a,b

i,j

Input condition thatmust exist in orderto execute thesetransitions fromState 1

Output condition thatresults from being ina particular present state

The Moore State Machineoutput remains the same aslong as the state machineremains in that state.The output can be arbitrarilycomplex but must be thesame every time themachine enters that state.

34

Mealy Machine

State 2

State 1 a,b q,r

i,jx,y

Input condition thatmust exist in orderto execute thesetransitions fromState 1

Output condition thatresults from being ina particular present state

The Mealy State Machine generates outputs based on: The Present State, and The Inputs to the M/c.So, same state can generate many different patterns of output signals, depending on the inputs.Outputs are shown on transitions since they are determined in the same way as is the next state.

35

Outline





36

Safety Belt Control

We want to design a controller for safety belt If the seat is seated and the belt is not

buckled within a set time, a buzzer will sound until the belt is buckled event driven

Inputs: seat sensor, timer, belt sensor Output: buzzer, timer System: specialized computer for reacting

according to eventssensed by the sensors

37

FSM for Event-driven Systems

idle

buzzer seated

belted

no seat/-

seat/timer onno belt and no timer/-

no belt/timer on

belt/-belt/

buzzer off

Belt/buzzer on

no seat/-

no seat/buzzer off

38

C Code Structure

Current state is kept in a variable State table is implemented as a switch

Cases define states States can test inputs and produce outputs

while (TRUE) {switch (state) {

case state1: …}

}

Switch is repeatedly evaluated by while-loop

39

C Implementation

#define IDLE 0#define SEATED 1#define BELTED 2#define BUZZER 3switch (state) {case IDLE: if (seat)

{ state = SEATED; timer_on = TRUE; }break;

case SEATED: if (belt) state = BELTED;else if (timer) state = BUZZER;

break;…

}

40

Another Example

A B

C D

in1=1/x=a

in1=0/x=b

r=0/out2=1

r=1/out1=0

s=1/out1=1

s=0/out1=0

41

C State Table

switch (state) {case A: if (in1==1) { x = a; state = B; } else { x = b; state = D; }break;

case B: if (r==0) { out2 = 1; state = B; }

else { out1 = 0; state = C; }break;

case C: if (s==0) { out1 = 0; state = C; }

else { out1 = 1; state = D; }break;

42

Outline





43

FSM as Recognizer/Translator

Outputs a ‘0’ if an even # of 1’s is received and outputs a ‘1’ otherwise

What is state? Two states: whether an even # of 1s have

been received, or an odd # of 1s have been receivedMealy Machine

0/0

Even

Odd

1/11/0

0/1

Output

Input

0Even

11

0

[0]

Odd [1]

Output

Input

Moore Machine

44

y recognizer of L

yes, y in L

no

Finite State Machines

Language recognizer (acceptor)

Problem solver

problems strings (languages) machines answers

45

FSM as Recognizer/Translator

How to recognize words in a document? Assume characters in the document are

input sequentially What is state?

State 1State 1 State 2State 2

[a-z, A-Z][a-z, A-Z]

others/[word]others/[word]

[a-z, A-Z][a-z, A-Z]othersothers

46

Example

A FSM that outputs a ‘1’ whenever it receives a multiple of 3 # of 1’s on a serial input

Relevant information to solve the problem:(A) A multiple of 3 # is received(B) A non-multiple of 3 # is received

Questions to consider:(1) How do we go from (A)(B)

Ans.: If a ‘0’ is received(2) How do we go from (B)(A)

Ans.: Not clear; need to consider(B1): 3y+1 # of 1’s received.(B2): 3y+2 # of 1’s received.

y is an integer 0

47

Transitions between 3 classes of information: (A) (B1) (B2) (A)

They can be considered states of the FSM:

1 received 1 received 1 received

i=0

i=1

i=2 i=2[0]

i=1[0]

i=0[1]

Reset Reset0/1

0/0

0/0

1/0

1/1

00

10

01 1

1

1

0

0

0

Moore MachineMealy Machine

Input

Output

1/0

Example

48

Outline





49

Scenario 1

入侵偵測系統：某一房間的麥克風偵測到有不正常的聲音，即提高偵測頻率，並通知房間內的攝影機追蹤聲音的來源，且將影像傳到管理員手機。

同時，通知走廊及其他房間內的麥克風提高偵測頻率，攝影機追蹤移動物體。

What are the states? What is the FSM?

50

Scenario 2

大富翁： What are the states? How states transit?

Are the transitions deterministic? What are the expected outcomes?

Markov chain, stochastic process, ...

51

Quiz

每天早上小明的爸爸開車送他到學校，然後到公司上班。小明的媽媽處理家務。

每天下午下課時，小明的媽媽用機車來接他，並送他去補習。

小明補完習，媽媽再來接他回家。爸爸下班時間比較不固定，他直接開車回家。

What are the states? What is the FSM?

What are the states for 小明？ hierarchy

What Is State?

Documents

Transcript of What Is State?