I HC QUC GIA THNH PH H CH MINH

TRNG I HC BCH KHOA

KHOA KHOA HC K THUT MY TNH

BO CO ASSIGNMENT 2THIT K B X L N CHU K( SINGLE CLOCK CYDLE) N GIN VI NGN NG M T PHN CNG(HDL)

GVGD:

Lp: MT13KTTN

Nhm:

L Tn Long

- 51302134

Hunh Quang Bo

- 51300225

Nguyn Phan Thnh t - 51300791

Nguyn L Minh Khi - 51301906Tp. H Ch Minh, Thng 5/2015Li m uKhc vi CPU, thut ng ALU c l vn cn xa l i vi nhiu ngi s dng my tnh. Khi nhc n CPU, ngi ta c th hnh dung ngay n mt b no nm trung tm, chuyn nhn trch nhim x l v ra lnh, lm cho ng thit b ri rc v ngha tr thnh mt c my cht ch v v cng thng minh. C th ni vai tr v tm quan trng ca CPU i vi mt chic my tnh l iu khng th bn ci. Cn ALU th sao ?

ALU l mt trong nhng thnh phn chnh to nn CPU, l b x l c bn vi chc nng thc hin cc php ton s hc v logic. Hay ni cch khc, mun chic my tnh bit tnh, ta cn phi c ALU. iu cho thy rng, vic thit k mt chic my tnh s bt u t cng on thit k b ALU bi n l thnh phn c bn v v cng quan trng. Chnh v vy, ti Thit k b ALU n gin do nhm chng ti thc hin s gip mi ngi c ci nhn tng quan v cch hin thc mt b ALU, to tin cho nhng ai mong mun thit k cho ring mnh mt chic my tnh.

Mc d c s u t tm hiu cng nh s chun b v kin thc, tuy nhin trong qu trnh trnh by chc hn s c rt nhiu thiu xt. Rt mong nhn c s gp thng thn ca cc bn.

Nhm chng ti xin chn thnh cm n !

Mc lc4I.Gii thiu bi ton:

5II.c t chc nng , thnh phn cu to cc module:

51.Thnh phn cu to cc module:

72.c t chc nng:

73.nh gi, kim tra u im nhc im:

8III.Phn chia cng vic:

I. Gii thiu bi ton:Bi tp ln ny gip sinh vin hiu, phn tch, thit k b x l n chu k. Bn cnh cn gip sinh vin lm quen vi kit FPGA (DE2i-xxx), lm quen vi ngn ng m t phn cng (verilog).

Cho kin trc b x l n chu k (single clock cycle) nh s bn di.

II. c t chc nng , thnh phn cu to cc module:1. Thnh phn cu to cc module:a. Module chnh ( module): Module system: module cao nht trong phn cp thit k ca b x l Input: tn hiu clk, load, reset, output_sel SYS_clk: tn hiu clk.

SYS_reset: tn hiu reset.

SYS_load:tn hiu iu khin load t ngi dng

SYS_pc_val[0:7]: d liu c load vo thanh ghi PC SYS_output_sel[0:7]: tn hiu chn output cn hin thOutput: SYS_leds

SYS_leds[26:0]: hin th output

Module instruction memory: b nh lnh cha m my chng trnhInput: IMEM_PC[7:0]: a ch c truyn t thanh ghi PCOutput: IMEM_instruction[31:0]: m lnh tng ng vi a ch IMEM_PC

Module Register files: gii m thanh ghi.

Input: REG_address1[5:0]: a ch thanh ghi Rs REG_address2[5:0]: a ch thanh ghi Rt REG_address_wb[5:0]: a ch thanh ghi Rd REG_write_1: tn hiu iu khin cho php thc hin lu d liu vo thanh ghi Rd REG_data_in1[31:0]: d liu lu vo thanh ghi RdOutput: REG_data_out1: d liu thanh ghi Rs REG_data_out2: d liu thanh ghi Rt hoc d liu imm-16bit, imm-26bit.

Module ALU: b ALU n gin cha cc b php tnh bn trongInput:

ALU_control[3:0]: tn hiu dng la chn cc php ton trn ALU ALU_operand_1[31:0]: Ton hng 1 ALU_operand_2[31:0]: Ton hng 2Output: ALU_result: Kt qu sau khi tnh ton. ALU_status: Thuc tnh ca kt qu.

Module Data memory: vng nh d liu 256 x 32Input:

DMEM_address[31:0]: a ch ca b nh d liu. DMEM_data_in[31:0]: d liu lu vo b nh. DMEM_mem_write: tn hiu dng kch hot ch write. DMEM_mem_read: tn hiu dng kch hot ch read.Output:

DMEM_data_out[31:0]: d liu c c t b nh

Module Control unit: tn hiu iu khin cc lnh da vo opcode u vo.

Input: Opcode[5:0] : 6 bit u tin c ly t IMEM_instructionOutput: Control_signal[10:0]: 11 bit tn hiu iu khin cho ton h thng.

Module exception_handle: kim tra ngoi l

Input:

exception : ngoi l khi m lnh khng ng dng. ALU status [7:0]: ngoi l khi xy ra trn, chia cho 0, Output: check: tch cc khi xy ra ngoi l

b. Module ph:

Bn cnh cc module chnh, chng ti to ra mt s module ph h tr cho vic tnh ton. V d nh cc module thc hin php cng (adder), php dch bit (shift), m rng du (signextend), cc b mux dng la chn tn hiu, cc cng lun l,2. c t chc nng: S dng cc nt nhn (button) lm cc tn hiu Clk, Load, Reset

S dng 27 Led (18 Led , 9 Led xanh) hin th output.

S dng 8 switch (t 0 n 7) chn output cn hin th.

S dng 8 switch ( t 10 n 17) chn d liu load vo thanh ghi PC.

S dng LCD ng thi hin th output cng vi Led

B vi x l Single Cycle c thit k trn y s hot ng da vo tn hiu xung Clk cnh xung. Mi tn hiu xung Clk p ng s tng ng vi mt cu lnh c thc hin.

Nu pht hin tn hiu Reset, b vi x l s hot ng li t u.

1. Nu pht hin tn hiu Load, b vi x l s tin hnh Load d liu c nhp bng Switch vo thanh ghi PC.

3. Phn chia cng vic:

L Tn Long(51302134): thc hin cc module Control Unit, Data MemoryHunh Quang Bo(51300225): thc hin cc module Instruction Memory, ALUNguyn Phan Thnh t(51300791): thc hin cc module ph, module hin th bng LCD.Nguyn L Minh Khi(51301906): ghp ni cc module, hon thnh bo co.4 | Page3 | Thit k b ALU n gin