實驗目的

External I/O control

External I/O control

Contents

5-15.External I/O Control

5-15.1.實驗目的

5-15.2.實驗原理

5-15.2.1.About the GPIO unit

5-25.2.2.GPIO Overview

5-35.2.3.Programmer’s model

5-45.3.引導實驗

5-45.3.1.檔案說明

5-55.3.2.實驗步驟

5-175.4.實驗要求

5-185.5.問題與討論

5-185.6.參考文件

說明

1. 本實驗所需設備：ARM Integrator AP、CM、LM (Xilinx)、ARM Multi-ICE、麵包板、LED；本實驗所需軟體：ARM Developer Suite、Xilinx ISE。

2. 本實驗需用到LM中的FPGA。規劃LM的FPGA的方法在另一個實驗「ASIC Logic」中提及，故授課教師可依實際狀況將本實驗安排在「ASIC Logic」實驗之後。

5. External I/O Control

--Using the GPIO Unit to Control the External I/O Devices

5.1. 實驗目的

In this Lab, you will learn (1) the operation mechanism of a GPIO (General Purpose Input/Output) unit, (2) the method of connecting an external I/O device to the ARM Integrator Platform, and (3) how to employ the GPIO to control the external I/O device.

5.2. 實驗原理

5.2.1. About the GPIO unit

The GPIO (General Purpose Input/Output) unit is an AMBA slave module that connects to the APB. It has 16 bits of programmable input/output organized as two 8-bit ports, port A and port B. Pins of both ports can be configured as either inputs or outputs. The GPIO unit interface with input/output pad cells using a data input, data output and output enable line per pad. Figure 5-1 illustrates the GPIO interfaces, and Figure 5-2 shows the GPIO block diagram.

Figure 5-1. GPIO interfaces.

Figure 5-2. GPIO block diagram

5.2.2. GPIO Overview

GPIO provides 16 inputs/outputs organized as two 8-bit groups, port A and port B. The CPU reads and writes data and control/status information to and from GPIO via the AMBA APB interface. Each port has an associated data direction register and a data register.

Data direction register

The data direction register is 8 bits wide, and is programmed to select whether each individual input/output pin is configured as an input or an output.

Data register

The data register is 8 bits wide, and is used to read the value input on those GPIO lines that are configured as inputs, and to program the value output on those GPIO line that are configured as outputs.

AMBA APB interface

The AMBA APB groups narrow-bus peripherals to avoid loading the system bus, and provides an interface using memory-mapped registers which are accessed under programmed control.

The AMBA APB interface generates read and write decodes for accesses to the control register and data register for each input/output port.

5.2.3. Programmer’s model

The GPIO registers are shown in Table 5-1.

Table 5-1. GPIO register summary

GPIOPADDR is the port A data direction register. Bits set in GPIOPADDR will set the corresponding pin in PORT A to be an output. Clearing a bit configures the pin to be an input.

GPIOPBDDR is the port B data direction register. Bits cleared in GPIOPBDDR will set the corresponding pin in PORT B to be an output. Setting a bit configures the pin to be an input.

The base address of the PrimeCell GPIO is not fixed, and may be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

In this Lab, the GPIO unit is implemented in the FPGA of LM, and the base address of GPIO is selected as 0xC2100000.

Figure 5-3. Memory map of Logic Module

5.3. 引導實驗

In this Lab, you will implement a GPIO in the FPGA of the logic module. The port A and port B of the GPIO unit will be assigned to those FPGA pins that connected to the prototyping grids such that the ports of GPIO can be accessed via the prototyping grids on the logic module. You will use the GPIO to control the flashing of LEDs on a breadboard.

5.3.1. 檔案說明

The associated Verilog files include

AHBAPBSys.v

AHBAHBTop.v

AHB2APB.v

AHBDecoder.v

AHBDefaultSlave.v

AHBMuxS2M.v

AHBZBTRAM.v

APBIntcon.v

APBRegs.v

GPIO060.v

APBMuxP2B.v

You can find the Verilog files in the directory Codes/HW/Xilinx/GPIO/Verilog. Also, you can find a testbench for simulating the GPIO unit in the directory Codes/HW/Xilinx/GPIO/Testbench.

The associated software source codes can be found in the directory Codes/SW/GPIO.

The associated reference documents, such as ARM PrimeCell™ General Purpose Input/Output （PL060）Technical Reference Manual, the document of the LM PCB layout, can be found in the directory Doc/Ref.

5.3.2. 實驗步驟

1. Pin Assignment

We want the input/output ports of GPIO to be connected to the prototyping grids in the logic module, such that we can access the input/output ports of GPIO via the prototyping grids. From the document lm_xcv600e_revc.pdf (in “\Program Files\ARM\Logic Modules\LM-XCV600E\schematics\lm_xcv600e_revc.pdf”), you can find the schematic diagram of the LM PCB. Figure 5-4 shows part of the pin names of prototyping grids in the logic module, and Figure 5-5 shows the Bank-0 pin names of the FPGA. You can see that many Bank-0 pins of FPGA are wired to the prototyping grids in the logic module. You have to modify the file xxx.ucf（\Codes\HW\Xilinx\GPIO\PnR\AHBAHBTop.ucf）such that the pins of the GPIO are assigned to the appropriate pins of the FPGA that are connected to the prototyping grids. In the following, we will assign the port A of GPIO to row 2 of prototyping grid, and assign port B to row 3 of the prototyping grid.

Figure 5-4. Pin names of prototyping grids in the logic module

Figure 5-5. The Bank-0 pin names of the FPGA (XCV600E)

(2) Add the pin assignment into ***.ucf （AHBAHBTop.ucf）as following:

NETGPIO1XPA<0> LOC=b20;

NETGPIO1XPA<1> LOC=a21;

NETGPIO1XPA<2> LOC=b21;

NETGPIO1XPA<3> LOC=a22;

NETGPIO1XPA<4> LOC=b22;

NETGPIO1XPA<5> LOC=c22;

NETGPIO1XPA<6> LOC=d22;

NETGPIO1XPA<7> LOC=e22;

NETGPIO1XPB<0> LOC=a23;

NETGPIO1XPB<1> LOC=b23;

NETGPIO1XPB<2> LOC=c23;

NETGPIO1XPB<3> LOC=d23;

NETGPIO1XPB<4> LOC=e23;

NETGPIO1XPB<5> LOC=a24;

NETGPIO1XPB<6> LOC=b24;

NETGPIO1XPB<7> LOC=c24;

2. Logic Synthesis

(1) Start Xilinx ISE 6.1 from the start menu and then you will see Figure 5-6.

Figure 5-6

(2)Create a New Project

(a)Input the project name

(b)Assign the project location (see Figure 5-7)

Figure 5-7

(3)Choose your device and then press next button (see Figure 5-8)

(a) Device Family: VirtexE

(b) Device: xcv2000e

(c) Package: fg680

(d) Speed Grade: -6

Figure 5-8

(4)Press next button (see Figure 5-9)

Figure 5-9

(5) Project→add source File(s)

(\Codes\HW\Xilinx\GPIO\Verilog\*.v)

Figure 5-10

(6)Then you can see Figure 5-11

Figure 5-11

(7) Press the next button (you will see Figure 5-12)

Figure 5-12

(8)Press finish button (you will see Figure 5-13)

Figure 5-13

(9)Add AHBAHBTop.ucf file to this project associate with AHBAHBTop.

( choose Project --->Add sources ,see Figure 5-14 )

(\Codes\HW\Xilinx\GPIO\PnR)

Figure 5-14

(10)Generate the Binary Bitstreams

(a) Select Top module (AHBAHBTop)

(b) Double click the Generate Programming File (see Figure 5-15)

Figure 5-15

NOTE:

(1) To ensure that Xilinx generate a file that operates correctly with logic module, you use some setting (reference “Integrator/LM-XCV600E+ User Guide” “Integrator/LM-EP20K600E+ User Guide” CHAPTER 5 Configuring Xilinx Logic Modules at page 5-1), and then compile your design to generate .bit file.

(2) Be careful !! Before programming the FPGA, you must generate a *.ucf file and then compile your design. Then, Xilinx will generate .bit file.

3. Porting the Bit file (AHBAHBTop.bit) to the Logic Module

(1) Create a BRD file as below

[General]

Name = AHB XCV2000E -> flash (addr 0x0)

Priority = 1

[ScanChain]

TAPs = 2

TAP0 = XCV2000E

TAP1 = XC9572XL

[Program]

SequenceLength = 3

Step1Method = Virtex

Step1TAP = 0

Step1File = lmxcv600e_72c_xcv2000e_via_reva_build0.bit

Step2Method = IntelFlash

Step2TAP = 0

Step2File = ahbahbtop.bit

Step3Method = IntelFlashVerify

Step3TAP = 0

Step3File = ahbahbtop.bit

Save the file and rename it as GPIO.brd.

(2) Copy the file progcard.exe (in \Program Files\ARM\Logic\Modules\LM-XCV600E\configure\) to your working directory

(3) Make sure that the Integrator is power off.

(4) Adjust the logic module into Flash Program Mode as follows:

(i) Let the CONFIG LINK be shorted.

(ii) Close the switch S1[4] (the switch is pull down)..

(5) Connect the Multi-ICE unit to the Logic Module.

(6) Power on the Integrator.

(7) Run the ARM Multi-ICE Server (/Programs/ARM Multi-ICE v2.2/Multi-ICE Server) (Figure 5-16).

Figure 5-16. Multi-ICE Server

(8)Check if the three files lmxcv600e_72c_xcv2000e_via_reva_build0.bit , AHBAHBTop.bit , GPIO.brd, and progcard.exe exist in the working directory. Execute progcard.exe (Figure 5-17). This step will download the design into the flash of LM.

Figure 5-17. Execute the progcard.exe to download the design into the flash.

(9)Shutdown the Integrator.

(10)Adjust the logic module into the User Mode as follows:

(i) Adjust the CONFIG Link as open;

(ii) Adjust the S1[4] as open (pull up).

(11) Adjust the switch S1[1] as closed (down) and switch S1[3] as open (up) to select flash image 0.

4. Running the application program

An application example that employs the GPIO implemented in LM FPGA to control the LED is given in the directory Codes/SW/GPIO.

(1) Connect Row 2 and Row 3 of the prototyping grid to the LEDs in a breadboard (Figure 5-18).

Note: We should series the LEDs with protective resistances to limit the current.

Figure 5-18. Connect the prototype grids to the LEDs in a breadboard

(2) Connect Multi-ICE to the Core Module

(3) Start the Multi-ICE Server

(4) Start CodeWarrior. Create a new project, and add the files in the directory Codes/SW/GPIO to the project. Build this project.

(5) Run the AXD and you will see the LEDs connected on the breadboard are flashing.

5.4. 實驗要求

· Understand the Verilog codes of GPIO and the source codes of the application program, and try to modify the application program such that the LEDs flash in a different way.

5.5. 問題與討論

· Read the ARM PrimeCell General Purpose Input/Output (PL061) Technical Reference Manual and compare the differences between GPIO PL060 and GPIO PL061.

5.6. 參考文件

1. ARM PrimeCell General Purpose Input/Output (PL060) Technical Reference Manual (ARM DDI 0142B).

2. Zong-xin Lin, “Design of an ARM-based System-on-Chip for Real-time QRS Detection in Electrocardiogram,” master thesis, Department of Electrical Engineering, Chang Gung University, Taiwan, June 2003.

3. Xilinx Logic Module Schematics : lm_xcv600e_revc.pdf

5-18

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5-17

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