DAC_MCP4921

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2010 Microchip Technology Inc. DS22248A-page 1

MCP4901/4911/4921

Features

MCP4901: 8-Bit Voltage Output DAC MCP4911: 10-Bit Voltage Output DAC MCP4921: 12-Bit Voltage Output DAC Rail-to-Rail Output SPI Interface with 20 MHz Clock Support Simultaneous Latching of the DAC Output

with LDAC Pin Fast Settling Time of 4.5 s

Selectable Unity or 2x Gain Output External Voltage Reference Input External Multiplier Mode 2.7V to 5.5V Single-Supply Operation Extended Temperature Range: -40C to +125C

Applications

Set Point or Offset Trimming Precision Selectable Voltage Reference Motor Control Feedback Loop Digitally-Controlled Multiplier/Divider Calibration of Optical Communication Devices

Related Products

Description

The MCP4901/4911/4921 devices are single channel8-bit, 10-bit and 12-bit buffered voltage outputDigital-to-Analog Converters (DACs), respectively. Thedevices operate from a single 2.7V to 5.5V supply withan SPI compatible Serial Peripheral Interface. The user can configure the full-scale range of the device to beVREF or 2*V REF by setting the gain selection option bit(gain of 1 of 2).

The user can shut down the device by setting the Con-

figuration Register bit. In Shutdown mode, most of theinternal circuits are turned off for power savings, andthe output amplifier is configured to present a knownhigh resistance output load (500 k typical .

The devices include double-buffered registers,allowing synchronous updates of the DAC output usingthe LDAC pin. These devices also incorporate aPower-on Reset (POR) circuit to ensure reliable power-up.

The devices utilize a resistive string architecture, withits inherent advantages of low Differential Non-Linear-ity (DNL) error and fast settling time. These devices arespecified over the extended temperature range

(+125C).The devices provide high accuracy and low noiseperformance for consumer and industrial applicationswhere calibration or compensation of signals (such astemperature, pressure and humidity) are required.

The MCP4901/4911/4921 devices are available in thePDIP, SOIC, MSOP and DFN packages.

Package Types

P/NDAC

ResolutionNo. of

Channels

VoltageReference

(VREF )

MCP4801 8 1

Internal(2.048V)

MCP4811 10 1

MCP4821 12 1

MCP4802 8 2

MCP4812 10 2

MCP4822 12 2

MCP4901 8 1

ExternalMCP4911 10 1

MCP4921 12 1

MCP4902 8 2

MCP4912 10 2

MCP4922 12 2

Note: The products listed here have similar AC/DCperformances.

DFN-8 (2x3) *

1

2

3

4

8

7

6

5

CS

SCK

SDI

VDD

VSS

VOUT

LDAC

MCP4901 : 8-bit single DACMCP4911 : 10-bit single DACMCP4921 : 12-bit single DAC

M C P 4 9 x 1

8-Pin PDIP, SOIC, MSOP

1

2

3

4

8

7

6

5

CS

SCK

SDI

VDD

VSS

VOUT

LDAC

VREF VREF

EP9

* Includes Exposed Thermal Pad (EP); see Table 3-1 .

8/10/12-Bit Voltage Output Digital-to-Analog Converter

with SPI Interface

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DS22248A-page 2 2010 Microchip Technology Inc.

Block Diagram

Op Amp

VDD

VSS

CS SDI SCK

Interface Logic

Input Register

DAC Register

StringDAC

Power-on Reset

VOUT

LDAC

Output GainLogic

OutputLogic

VREF

Buffer

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MCP4901/4911/4921

1.0 ELECTRICALCHARACTERISTICS

Absolute Maximum Ratings

VDD ............................................................................................................. 6.5V

All inputs and outputs w.r.t ............... .V SS 0.3V to V DD+0.3VCurrent at Input Pins ....................................................2 mA

Current at Supply Pins ...............................................50 mA

Current at Output Pins ...............................................25 mA

Storage temperature .............. ............... ........ -65C to +150C

Ambient temp. with power applied .............. ..-55C to +125C

ESD protection on all pins 4 kV (HBM), 400V (MM)

Maximum Junction Temperature (T J ) . .........................+150C

Notice: Stresses above those listed under MaximumRatings may cause permanent damage to the device. This isa stress rating only and functional operation of the device atthose or any other conditions above those indicated in theoperational listings of this specification is not implied.Exposure to maximum rating conditions for extended periodsmay affect device reliability.

ELECTRICAL CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, V DD = 5V, V SS = 0V, V REF = 2.048V, Output Buffer Gain(G) = 2x, R

L= 5 k to GND, C

L= 100 pF T

A= -40 to +85C. Typical values are at +25C.

Parameters Sym Min Typ Max Units Conditions

Power Requirements

Operating Voltage V DD 2.7 5.5

Supply Current I DD 175 350 A V DD = 5VVDD = 3VVREF input is unbuffered, all digitalinputs are grounded, all analogoutputs (V OUT ) are unloaded.Code = 0x000h

125 250 A

Software Shutdown Current I SHDN_SW 3.3 6 A Power-on Reset circuit remains on

Power-On-Reset Threshold V POR 2.0 V

DC AccuracyMCP4901

Resolution n 8 Bits

INL Error INL -1 0.125 1 LSb

DNL DNL -0.5 0.1 +0.5 LSb Note 1

MCP4911

Resolution n 10 Bits

INL Error INL -3.5 0.5 3.5 LSb

DNL DNL -0.5 0.1 +0.5 LSb Note 1

MCP4921


INL Error INL -12 2 12 LSbDNL DNL -0.75 0.2 +0.75 LSb Note 1

Note 1: Guaranteed monotonic by design over all codes.2: This parameter is ensured by design, and not 100% tested.

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Offset Error V OS 0.02 1 % ofFSR

Code = 0x000h

Offset Error TemperatureCoefficient

VOS /C 0.16 ppm/C -45C to 25C

-0.44 ppm/C +25C to 85C

Gain Error g E -0.10 1 % ofFSR

Code = 0xFFFh, not includingoffset error

Gain Error TemperatureCoefficient

G/C -3 ppm/C

Input Amplifier (V REF Input)

Input Range BufferedMode

VREF 0.040 V DD 0.040

V Note 2Code = 2048VREF = 0.2 Vp-p, f = 100 Hz and1 kHz

Input Range UnbufferedMode

VREF 0 V DD V

Input Impedance R VREF 165 k Unbuffered ModeInput Capacitance Unbuffered Mode

CVREF 7 pF

Multiplier Mode-3 dB Bandwidth

f VREF 450 kHz V REF = 2.5V 0.2Vp-p,Unbuffered, G = 1

f VREF 400 kHz V REF = 2.5V 0.2 Vp-p,Unbuffered, G = 2

Multiplier Mode Total Harmonic Distortion

THD VREF -73 dB V REF = 2.5V 0.2Vp-p,Frequency = 1 kHz

Output Amplifier

Output Swing V OUT 0.01 toVDD 0.04

V Accuracy is better than 1 LSb forVOUT = 10 mV to (V DD 40 mV)

Phase Margin m 66 DegreesSlew Rate SR 0.55 V/s

Short Circuit Current I SC 15 24 mA

Settling Time t settling 4.5 s Within 1/2 LSB of final value from1/4 to 3/4 full-scale range

Dynamic Performance ( Note 2 )

DAC-to-DAC Crosstalk 10 nV-s

Major Code TransitionGlitch

45 nV-s 1 LSB change around major carry(0111 ... 1111 to 1000 ... 0000 )

Digital Feedthrough 10 nV-s

Analog Crosstalk 10 nV-s

ELECTRICAL CHARACTERISTICS (CONTINUED)Electrical Specifications: Unless otherwise indicated, V DD = 5V, V SS = 0V, V REF = 2.048V, Output Buffer Gain(G) = 2x, R L = 5 k to GND, C L = 100 pF T A = -40 to +85C. Typical values are at +25C.



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ELECTRICAL CHARACTERISTIC WITH EXTENDED TEMPERATUREElectrical Specifications: Unless otherwise indicated, V DD = 5V, V SS = 0V, V REF = 2.048V, Output Buffer Gain(G) = 2x, R L = 5 k to GND, C L = 100 pF. Typical values are at +125C by characterization or simulation.


Power Requirements

Input Voltage V DD 2.7 5.5

Input Current I DD 200 A V REF input is unbuffered, all digi-tal inputs are grounded, all analogoutputs (VOUT) are unloaded.Code = 0x000h

Software Shutdown Current I SHDN_SW 5 A

Power-on Reset Threshold V POR 1.85 V

DC Accuracy

MCP4901

Resolution n 8 Bits

INL Error INL 0.25 LSb

DNL

DNL 0.2 LSb Note 1MCP4911


INL Error INL 1 LSb

DNL DNL 0.2 LSb Note 1

MCP4921


INL Error INL 4 LSb

DNL DNL 0.25 LSb Note 1Offset Error VOS 0.02 % of FSR Code = 0x000h

Offset Error Temperature

Coefficient

VOS /C -5 ppm/C +25C to +125C

Gain Error g E -0.10 % of FSR Code = 0xFFFh, not includingoffset error

Gain Error TemperatureCoefficient

G/C -3 ppm/C

Input Amplifier (V REF Input)

Input Range BufferedMode

VREF 0.040 toVDD-0.040

V Note 1Code = 2048,VREF = 0.2 Vp-p, f = 100 Hz and1 kHz

Input Range UnbufferedMode

VREF 0 VDD V

Input Impedance RVREF

174 k Unbuffered Mode

Input Capacitance Unbuffered Mode

CVREF 7 pF

Multiplying Mode-3 dB Bandwidth

f VREF 450 kHz V REF = 2.5V 0.1 Vp-p,Unbuffered, G = 1x

f VREF 400 kHz V REF = 2.5V 0.1 Vp-p,Unbuffered, G = 2x


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AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)

FIGURE 1-1: SPI Input Timing Data.

Electrical Specifications: Unless otherwise indicated, V DD= 2.7V 5.5V, T A= -40 to +125C.Typical values are at +25C.


Schmitt Trigger High LevelInput Voltage (All digital inputpins)

VIH 0.7 V DD V

Schmitt Trigger Low Level InputVoltage (All digital input pins)

VIL 0.2 V DD V

Hysteresis of Schmitt TriggerInputs

VHYS 0.05 V DD

Input Leakage Current I LEAKAGE -1 1 A LDAC = CS = SDI =SCK = V REF = VDD or V SS

Digital Pin Capacitance(All inputs/outputs)

C IN,COUT

10 pF V DD = 5.0V, T A = +25C,f CLK = 1 MHz (Note 1 )

Clock Frequency F CLK 20 MHz T A = +25C (Note 1 )

Clock High Time tHI

15 ns Note 1

Clock Low Time t LO 15 ns Note 1

CS Fall to First Rising CLKEdge

tCSSR 40 ns Applies only when CS falls withCLK high (Note 1 )

Data Input Setup Time t SU 15 ns Note 1

Data Input Hold Time t HD 10 ns Note 1

SCK Rise to CS Rise HoldTime

tCHS 15 ns Note 1

CS High Time t CSH 15 ns Note 1

LDAC Pulse Width t LD 100 ns Note 1

LDAC Setup Time t LS 40 ns Note 1

SCK Idle Time before CS Fall t IDLE 40 ns Note 1Note 1: This parameter is ensured by design and not 100% tested.

CS

SCK

SI

LDAC

tCSSR

tHDtSU

tLO

tCSH

tCHS

LSB inMSB in

tIDLE

Mode 1,1

Mode 0,0

tHI

tLDtLS

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TEMPERATURE CHARACTERISTICSElectrical Specifications: Unless otherwise indicated, V DD = +2.7V to +5.5V, V SS = GND.


Temperature Ranges

Specified Temperature Range T A -40 +125 C

Operating Temperature Range T A -40 +125 C Note 1Storage Temperature Range T A -65 +150 C

Thermal Package Resistances

Thermal Resistance, 8L-DFN (2 x 3) JA 68 C/WThermal Resistance, 8L-PDIP JA 90 C/WThermal Resistance, 8L-SOIC JA 150 C/WThermal Resistance, 8L-MSOP JA 211 C/WNote 1: The MCP4901/4911/4921 devices operate over this extended temperature range, but with reduced

performance. Operation in this range must not cause T J to exceed the maximum junction temperature of150C.

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MCP4901/4911/4921

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, T A = +25C, V DD = 5V, V SS = 0V, V REF = 2.048V, Gain = 2x, R L = 5 k , C L = 100 pF.

FIGURE 2-1: DNL vs. Code (MCP4921).

FIGURE 2-2: DNL vs. Code andTemperature (MCP4921).

FIGURE 2-3: DNL vs. Code and V REF ,Gain=1 (MCP4921).

FIGURE 2-4: Absolute DNL vs.Temperature (MCP4921).

FIGURE 2-5: Absolute DNL vs. VoltageReference (MCP4921).

FIGURE 2-6: INL vs. Code andTemperature (MCP4921).

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0 1024 2048 3072 4096

Code (Decimal)

D N L ( L S B )

-0.2

-0.1

0

0.1

0.2

0 1024 2048 3072 4096

Code (Decimal)

D N L ( L S B )

125C 85C 25C

-0.4

-0.3-0.2

-0.1

0

0.1

0.2

0.3

0.4

0 1024 2048 3072 4096

Code (Decimal)

D N L ( L S B )

1 2 3 4 5.5

0.075

0.0752

0.0754

0.0756

0.0758

0.076

0.0762

0.0764

0.0766

-40 -20 0 20 40 60 80 100 120

Ambient Temperature (C)

A b s o

l u t e D N L ( L S B )

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

1 2 3 4 5

Voltage Reference (V)

A b s o l u

t e D N L ( L S B )

-5-4-3-2

-1012345

0 1024 2048 3072 4096Code (Decimal)

I N L ( L S B )

125C 85 25

Ambient Temperature

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Note: Unless otherwise indicated, T A = +25C, V DD = 5V, V SS = 0V, V REF = 2.048V, Gain = 2, R L = 5 k , C L = 100 pF.

FIGURE 2-7: Absolute INL vs.Temperature (MCP4921).

FIGURE 2-8: Absolute INL vs. V REF(MCP4921).

FIGURE 2-9: INL vs. Code and V REF(MCP4921).

FIGURE 2-10: INL vs. Code (MCP4921).



0

0.5

1

1.5

2

2.5

-40 -20 0 20 40 60 80 100 120


A b s o l u

t e I N L ( L S B )

0

0.5

1

1.5

2

2.5

3

1 2 3 4 5

Voltage Reference (V)

A b s o l u

t e I N L ( L S B )

-4

-3

-2

-1

0

1

2

3

0 1024 2048 3072 4096Code (Decimal)

I N L ( L S B )

1 2 3 4 5.5

VREF

Note: Single device graph ( Figure 2-10 ) for illustration of 64 code effect.

-6

-4

-2

0

2

0 1024 2048 3072 4096

Code (Decimal)

I N L ( L S B )

-0.2

-0.1

0

0.1

0.2

0 128 256 384 512 640 768 896 1024Code

D N L ( L S B )

Temp = - 40 oC to +125 oC

-3.5

-2.5

-1.5

-0.5

0.5

1.5

0 128 256 384 512 640 768 896 1024Code

I N L ( L S B )

125 o C

85 o C

25 oC- 40 oC

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FIGURE 2-15: I DD vs. Temperature andV DD .

FIGURE 2-16: I DD Histogram (V DD =2.7V).

FIGURE 2-17: I DD Histogram (V DD =5.0V).

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0 32 64 96 128 160 192 224 256Code

D N L ( L S B )

Temp = -40 oC to +125 o C

-0.5

-0.25

0

0.25

0.5

0 32 64 96 128 160 192 224 256Code

I N L ( L S B )

125 oC

-40 oC to +85 o C

110

130

150

170

190

210

-40 -20 0 20 40 60 80 100 120Ambient Temperature (C)

I D D

( A )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

02468

1012141618

1 4 3

1 4 5

1 4 7

1 4 9

1 5 1

1 5 3

1 5 5

1 5 7

1 5 9

1 6 1

1 6 3

1 6 5

1 6 7

IDD (A)

O c c u r r e n c e

0

1

2

3

4

5

67

8

9

151 156 161 166 171 176 181 186 191 196 201

IDD (A)

O c c u r r e n c e

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FIGURE 2-18: Shutdown Current vs.Temperature and V DD .

FIGURE 2-19: Offset Error vs.Temperatureand V DD.

FIGURE 2-20: Gain Error vs. Temperatureand V DD.

FIGURE 2-21: V IN High Threshold vs.Temperature and V DD .

FIGURE 2-22: V IN Low Threshold vs.Temperature and V DD .

0

1

2

3

4

5

6


I S H D N

_ S W (

A )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

-0.02

0

0.02

0.04

0.06

0.08

0.1

0.12

-40 -20 0 20 40 60 80 100 120


O f f s e

t E r r o r

( % )

VDD

5.5V

4.0V5.0V

3.0V2.7V

-0.16

-0.14

-0.12

-0.1

-0.08


G a i n

E r r o r

( % )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

1

1.5

2

2.5

3

3.5

4


V I N

H i T h r e s

h o l d ( V )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

-40 - 20 0 20 40 60 80 100 120Ambient Temperature (C)

V I N

L o w

T h r e s h o l d

( V ) VDD

5.5V

4.0V

5.0V

3.0V2.7V

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FIGURE 2-23: Input Hysteresis vs.Temperature and V DD .

FIGURE 2-24: V REF Input Impedance vs.Temperature and V DD .

FIGURE 2-25: V OUT High Limit vs.Temperature and V DD .

FIGURE 2-26: V OUT Low Limit vs.Temperature and V DD .

FIGURE 2-27: I OUT High Short vs.Temperature and V DD .

FIGURE 2-28: I OUT vs. V OUT . Gain = 1.

00.25

0.50.75

11.25

1.51.75

22.25

2.5


V I N_ S

P I

H y s

t e r e s i s

( V )

VDD5.5V

4.0V

5.0V

3.0V2.7V

155

160

165

170

175

-40 -20 0 20 40 60 80 1 00 120Ambient Temperature (C)

V R E F_ U N B U F F E R E D

I m p e d a n c e

( k O h m

)

VDD

5.5V -2.7V

0

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

-40 -20 0 20 40 60 80 1 00 120Ambient Temperature (C)

V O U T_ H I

L i m i t ( V

D D - Y

) ( V )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

0.0015

0.002

0.0025

0.003

0.0035

0.004

0.0045

-40 -20 0 20 40 60 80 100 120


V O U T_ L O W L

i m i t ( Y - A

V S S

) ( V )

VDD

5.5V

4.0V

5.0V

3.0V2.7V

10

11

12

13

14

15

16

17

18


I O U T_ H I_ S H O R T E D

( m A )

VDD

5.5V

4.0V5.0V

3.0V2.7V

0.0

1.0

2.0

3.0

4.0

5.0

6.0

0 2 4 6 8 10 12 14 16IOUT (mA)

V O U T

( V )

VREF =4.0

Output Shorted to V SS

Output Shorted to V DD

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FIGURE 2-29: V OUT Rise Time

FIGURE 2-30: V OUT Fall Time.



FIGURE 2-33: V OUT Rise Time ExitShutdown.

FIGURE 2-34: PSRR vs. Frequency.

VOUT

SCK

LDAC

Time (1 s/div)

VOUT

SCK

LDAC

Time (1 s/div)

VOUT

SCK

LDAC

Time (1 s/div)

Time (1 s/div)

VOUT

LDAC

Time (1 s/div)

VOUT

SCK

LDAC

R i p p

l e R e

j e c

t i o n

( d B )

Frequency (Hz)

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FIGURE 2-35: Multiplier Mode Bandwidth.

FIGURE 2-36: -3 db Bandwidth vs. WorstCodes.

FIGURE 2-37: Phase Shift.

-12

-10

-8

-6

-4

-2

0

100 1,000Frequency (kHz)

A t t e n u a t

i o n

( d B )

D = 160D = 416D = 672D = 928D = 1184D = 1440D = 1696D = 1952D = 2208D = 2464D = 2720D = 2976D = 3232D = 3488D = 3744

Figure 2-35 calculation: Attenuation (dB) = 20 log (V OUT /VREF ) 20 log (G(D/4096))

400420440460480500520540560580600

1 6 0 4 1 6

6 7 2 9 2 8

1 1 8 4 1 4 4 0

1 6 9 6 1 9 5 2

2 2 0 8 2 4 6 4

2 7 2 0 2 9 7 6

3 2 3 2 3 4 8 8

3 7 4 4

Worst Case Codes (decimal)

B a n

d w

i d t h ( k H z )

G = 1

G = 2

-180

-135

-90

-45

0

100 1,000Frequency (kHz)

q V R E F q V O U T

D = 160D = 416D = 672D = 928D = 1 184D = 1 440D = 1 696

D = 1 952D = 2 208D = 2 464D = 2 720D = 2 976D = 3 232D = 3 488D = 3 744

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NOTES:

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3.0 PIN DESCRIPTIONSThe descriptions of the pins are listed in Table 3-1 .

3.1 Supply Voltage Pins (V DD, VSS )VDD is the positive supply voltage input pin. The inputsupply voltage is relative to V SS and can range from2.7V to 5.5V. The power supply at the V DD pin shouldbe as clean as possible for good DAC performance. Itis recommended to use an appropriate bypass capaci-tor of about 0.1 F (ceramic) to ground. An additional10 F capacitor (tantalum) in parallel is also recom-mended to further attenuate high-frequency noisepresent in application boards.

VSS is the analog ground pin and the current return pathof the device. The user must connect the V SS pin to aground plane through a low-impedance connection. If an analog ground path is available in the applicationPrinted Circuit Board (PCB), it is highly recommendedthat the V SS pin be tied to the analog ground path or isolated within an analog ground plane of the circuitboard.

3.2 Chip Select (CS)

CS is the chip select input, which requires an active-lowsignal to enable serial clock and data functions.

3.3 Serial Clock Input (SCK)

SCK is the SPI compatible serial clock input.

3.4 Serial Data Input (SDI)

SDI is the SPI compatible serial data input.

3.5 Latch DAC Input (LDAC)The LDAC (latch DAC synchronization input) pin isused to transfer the input latch register to the DAC reg-ister (output latches, V OUT ). When this pin is low, V OUTis updated with input register content. This pin can betied to low (V SS ) if the V OUT update is desired at therising edge of the CS pin. This pin can be driven by anexternal control device such as an MCU I/O pin.

3.6 Analog Output (V OUT )

VOUT is the DAC analog output pin. The DAC outputhas an output amplifier. The full-scale range of the DAC

output is from V SS to G*V REF , where G is the gainselection option (1x or 2x). The DAC analog outputcannot go higher than the supply voltage (V DD).

3.7 Voltage Reference Input (V REF )

VREF is the voltage reference input for the device. Thereference on this pin is utilized to set the referencevoltage on the string DAC. The input voltage can rangefrom V SS to V DD. This pin can be tied to V DD .

3.8 Exposed Thermal Pad (EP)

There is an internal electrical connection between theExposed Thermal Pad (EP) and the V SS pin. They mustbe connected to the same potential on the PCB.

TABLE 3-1: PIN FUNCTION TABLE

PDIP, MSOP, SOIC DFN Symbol Description

1 1 VDD

Supply Voltage Input (2.7V to 5.5V)

2 2 CS Chip Select Input

3 3 SCK Serial Clock Input

4 4 SDI Serial Data Input

5 5 LDAC DAC Output Synchronization Input. This pin is used to transferthe input register (DAC settings) to the output register (V OUT )

6 6 V REF Voltage Reference Input

7 7 V SS Ground reference point for all circuitry on the device

8 8 V OUT DAC Analog Output 9 EP Exposed Thermal Pad. This pad must be connected to V SS in

application

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4.0 GENERAL OVERVIEWThe MCP4901, MCP4911 and MCP4921 are singlechannel voltage output 8-bit, 10-bit and 12-bit DACdevices, respectively. These devices include a V REFinput buffer, a rail-to-rail output amplifier, shutdown andreset management circuitry. The devices use an SPI

serial communication interface and operate with asingle-supply voltage from 2.7V to 5.5V.

The DAC input coding of these devices is straightbinary. Equation 4-1 shows the DAC analog outputvoltage calculation.

EQUATION 4-1: ANALOG OUTPUTVOLTAGE (V OUT )

The ideal output range of each device is:

MCP4901 (n = 8)

(a) 0V to 255/256*V REF when gain setting = 1x.

(b) 0V to 255/256*2*V REF when gain setting = 2x.

MCP4911 (n = 10)



MCP4921 (n = 12)



1 LSb is the ideal voltage difference between twosuccessive codes. Table 4-1 illustrates the LSbcalculation of each device.

4.1 DC Accuracy

4.1.1 INL ACCURACY

Integral Non-Linearity (INL) error is the maximumdeviation between an actual code transition point andits corresponding ideal transition point, after offset andgain errors have been removed. The two endpoints

(from 0x000 and 0xFFF) method is used for the calcu-lation. Figure 4-1 shows the details.

A positive INL error represents transition(s) later thanideal. A negative INL error represents transition(s) ear-lier than ideal.

FIGURE 4-1: Example for INL Error.

4.1.2 DNL ACCURACY

A Differential Non-Linearity (DNL) error is the measureof variations in code widths from the ideal code width.

A DNL error of zero indicates that every code is exactly1 LSB wide.

Note: See the output swing voltage specificationin Section 1.0 Electrical Characteris-tics .

V OU T V RE F Dn

2 n------------------------------- G=

Where:

VREF = E Xternal voltage reference

Dn = DAC input codeG ===

Gain Selection2 for bit = 01 for bit = 1

n ====

DAC Resolution8 for MCP490110 for MCP491112 for MCP4912

TABLE 4-1: LSb OF EACH DEVICE

DeviceGain

Selection LSb Size

MCP4901(n = 8)

1x VREF /2562x (2*V REF )/256

MCP4911(n = 10)

1x VREF

/1024 2x (2*V REF )/1024

MCP4921(n = 12)

1x V REF /40962x (2*V REF )/4096

where V REF is the external voltage reference.

111

110

101

100

011

010

001

000

DigitalInputCode

ActualTransfer Function

INL < 0

Ideal Transfer Function

INL < 0

DAC Output

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FIGURE 4-2: Example for DNL Accuracy.

4.1.3 OFFSET ERROR

An offset error is the deviation from zero voltage outputwhen the digital input code is zero.

4.1.4 GAIN ERROR

A gain error is the deviation from the ideal output,VREF 1 LSB, excluding the effects of offset error.

4.2 Circuit Descriptions

4.2.1 OUTPUT AMPLIFIER

The DACs output is buffered with a low-power,precision CMOS amplifier. This amplifier provides lowoffset voltage and low noise. The output stage enablesthe device to operate with output voltages close to thepower supply rails. Refer to Section 1.0 ElectricalCharacteristics for the analog output voltage rangeand load conditions.

In addition to resistive load driving capability, theamplifier will also drive high capacitive loads withoutoscillation. The amplifiers strong output allows V OUT tobe used as a programmable voltage reference in asystem.

Selecting a gain of 2 reduces the bandwidth of theamplifier in Multiplying mode. Refer to Section 1.0

Electrical Characteristics for the Multiplying modebandwidth for given load conditions.

4.2.1.1 Programmable Gain Block

The rail-to-rail output amplifier has two configurablegain options: a gain of 1x ( = 1 ) or a gain of 2x( = 0 ). The default value is a gain of 2x( = 0 ).

4.2.2 VOLTAGE REFERENCE AMPLIFIER

The input buffer amplifier for the MCP4901/4911/4921devices provides low offset voltage and low noise. AConfiguration bit for each DAC allows the V REF input tobypass the V REF input buffer amplifier, achievingBuffered or Unbuffered mode. Buffered mode providesa very high input impedance, with only minor limitationson the input range and frequency response. Unbuf-fered mode provides a wide input range (0V to V DD),with a typical input impedance of 165 k with 7 pF.Unbuffered mode ( = 0 ) is the defaultconfiguration.

4.2.3 POWER-ON RESET CIRCUIT

The internal Power-on Reset (POR) circuit monitors thepower supply voltage (V DD) during device operation.The circuit also ensures that the device powers up withhigh output impedance ( = 0 , typically500 k . The devices will continue to have a high-impedance output until a valid write command is

received, and the LDAC pin meets the input low thresh-old.

If the power supply voltage is less than the PORthreshold (V POR = 2.0V, typical), the device will be heldin its Reset state. It will remain in that state untilVDD > VPOR and a subsequent write command isreceived.

Figure 4-3 shows a typical power supply transientpulse and the duration required to cause a reset tooccur, as well as the relationship between the durationand trip voltage. A 0.1 F decoupling capacitor,mounted as close as possible to the V DD pin, canprovide additional transient immunity.

FIGURE 4-3: Typical Transient Response.

111

110

101

100

011

010

001

000

DigitalInputCode

ActualTransfer

FunctionIdeal Transfer Function

Narrow Code, < 1 LSb

DAC Output

Wide Code, > 1 LSb

Transients above the

Transients below the

5V

Time

S u p p l y V o l t a g e s

Transient Duration

V POR

V DD - V POR

T A =

T r a n s i e n t D u r a t i o n ( s )

10

8

6

4

2

01 2 3 4 5

V DD V POR (V)

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4.2.4 SHUTDOWN MODE

The user can shut down the device by using a softwarecommand. During Shutdown mode, most of the internalcircuits, including the output amplifier, are turned off for power savings. The serial interface remains active,thus allowing a write command to bring the device outof Shutdown mode. There will be no analog output atthe V OUT pin, and the V OUT pin is internally switched toa known resistive load (500 k typical . Figure 4-4shows the analog output stage during Shutdown mode.

The device will remain in Shutdown mode until itreceives a write command with bit = 1 and thebit is latched into the device. When the device ischanged from Shutdown to Active mode, the outputsettling time takes less than 10 s, but more than thestandard active mode settling time (4.5 s).

FIGURE 4-4: Output Stage for ShutdownMode.

500 k

Power-DownControl Circuit

ResistiveLoad

VOUTOP

Amp

Resistive String DAC

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5.0 SERIAL INTERFACE

5.1 Overview

The MCP4901/4911/4921 devices are designed tointerface directly with the Serial Peripheral Interface(SPI) port, which is available on many microcontrollers

and supports Mode 0,0 and Mode 1,1. Commands anddata are sent to the device via the SDI pin, with databeing clocked-in on the rising edge of SCK. Thecommunications are unidirectional, thus the datacannot be read out of the MCP4901/4911/4921. TheCS pin must be held low for the duration of a writecommand. The write command consists of 16 bits andis used to configure the DACs control and data latches.Register 5-1 through Register 5-3 detail the input regis-ter that is used to configure and load the DAC register for each device. Figure 5-1 through Figure 5-3 showthe write command for each device.

Refer to Figure 1-1 and the SPI Timing SpecificationsTable for detailed input and output timing specificationsfor both Mode 0,0 and Mode 1,1 operation.

5.2 Write Command

The write command is initiated by driving the CS pinlow, followed by clocking the four Configuration bits andthe 12 data bits into the SDI pin on the rising edge of SCK. The CS pin is then raised, causing the data to belatched into the DACs input register.

The MCP4901/4911/4921 utilizes a double-bufferedlatch structure to allow the analog output to besynchronized with the LDAC pin, if desired.

By bringing the LDAC pin down to a low state, the con-tent stored in the DACs input register is transferred intothe DACs output register (V OUT ), and V OUT is updated.

All writes to the MCP4901/4911/4921 devices are16-bit words. Any clocks past the 16th clock will beignored. The Most Significant 4 bits are Configurationbits. The remaining 12 bits are data bits. No data canbe transferred into the device with CS high. Thistransfer will only occur if 16 clocks have beentransferred into the device. If the rising edge of CS

occurs prior to that, shifting of data into the inputregister will be aborted.

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REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4921 (12-BIT DAC)



Where:

W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x

0 BUF GA SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

bit 15 bit 0


0 BUF GA SHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x

bit 15 bit 0


0 BUF GA SHDN D7 D6 D5 D4 D3 D2 D1 D0 x x x x

bit 15 bit 0

bit 15 0 = Write to DAC register 1 = Ignore this command

bit 14 BUF: VREF Input Buffer Control bit1 = Buffered0 = Unbuffered

bit 13 GA: Output Gain Selection bit1 = 1x (V OUT = VREF * D/4096)0 = 2x (V OUT = 2 * V REF * D/4096)

bit 12 SHDN: Output Shutdown Control bit1 = Active mode operation. V OUT is available.0 = Shutdown the device. Analog output is not available. V OUT pin is connected to 500 k typical)

bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.

Legend

R = Readable bit W = Writable bit U = Unimplemented bit, read as 0

-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

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6.0 TYPICAL APPLICATIONSThe MCP4901/4911/4921 family devices are generalpurpose DACs intended to be used in applicationswhere precision with low-power and moderatebandwidth is required.

Applications generally suited for the devices are:

Set Point or Offset Trimming Sensor Calibration Digitally-Controlled Multiplier/Divider Portable Instrumentation (Battery Powered) Motor Control Feedback Loop

6.1 Digital Interface

The MCP4901/4911/4921 devices utilize a 3-wiresynchronous serial protocol to transfer the DACs setupand output values from the digital source. The serialprotocol can be interfaced to SPI or Microwire periph-erals that are common on many microcontrollers,including Microchips PIC MCUs and dsPIC DSCs.In addition to the three serial connections (CS, SCKand SDI), the LDAC pin synchronizes the analog output(VOUT ) with the pin event. By bringing the LDAC pindown low, the DAC input code and settings in theinput register are latched into the output register, andthe analog output is updated. Figure 6-1 shows anexample of the pin connections. Note that the LDAC pincan be tied low (V SS ) to reduce the requiredconnections from 4 to 3 I/O pins. In this case, the DACoutput can be immediately updated when a valid16-clock transmission has been received and CS pinhas been raised.

6.2 Power Supply Considerations

The typical application will require a bypass capacitor in order to filter high-frequency noise. The noise can beinduced onto the power supply's traces from variousevents such as digital switching or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources.Figure 6-1 illustrates an appropriate bypass strategy. Inthis example, two bypass capacitors are used inparallel: (a) 0.1 F (ceramic) and (b) 10 F (tantalum).These capacitors should be placed as close to thedevice power pin (V DD) as possible (within 4 mm).

The power source supplying these devices should beas clean as possible. If the application circuit hasseparate digital and analog power supplies, V DD andVSS should reside on the analog plane.

FIGURE 6-1: Typical ConnectionDiagram.

6.3 Layout Considerations

Inductively-coupled AC transients and digital switchingnoises can degrade the input and output signalintegrity, potentially reducing the devices performance.Careful board layout will minimize these effects and

increase the Signal-to-Noise Ratio (SNR). Bench test-ing has shown that a multi-layer board utilizing alow-inductance ground plane, isolated inputs, andisolated outputs with proper decoupling, is critical for best performance. Particularly harsh environmentsmay require shielding of critical signals.

Breadboards and wire-wrapped boards are notrecommended if low noise is desired.

VDD

VDD VDD

AVSS

AVSS VSS

VREF

VOUT P I C

M i c r o c o n

t r o

l l e r

VREF

VOUT

SDI

SDI

CS 1

SDO

SCK

LDAC

CS 0

C1 C1 C2C2

M C P 4 9 X 1

M C P 4 9 X 1

C1

C1 = 10 FC2 = 0.1 F

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6.4 Single-Supply Operation

The MCP4901/4911/4921 devices are rail-to-rail volt-age output DAC devices designed to operate with aVDD range of 2.7V to 5.5V. Its output amplifier is robustenough to drive small signal loads directly. Therefore, itdoes not require an external output buffer for most

applications.6.4.1 DC SET POINT OR CALIBRATION

A common application for DAC devices isdigitally-controlled set points and/or calibration of variable parameters, such as sensor offset or slope.For example, the MCP4921 and MCP4922 provide4096 output steps. If the external voltage reference(VREF ) is 4.096V, the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltagereference is needed.

6.4.1.1 Decreasing Output Step Size

If the application is calibrating the bias voltage of adiode or transistor, a bias voltage range of 0.8V may bedesired with about 200 V resolution per step. Twocommon methods to achieve a 0.8V range is to either reduce V REF to 0.82V or use a voltage divider on theDACs output.

Using a V REF is an option if the V REF is available withthe desired output voltage range. However,occasionally, when using a low-voltage V REF , the noisefloor causes an SNR error that is intolerable. Using avoltage divider method is another option and providessome advantages when V REF needs to be very low or when the desired output voltage is not available. In thiscase, a larger value V REF is used while two resistorsscale the output range down to the precise desiredlevel.

Example 6-1 illustrates this concept. Note that thebypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noiseof the DAC and the induced noise from theenvironment.

EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION.

VDD

SPI3-wire

VTRIPR1

R2 0.1 uF

Comparator

G = Gain selection (1x or 2x)Dn = Digital value of DAC (0-255) for MCP4901/MCP4902

V OU T V RE F G Dn

2 N ------ =

VCC +

VCC

VOUT

V trip V OU T

R2 R1 R2+--------------------

=

VDD

RSENSE

DAC

= Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4921/MCP4922

N = DAC Bit Resolution

VREF VO

MCP4901MCP4911MCP4921

(a) Single Output DAC:

(b) Dual Output DAC:MCP4902MCP4912MCP4922

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6.4.1.2 Building a Window DAC

When calibrating a set point or threshold of a sensor,typically only a small portion of the DAC output range isutilized. If the LSb size is adequate enough to meet theapplications accuracy needs, the unused range issacrificed without consequences. If greater accuracy isneeded, then the output range will need to be reducedto increase the resolution around the desired threshold.

If the threshold is not near V REF or V SS , then creatinga window around the threshold has severaladvantages. One simple method to create thiswindow is to use a voltage divider network with apull-up and pull-down resistor. Example 6-2 andExample 6-4 illustrate this concept.

EXAMPLE 6-2: SINGLE-SUPPLY WINDOW DAC.

VREF VDD

SPI3

VtripR1

R2 0.1 F

Comparator R

3

VCC-

VCC+ VCC+

VCC-

VOUT

R23 R2 R3

R2 R3+------------------=

V 23V CC+ R2 V CC- R3 +

R2 R3+-----------------------------------------------------=

V tr ipV OU T R23 V 23 R1+

R2 R23+--------------------------------------------=

R1

R23

V23

VOUT VOTheveninEquivalent

Rsense

G = Gain selection (1x or 2x)

Dn = Digital value of DAC (0-255) for MCP4901/MCP4902

V OU T V RE F G Dn

2 N ------

=



DAC




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6.5 Bipolar Operation

Bipolar operation is achievable using the MCP4901/4911/4921 family devices by using an externaloperational amplifier (op amp). This configuration isdesirable due to the wide variety and availability of opamps. This allows a general purpose DAC, with its cost

and availability advantages, to meet almost anydesired output voltage range, power and noiseperformance.

Example 6-3 illustrates a simple bipolar voltage sourceconfiguration. R 1 and R 2 allow the gain to be selected,while R 3 and R 4 shift the DAC's output to a selectedoffset. Note that R4 can be tied to V REF instead of V SSif a higher offset is desired. Note that a pull-up to V REFcould be used, instead of R 4, if a higher offset isdesired.

EXAMPLE 6-3: DIGITALLY-CONTROLLED BIPOLAR VOLTAGE SOURCE.

6.5.1 DESIGN EXAMPLE: DESIGN A BIPOLARDAC USING EXAMPLE 6-3 WITH 12-BITMCP4912 OR MCP4922

An output step magnitude of 1 mV with an output rangeof 2.05V is desired for a particular application.The following steps show the details:1. Calculate the range: +2.05V (-2.05V) = 4.1V.2. Calculate the resolution needed:

4.1V/1 mV = 4100Since 2 12 = 4096, 12-bit resolution is desired.

3. The amplifier gain (R 2/R1), multiplied by V REF ,must be equal to the desired minimum output toachieve bipolar operation. Since any gain can

be realized by choosing resistor values(R1 + R 2), the V REF source needs to be deter-mined first. If a V REF of 4.1V is used, solve for the gain by setting the DAC to 0, knowing thatthe output needs to be -2.05V. The equation canbe simplified to:

4. Next, solve for R 3 and R 4 by setting the DAC to4096, knowing that the output needs to be+2.05V.

VREF

VREFVDD

SPI3

VOUT R3

R4

R1

VIN+

0.1 F

VCC +

VCC

VO

V IN+V OU T R4 R3 R4+--------------------=

V O V IN+ 1 R2 R1------+

V DD R2 R1------ =

G = Gain selection (1x or 2x)Dn = Digital value of DAC (0 255) for MCP4901/MCP4902

V OU T V RE F G Dn

2 N ------ =

= Digital value of DAC (0 1023) for MCP4911/MCP4912 = Digital value of DAC (0 4095) for MCP4921/MCP4922


DAC




R2

R1---------

2.05

V RE F -------------

2.05

4.1-------------= =

If R1 = 20 k and R 2 = 10 k , the gain will be 0.5

R2 R1------

1

2---=

R4 R3 R4+

-----------------------2.05 V 0.5 V RE F +

1.5 V RE F -----------------------------------------

2

3---= =

If R4 = 20 k , then R 3 = 10 k

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6.6 Selectable Gain and Offset BipolarVoltage Output Using DACDevices

In some applications, precision digital control of theoutput range is desirable. Example 6-4 illustrates howto use the DAC devices to achieve this in a bipolar or

single-supply application.

This circuit is typically used in Multiplier mode and isideal for linearizing a sensor whose slope and offsetvaries. Refer to Section 6.9 Using Multiplier Modefor more information on Multiplier mode.

The equation to design a bipolar window DAC wouldbe utilized if R 3 , R 4 and R 5 are populated.

EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET.

VREFA

DAC B

VDD

R3

R4

R2

DAC A

VDD

R1

DAC A (Gain Adjust)

DACB (Offset Adjust) SPI3

R5

VCC +

Thevenin

Bipolar Window DAC using R 4 and R 5

0.1uF

VCC

VCC +

VCC

V OUTB V RE FB G B D B2 N -------=

VOUTA

VOUTB

V OUTA V RE FA G A D A2 N -------=

V IN+ V OUTB R4 V CC- R3+

R3 R4+------------------------------------------------=

V O V IN+ 1 R2 R1------+

V OUTA R2 R1------ =

Equivalent V 45V CC+ R4 V CC- R5+

R4 R5+------------------------------------------- -= R45

R4 R5 R4 R5+------------------=

V IN+V OUTB R45 V 45 R3+

R3 R45+-----------------------------------------------= V O V IN+ 1

R2 R1------+

V OUTA R2 R1------ =

Offset Adjust Gain Adjust

Offset Adjust Gain Adjust

VREFB

GX = Gain selection (1x or 2x)

D A, DB = Digital value of DAC (0-255) for MCP4901/MCP4902 = Digital value of DAC (0-1023) for MCP4911/MCP4912 = Digital value of DAC (0-4095) for MCP4912/MCP4922


VO

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6.7 Designing a Double-PrecisionDAC

Example 6-5 illustrates how to design a single-supplyvoltage output capable of up to 24-bit resolution byusing 12-bit DACs. This design is simply a voltagedivider with a buffered output.

As an example, if a similar application to the onedeveloped in Section 6.5.1 Design Example:Design a bipolar dac using example 6-3 with 12-bitMCP4912 or MCP4922 required a resolution of 1 Vinstead of 1 mV and a range of 0V to 4.1V, then 12-bitresolution would not be adequate.

1. Calculate the resolution needed:4.1V/1 V = 4.1x 10 6 . Since 2 22 = 4.2 x 10 6,22-bit resolution is desired. Since DNL = 0.75LSB, this design can be done with the MCP4921or MCP4922.

2. Since the DAC Bs VOUTB has a resolution of 1 mV, its output only needs to be pulled 1/1000to meet the 1 V target. Dividing V OUTA by 1000would allow the application to compensate for DACBs DNL error.

3. If R 2 is 100 , then R 1 needs to be 100 k .4. The resulting transfer function is not perfectly

linear, as shown in the equation of Example 6-5 .

EXAMPLE 6-5: SIMPLE, DOUBLE PRECISION DAC WITH MCP4921 OR MCP4922.

VREF

DAC B

VDD

R2

DAC A

VDD

R1DAC A (Fine Adjust)

DACB (Course Adjust) SPI

3

R1 >> R 2

V OV OUTA R2 V OUTB R1+

R1 R2+-----------------------------------------------------=

G = Gain selection (1x or 2x)

D = Digital value of DAC (0-4096)

0.1 F

VCC +

VCC

V OUTA V RE FA G A D A2

12-------=

V OUTB V RE FB G B D B2

12-------=

VOUTA

VOUTB

VO

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6.8 Building Programmable CurrentSource

Example 6-6 shows an example for building aprogrammable current source using a voltage follower.The current sensor (sensor resistor) is used to convertthe DAC voltage output into a digitally-selectable

current source. Adding the resistor network from Example 6-2 wouldbe advantageous in this application. The smaller R senseis, the less power is dissipated across it. However, thisalso reduces the resolution that the current can becontrolled with. The voltage divider, or window, DACconfiguration would allow the range to be reduced, thusincreasing the resolution around the range of interest.

When working with very small sensor voltages, plan oneliminating the amplifiers offset error by storing theDAC's setting under known sensor conditions.

EXAMPLE 6-6: DIGITALLY-CONTROLLED CURRENT SOURCE.

DAC

RSENSE

Ib

Load

IL

VDD

SPI3-wire

VCC +

VCC

VOUT

I LV OU T

R se ns e---------------

1+------------=

I b

I L----=

G = Gain select (1x or 2x)Dn = Digital value of DAC (0-255) for MCP4901/MCP4902

V OUT V RE F G Dn

2 N ------

=



Common-Emitter Current Gainwhere

VREF

VDD or V REF




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6.9 Using Multiplier Mode

The MCP4901/4911/4921 and MCP4902/MCP4912/MCP4922 family devices use external reference, andthese devices are ideally suited for use as a multiplier/divider in a signal chain. Common applications are: (a)precision programmable gain/attenuator amplifiers and

(b) motor control feedback loops. The wide input range(0V V DD) is in Unbuffered mode, and near rail-to-railrange in Buffered mode. Its bandwidth (> 400 kHz),selectable 1x/2x gain and low power consumption givemaximum flexibility to meet the applications needs.

To configure the device for multiplier applications,connect the input signal to V REF and serially configurethe DACs input buffer, gain and output value. TheDACs output can utilize any of the examples from 6-1to 6-6 , depending on the application requirements.Example 6-7 is an illustration of how the DAC canoperate in a motor control feedback loop.

If the gain selection bit is configured for 1x mode( = 1 ), the resulting input signal will be attenuatedby D/2 n. With the 12-bit DAC (MCP4921 or MCP4922),if the gain is configured for 2x mode ( = 0 ), codesless than 2048 attenuate the signal, while codesgreater than 2048 gain the signal.

A DAC provides significantly more gain/attenuationresolution when compared to typical programmablegain amplifiers. Adding an op amp to buffer the output,as illustrated in Examples 6-2 through 6-6 , extends theoutput range and power to meet the precise needs of the application.

EXAMPLE 6-7: MULTIPLIER MODE USING V REF INPUT.

VCC +

VCC

VREF DAC

VRPM

+

VDD

SPI3

VOUT

R sense

VRPM_SET

ZFBMCP4901MCP4911MCP4921



V OU T V RE F G Dn

2 N ------ =

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7.0 DEVELOPMENT SUPPORT

7.1 Evaluation & DemonstrationBoards

The Mixed Signal PICtail Board supports theMCP4901/4911/4921 family of devices. Please refer towww.microchip.com for further information on thisproducts capabilities and availability.

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8.0 PACKAGING INFORMATION

8.1 Package Marking Information

Legend: XX...X Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week 01)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn)* This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note : In the event the full Microchip part number cannot be marked on one line, it willbe carried over to the next line, thus limiting the number of available charactersfor customer-specific information.

3e

3e

XXXXXXXXXXXXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXXXXXXYYWW

NNN

MCP4901E/P 256

1010

MCP4901E SN 1010

256

8-Lead MSOP Example:

XXXXXX

YWWNNN

4901E

010256

3e

3e

8-Lead DFN (2x3) Example:

XXXYWW

NN01025

AHS

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D

N

E

NOTE 1

1 2

EXPOSED PAD

NOTE 12 1

D2

K

L

E2

N

eb

A3 A1

A

NOTE 2

BOTTOM VIEWTOP VIEW

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D

N

E

E1

NOTE 1

1 2

e

b

A

A1

A2c

L1 L

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Note: For the most current package drawings, please see the Microchip Packaging Specification located athttp://www.microchip.com/packaging

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D

N

e

E

E1

NOTE 1

1 2 3

b

A

A1

A2

L

L1

c

h

h

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N

E1

NOTE 1

D

1 2 3

A

A1

A2

L

b1

b

e

E

eB

c

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APPENDIX A: REVISION HISTORY

Revision A (April 2010)

Original Release of this Document.

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PRODUCT IDENTIFICATION SYSTEMTo order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .

PART NO. X /XX

PackageTemperatureRange

Device

Device MCP4901: 8-Bit Voltage Output DACMCP4901T: 8-Bit Voltage Output DAC

(Tape and Reel)MCP4911: 10-Bit Voltage Output DACMCP4911T: 10-Bit Voltage Output DAC

(Tape and Reel)MCP4921: 12-Bit Voltage Output DACMCP4921T: 12-Bit Voltage Output DAC

(Tape and Reel)

Temperature Range E = -40 C to +125 C (Extended)

Package MC = 8-Lead Plastic Dual Flat, No Lead Package -2x3x0.9 mm Body (DFN)

MS = 8-Lead Plastic Micro Smal l Out line (MSOP)SN = 8-Lead Plastic Small Outline - Narrow, 150 mil

(SOIC)P = 8-Lead Plastic Dual In-Line (PDIP)

Examples:

a) MCP4901-E/P: Extended temperature,PDIP package.

b) MCP4901-E/SN: Extended temperature,SOIC package.

c) MCP4901T-E/SN: Extended temperature,SOIC packageTape and Reel.

d) MCP4901-E/MS: Extended temperature,MSOP package.

e) MCP4901T-E/MS: Extended temperature,MSOP packageTape and Reel.

f) MCP4901-E/MC: Extended temperature,DFN package.

g) MCP4901T-E/MC:Extended temperature,DFN packageTape and Reel.

h) MCP4911-E/P: Extended temperature,PDIP package.

i) MCP4911-E/SN: Extended temperature,SOIC package.

j) MCP4911T-E/SN: Extended temperature,SOIC packageTape and Reel.

k) MCP4911-E/MS: Extended temperature,MSOP package.

l) MCP4911T-E/MS:Extended temperature,MSOP packageTape and Reel.

m) MCP4911-E/MC: Extended temperature,DFN package.

n) MCP4911T-E/MC: Extended temperature,DFN packageTape and Reel.

o) MCP4921-E/P: Extended temperature,PDIP package.

p) MCP4921-E/SL: Extended temperature,SOIC package.

q) MCP4921T-E/SL: Extended temperature,SOIC packageTape and Reel.

r) MCP4921-E/MS: Extended temperature,MSOP package.

s) MCP4921T-E/MS: Extended temperature,

MSOP packageTape and Reel.

t) MCP4921-E/MC: Extended temperature,DFN package.

u) MCP4921T-E/MC:Extended temperature,DFN packageTape and Reel.

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Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE . Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyers risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,KEE LOQ , KEE LOQ logo, MPLAB, PIC, PICmicro, PICSTART,PIC 32 logo, rfPIC and UNI/O are registered trademarks ofMicrochip Technology Incorporated in the U.S.A. and othercountries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,MXDEV, MXLAB, SEEVAL and The Embedded ControlSolutions Company are registered trademarks of MicrochipTechnology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit SerialProgramming, ICSP, Mindi, MiWi, MPASM, MPLAB Certifiedlogo, MPLIB, MPLINK, mTouch, Octopus, Omniscient CodeGeneration, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,TSHARC, UniWinDriver, WiperLock and ZENA aretrademarks of Microchip Technology Incorporated in theU.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporatedin the U.S.A.

All other trademarks mentioned herein are property of theirrespective companies.

2010, Microchip Technology Incorporated, Printed in theU.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN:

Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in theintended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips DataSheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does notmean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protect ion feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwideheadquarters, design and wafer fabrication facilities in Chandler andTempe, Arizona; Gresham, Oregon and design centers in Californiaand India. The Companys quality system processes and proceduresare for its PIC MCUs and dsPIC DSCs, K EE LOQ code hoppingdevices, Serial EEPROMs, microperipherals, nonvolatile memory andanalog products. In addition, Microchips quality system for the designand manufacture of development systems is ISO 9001:2000 certified.

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AMERICASCorporate Office2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 480-792-7200Fax: 480-792-7277Technical Support:http://support.microchip.comWeb Address:www.microchip.com

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Santa Clara, CATel: 408-961-6444Fax: 408-961-6445

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