Chenghao (Peter) Chen Tel: (310) 801­3618                                                                                                                             6 Templeton E­mail: peter.hao@gmail.com                                                                                                             Irvine, CA 92602 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ Career Summary

Senior design engineer who is experienced in block level design, SoC integration, technology roadmap                           development and is heading up to chip lead position. 

 Experience Engineer Principal – IC Design, Broadcom Corporation, Irvine CA                 April 2007 ~ Present  

Cable Front End Receiver Chip Lead                                                                                    2016 ~ Present ➢ Achieve very aggressive three­month schedule from A0 silicone back to B0 production tape­out to lock in                               

customer design win. ➢ By prioritizing silicone verification plan, we were able to root cause all performance bugs, verify performance at                                 

process corners, bring up ATE vectors, establish screening yields, rule out false failure, develop firmware,                             complete production qualification and all other tier 1 tests within schedule and minimize production risk. 

➢ Minimize production cost by balancing bug fix and new features to fit into same die size and package. ➢ Excellent communication skills to summarize problems and solutions to bring management and engineering team                           

in sync and in agreement ➢ Proactive attitude to track and tackle every issue in time  SoC Core Lead                                                                                                                         2011 ~ Present ➢ Successfully integrate a host interface block that is essential to Set Top Box boot­up, system access and external                                   

Flash device access. ➢ Time tested design quality from 40nm to 28nm technology with consistent performance and reliability ➢ Lead a small and very efficient team through all phases of SoC project: architecture definition, IP integration,                                 

design verification, synthesis & layout sign­off, timing closure, gate level simulation, ATE pattern generation,                           silicone bring­up. Hands on experience in each phase. 

➢ Architect a host interface for 802.11ac WiFi enabled UHD video client SoC. This chip combines existingWLAN                                 chip into Set Top Box chip with a host interface bridges to a quad core ARM B53 CPU to both domains. The                                           customized host interface is capable of supporting very frequent register access in WiFi Dongle mode without                               stalling Set Top Box system. The architecture is designed to allow direct software transportation from existing                               WLAN chip and allows future software migration into host CPU platform to further reduce die cost in WLAN                                   block. The end result is a very smooth silicone bring­up that successfully streams 4Kp60 videos over WiFi in one                                     month from parts back. 

➢ Architect a host interface for a very complex routing gate way SoC that combines cable front end receiver,                                   GENET switch and Set Top Box video display. The customized host interface is partitioned to bridge a dual core                                     ARM B15 as both host and router CPU for best die cost yet allow independent sub­system access and reboot.                                     Software is isolated between each sub­system and each can run separate OS. This architecture also makes the chip                                   qualify for stringent Nagra & NDS security standard while allowing shortest time­to­market development by                           providing a flexible platform to share software from existing chips. 

 Flash Technology Lead                                                                                                           2010 ~ Present ➢ The “go to” person of all Broadband business groups for Flash technology knowledge, industry trend, vendor                               

roadmap and device application ➢ Consolidate Flash Storage interface and unify software sharing among all Broadband product lines to reduce                             

development overhead and cost ➢ Slashed die size, free up software resource and avoid mid cycle re­spin cost by defining a clear strategy that                                     

focuses on SLC NAND Flash development over MLC NAND.    

  

NAND Flash Controller Designer                                                                                     April   2007 ~ 2015 ➢ Contribute to all Broadband chips by designing and integrating a generic NAND Flash Controller that allows both                                 

XIP access for system boot and posted DMA access for bulk data transfer. ➢ Enhance controller features to follow vendor roadmap over the years. Improvement includes BCH­60 code, LFSR                             

based scrambler, blank page ECC protection, double throughput with cache mode and pipelined read/write, ONFI                             DDR interface at 100MHz.  

➢ Hands on experience from micro architecture definition to RTL implementation and verification with Verilog                           tests, Spygass Lint & CDC, Cadence Incisive code coverage tool. Improve design quality by building a self                                 sustained core bench that can easily expand and randomize usage parameter and timing sequence. 

 Education University of Southern California (USC), Los Angeles, CA                                               December 2006 M.S. in Electrical Engineering, GPA 3.76/4.0 National Chiao Tung University (NCTU), Taiwan                                                                           July 2004 B.S. in Communication Engineering 

Skills Language: Verilog, C, TCL Simulator: Debussy, Signal Scan, Simvision, NC Verilog Static Timing Analysis: Primetime, Goldtime Debug tool: Logic Analyzer, Spyglass CDC