MIAT20091112ESD-07UART

Synchronous Serial Standard

Asynchronous Serial StandardUniversal Synchronous/Asynchronous Receiver Transmitter (USART or UART)

Universal Asynchronous Receive TransmitAsynchronous Serial Standard

RS-232The UART input/output uses 0V for logic 0 and 5V for logic 1.The RS-232 standard (and the COM port) use +12V for logic 0 and 12V for logic 1.To convert between these voltages levels we need an additional integrated circuit (such as Maxims MAX232).

EIA Terminology DTE Data terminal equipment(computer) DCE Data communication equipment(modem) RxD Receiver data TxD Transmitter data DCD Data carrier detect (valid modem connection) DTR Data terminal ready (Computer on and software is ready) DSR -- Data set ready (Modem on and software ready) RTS Request to send (DTE wants to send character) CTS Clear to send (DCE acknowledge to RTS from DTE) RI Ring indicator from telephone

UART Communication ProtocolUARTLOWHIHIHILOW88HI

UART

UART IP

UARTTransmitter

UARTReceiver

BaudrateGenerator

TXD

RXD

Tx Enable

Tx Data8Bit

Rx Finish

Rx Data8Bit

Set

Rate16Bit

UARTI/O

05-200

mode

CLKSystem Clock 1 bitINPUT

RSTReset 1 bitINPUT

Set_RATEbaud rate1 bitINPUT

HIGH_RATE(8)8 bitINPUT

LOW_RATE(8)8 bitINPUT

TX_E1 bitINPUT

TX_DATA8 bitINPUT

RXDUARTRS2321 bitINPUT

TXUARTRS2321 bitOUTPUT

RX_DATA8 bitOUTPUT

RX_FINISH1 bitOUTPUT

TX_FINISH1 bitOUTPUT

ERR1 bitOUTPUT

Baud Rate for UARTBaud rateSystem Clockbaud rate150Mhz115200baud rate 150Mhz13021152070.006%

Baud Rate for UART168HILOW16115200 baud rate 1843200(150M/82)

Baud Rate Generator

Select BitsBAUD Rate00038,46200119,2310109615011480810024041011202110601111300.5

UART

Transmit GRAFCET

ReceiveGRAFCET

UART EntityENTITY UART ISPORT ( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; RXD : IN STD_LOGIC; SET_RATE : IN STD_LOGIC; HIGH_RATE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); LOW_RATE : IN STD_LOGIC_VECTOR(7 DOWNTO 0); TX_E : IN STD_LOGIC; TX_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); TXD : OUT STD_LOGIC; RX_DATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ERR : OUT STD_LOGIC; RX_FINISH : OUT STD_LOGIC; TX_FINISH : OUT STD_LOGIC);

Component-based ArchitectureARCHITECTURE RTL OF UART IS SIGNAL ENABLE_R_IO : STD_LOGIC; SIGNAL ENABLE_T_IO : STD_LOGIC; COMPONENT BaudRate_Generator PORT ( .. ); END COMPONENT BaudRate_Generator; COMPONENT Transmit_Module PORT ( ); END COMPONENT Transmit_Module; COMPONENT Received_Module PORT ( ); END COMPONENT Received_Module;BEGIN M0 : BaudRate_Generator PORT MAP(.); M1 : Transmit_Module PORT MAP (.); M2 : Received_Module PORT MAP (.);END RTL;

Baudrate Generator

Select BitsBAUD Rate00038,46200119,2310109615011480810024041011202110601111300.5

entity clk_divider is port(Sysclk, rst_b: in std_logic; Sel: in unsigned(2 downto 0); BclkX8: buffer std_logic; Bclk: out std_logic);end clk_divider;architecture baudgen of clk_divider is signal ctr1: unsigned(3 downto 0) := "0000"; -- divide by 13 counter signal ctr2: unsigned(7 downto 0) := "00000000"; -- div by 256 ctr signal ctr3: unsigned(2 downto 0) := "000"; -- divide by 8 counter signal Clkdiv13: std_logic;BaudRate_Generator VHDL Model

begin process(Sysclk) -- first divide system clock by 13 begin if (Sysclk'event and Sysclk = '1') then if (ctr1 = "1100") then ctr1

BaudRate_Generator VHDL Model(3) process(Clkdiv13) -- ctr2 is an 8-bit counter begin if (Clkdiv13'event and Clkdiv13 = '1') then ctr2

UART Transmitter

05-200

CLKClock baudrate1 bitINPUT

RSTReset 1 bitINPUT

S0S0 1 bitINPUT

TBAUDRATE_Ibaudrate1 bitINPUT

DATA_I8 bitINPUT

TXUARTRS2321 bitOUTPUT

READY_O1 bitOUTPUT

FINISH1 bitOUTPUT

UART Transmitter0Ready_REG = 0FINISH = 0TX1S0 = 111DATA_ITX_BUFFReady_REG = 1BitCnt_REGbaudrate TBAUDRATE_I=122TXTX_BUFF(0)TX_BUFF1BitBitCnt_REG33baudrate TBAUDRATE_I=044TBAUDRATE_I=1BitCnt_REG> 1BitCnt_REG ++

TBAUDRATE_I = 1

3

1

TBAUDRATE_I = 0

BitCnt_REG < 10 &TBAUDRATE_I = 1

5

BitCnt_REG >= 10 & TBAUDRATE_I = 1

/S0

FINISH

TX_Buff = DATA_I & 0BitCnt_REG = 0Ready_O = 0

UART Transmitter

UART Receiver

05-200

CLKSystem Clock 1 bitINPUT

RSTReset 1 bitINPUT

RXUARTRS2321 bitINPUT

DATA_O8 bitOUTPUT

ERR1 bitOUTPUT

FINISH1 bitOUTPUT

UART Receiver0BitCnt_REG = 0FINISH = 0UARTRX = 011SampleCnt_REG = 022RBAUDRATE_I=1SampleCnt_REG=84SampleCnt_REG=15633SampleCnt_REG54UARTRX RX_BUFF1SampleCnt_REG55RBAUDRATE_I=026BitCnt_REG177RBAUDRATE_I=0BitCnt_REG> 1SampleCNT_REG ++

6

BitCNT_REG ++

RBAUDRATE_I = 1 & SampleCNT_REG = 15

1

1

5

7

RBAUDRATE_I = 0

2

1

1

RBAUDRATE_I = 0 & BitCNT_REG = 10

8

9

1

FINISH

Data_O = RX_Buff(8~1)ERR = RX_Buff(9)

RBAUDRATE_I = 0 & BitCNT_REG < 10

UART Receiver