Post on 16-Jan-2016
description
IPAS SPring-8 FADC Project
章文箴蘇大順
04/26/2002
Super Photon Ring 8 GeV (SPring-8)
Harima Science Garden City
Laser Electron Photon
LEPS Detector Configuration
TPC inside LEPS Detectors
Time Projection Chamber
Working Principles of Time Projection Chamber
1. Passage of charged particles through the gas generates ionization electrons.
2. Electrons drift towards the readout plane along the imposed E x B drifting fields.
3. At the end of readout plane, an avalanche (amplification) will happen upon the arrival of electrons by the proportional sense wires and an induced image charge on the corresponding cathode pads.
4. The pads are connected with a read-out electronics which provides low-noise and high resolution analogue information as well as the drift time associated with the signal.
Electric Field Configuration
Grid Wire
Sense Wire
Field Wires
Cathod
Determination of the Particle Trajectory
Particle Identification by dE/dx vs. P
Time Projection Chamber at SPring-8 LEPS Experiment
Time Projection Chamber at Spring-8 LEPS Experiment
Readout Pads of TPC
Zoom-in View of Wires
TPC Inside the Solenoid Magnet at SPring-8
View of Particle Trajectory along the beam in
Simulation
TPC Mechanical Specification
• Inner radius: < 1.25 cm.• Outer radius: < 30 cm.• Read out channels: 95 sensing wires, 1000 pads.• Pad size:inner 8mm*8mm, outer 8mm*13mm.• Distance between sensing wires and pads: 4mm.• Separation of sensing wire: 4mm.• Cathode readout.• Maximum drift distance : about 70 cm.• Maximum drift time: about 14 sec with drift velocity
= 5.1 cm/sec.
Requirement of TPC Electronics
• Good energy resolution: measuring dE/dx from the charge readout of either wires or pads for the particle identification for K/p separation at low momentum.
• Requirement of spatial resolution:– x,y < 300 m.– z < 1 mm.
• Position information: – x(t),y(t): x from fired sense wires; y from interpolation of
signals on pads(t).– z(t) from time bin of FADC time slice.
• Timing information: fitting of pulse peak in FADC.• On-board zero-suppression to ensure fast data transfer and short
system dead time.
Digitizer in TPC Electronic: FADC
• Large data size:– High sampling rate: 40 MHz = 25 nsec.– Read-out bit (Nbit): 10 bits.– # of Time bins per event: ~600 time bins. (Max drift time/clock = 14
sec/25 nsec = 560 bins.)– 1000 channels.
• Trigger latency: 1 sec .• On-board zero-suppression.• Need of a large buffer size to store 4-5 events on board for
one single VME readout.(16*600*5=48K per channel, w/o a zero suppression factor.)
• High channel density.
SPring-8 FADC Module
– Use TEXONO FADC and IHEP BES version as the starting point.
– 40 MHz; 10-bit FADC: input 0-2 V range.– Shift register inside FPGA: length = trigger latency (1
s).– On-board FPGA for threshold suppression.– Buffer FIFO: dual port memory. – CPLD: controlling VME actions.– Free clock running.– VME 9U; 32 channels/module; 8 attached
cards/module; 4 channel/card.
Main Electronic Components
• Receiver: MAXIM, MAX4145ESD.
• OPA: Analog Device, AD8138ARSO-8.
• FADC: Analog Device, AD9203ARVRU-28.
• FPGA: Xilinx, XC2S150-6FG456.
• FIFO: TI, SN74V245.
SPring-8 FADC Module(4 channels, 10 bits, 40 MHz)
OPA
FADC
FPGA
FIFO
40 MHz sampling rate.10 bits resolution with 2Vp-p dynamic range.Clock distribution with Phase Lock Loop circuit.On Board digital signal delay and Real-Time ZERO-Suppression.High capacity First In First Out Memory.Easy to use with high density connector.
Mixed signal AD Converter Adapter Board
FADC Mother Board
CPLD
Driver
Clock Driver
VME Connector
FPGA, digital signal control chip.
First In First Out memory.
VMEBus slave controller, with high performance BLTransfer Mode.
32 Channels, high sampling rate Flash AD converter.
Differential AD Converter (40 MHz)
16 channels differential signal input connector.
Spring-8 2002/03
Receiver & Driver FADC
Differential Signal from MAMP
10
Hit Flag FIFO
Processing FPGA
ClockTrigger
Receiver & Driver FADC
10
Receiver & Driver FADC
10
Receiver & Driver FADC
10
CH 1
CH 4
CH 3
CH 2
x 8Four ChannelsFour Channels
VA[8..23]
Trigger Counter
Trigger FIFO
VME Control
12
DelayWrite
VME_ResetCheck Trigger NumberClear Trigger FIFORead Trigger FIFO
VD[0..11]
VD[0..11]
x 8
Rea
dR
ST
Read FlagW
rite
Fla
g
Global FPGAGlobal FPGA
JTAG
VD[0..31]
VD[0..31]
VA[8..15]
4 Fla
g
Reset
Download PROM
VD1
VA1
VCAS,D0,D1,AM[0..5],Write,DTACK, et. al.
8 bits DIP Switch
8
Write_inRead_out
Download PROM
Shift Register 10 bits Data
Threshold
Comparator
32 bits FIFO10
10
Trigger
Clock Counter & Control
Enable
Clock
Over_Threshold
Comp_Control
Write_header&trailerClock
RstReset
VD[0…15]
VA[8…15]
Re
ad
Wri
t e
Ena
ble W
rite
Disable Clear
Count
Write_Data
Write_Flag
Read
Write Flag
S
R
QFlag
10
10
L=(Trigger Latency + 1)
VA2
VD2
Fig. 2 Block Diagram of Processing FPGA
Clo
ck
Data Format
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
CS 0 0 1 ND FADC Module Number (1-64) Channel Number (1-32)
CS 0 1 0 ND ND ADC (0-1024)
CS 1 0 0 ND ND Number of ADC data bins (0-600)
CS 0 1 1 ND ND Time (0-1024)
Header 1
ADC
Time
Trailer
CS: Checksum bit
ND: Not defined.Lowest Bit
CS 0 0 1 ND Event Number (1-5)Header 2
CSR Format
16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01
Reset
Sampling Count: default value 1020.
VME address: 0x010000
Lowest Bit
1
1 0 0 Last six digits of number of sampling count.
FADC VME Action List (A24/D16)
• 0x0i0000: address to write, bit 9 for resetting FIFO and set ready, bit 10 for resetting suppression threshold and bit 11 for setting the sample count of the FADC i. (Address modifier: 0x3D).
• 0x0i0100: address to read the merged 32 FIFOs’ content in BLT mode for FADC i. (Address modifier: 0x3B, 0x3F).
• 0x0i0101: address to read the BLT reading cycle for FADC i. (Address modifier: 0x3B, 0x3F).
• 0x0i0000+j*0x000100: address to read the single FIFO content in AO mode for channel j. (Address modifier: 0x3D)
• 0x0i0000+j*0x000100: address to write for setting the zero-suppression threshold for channel j. (Address modifier: 0x3D)
The Control Flow of FADC
< 5 events
Send IRQ to VME CPU
DAQ READ FIFO
DAQ send Reset
FADC clear BUSY
Clear trigger Veto
Yes
No
DAQ Start
Trigger Count *Veto
NIM
CPLD FADC Trigger Clock 100MHz
Trigger signal
Trigger
FADC
Busy
FADC Module
Preamplifier Module
For each channel
VME
CPU
Reset
Master
Slave
Trigger , Conversion
Observation Window of Signals
Signal
Trigger
Conversion Strobe
Sampling Counts ( max 1024*25ns=25s)
Shift Register Length ( max 100*25ns = 2.5 s)
DAQ Trigger Logic TEXONO
MAMP
LTDS1
Rst
LTD0
Strb
SCLK
HTD0
Evnt
H VT
L VT
LeCroy222
START
OR
BLANK
STOP
NIM
DELTTL
NIM
BUSY
1.0
10
100
1.0 10100
1.0
LATCH
10
Full scale width
START
OR
BLANK TTL
NIM
BUSY
1.0
10
100
1.0 10100
1.0
LATCH
10
Full scale width
STOP
DEL
NIM
FB
SY
INT
RE
AD
CLK
Bus
y
Res
et +5V +12V -12V-5.2V SPring-8 32-channel FADC
Trig
ger
Voltage Reference
Clock Generator
TEXONO Online Event Display
(400 KHz sine wave)
TEXONO Online Event Display
(1 MHz sine wave)
ROOT Offline Event Display for 2 SPring-8 FADC (64
channels)Module 1
Module 2
Events
• 02/09/2001: Prof. Imai and Ahn visited AS. Collaborating plan was discussed and finalized.
• 03/31/2001: Wen-Chen and Henry visited IHEP, Beijing and explored the R&D plan in IHEP.
• 05/31/2001: IHEP was not able to perform the R&D plan.• 08/01/2001: Da-Shun visited IHEP for 3 weeks to learn the
conceptual design.• 02/01/2002: Prototype 1 boards made.• 02/28/2002: Wen-Chen and Da-Shun tested prototype-1
boards with TPC at SPring-8.• 04/25/2002: Finished up 64 channels of prototype-1 and
deliver them to SPring-8.
Plan
• 04/30/2002: Issue out prototype-2 (quasi-final) fabrication order.
• 05/21/2002: Deliver prototype-2 to SPring-8.• 06/01/2002: System test with a complete electronic chain (Pre-
amp, shaper, and FADC) with TPC and Solenoid magnet.• 06/15/2002: Issue out final production fabrication order (1440
channels).• 07/01/2002: Send production boards for stuffing.• 07/15/2002 – 07/31/2002: Test production boards.• 08/01/2002 – 08/31/2002: Delivery of production board,
installation, system test and DAQ.• 09/15/2002: Commission Run with photon beam.
Remarks
• Many valuable experiences learned: board design, firmware, modification of TEXONO DAQ, coordinating people, etc.
• A good starting point for a continuing “rooting” process of experimental technique at IPAS.
• Thanks to many people: Henry, P.K., A.C., K.C., Tracy, IHEP group….