Wire Planning with consideration of Electromigration and Interference Avoidance in Analog Circuits

Wire Planning with consideration of Electromigration and Interference

Avoidance in Analog Circuits

演講者 : 黃信雄

龍華科技大學電子工程系

Outline

Introduction Preliminary Algorithms Experimental Result Conclusion and Future Work

Introduction(1) Electromigration (abbreviated as EM) due to

insufficient wire width can cause the premature failure of a circuit. 1000mA

EM reduce the product circuit life

open

short

We must improve reliability

open

short[11] J. Lienig and G. Jerke, “Current-Driven Wire Planning for Electrimigration Avoidance in Analog Circuits,” in Proc of Asia and South Pacific Design Automation Conference, pp. 783-788, 2003.

These pictures are published in [11]

Introduction(2)

Circuit Simulation

Schematic

Partitioning+Floorplanning

Placement

Current-Driven Routing

Start

Current-Density Verification

EMViolations

Yes

No

Current-Density LayoutDecompaction

Electromigration-Robust Design

PhysicalDesign

1. Wire planning

2. Detail routing

Electromigration reduce circuit life

Total wiring area :840

Avoid electromigration to increase circuit life

Total wiring area :1830Electromigration aware

analog design flow

Avoid electromigration to increase circuit life

Total wiring area :2520

Introduction (3)

Previous Works Minimize total wiring area without obstacle

Greedy-based approach [11] [19] Minimize total wiring area with obstacle

Greedy-based approach [1][12] Minimize total wiring area without interference consideration

Greedy-based approach [1] [11] [19][12]

[11] J. Lienig and G. Jerke, “Current-Driven Wire Planning for Electrimigration Avoidance in Analog Circuits,” in Proc of Asia and South Pacific Design Automation Conference, pp. 783-788, 2003.

[19] J.T. Yan Z.W. Chen and D.H. Hu, “Electromigration-Aware Rectilinear Steiner Tree Construction for Analog Circuits,” in Proc. of 18-th VLSI Design and CAD Symposium, CD-ROM, 2008.

[1] T. Adler and E. Barke, “Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications,” in Proc. of Design, Automation and Test in Europe, pp. 446-450, 2000.

[12] J. Lienig, G. Jerke, T. Adler, “Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing,” in Proc. of IEEE International Symposium on VLSI Design, pp. 372-37, 2002.

Introduction (4)

Contributions First, to avoid the electormigration of the circuit, the

greedy-based approach, which formulates the problem into the graph model, is used to automatically determine the feasible connections between sources and targets with the proper wire width.

Second, to avoid the interference between the obstacle and wires, the space reservation [5][11] is utilized for all obstacles.

Third, the proposed method efficiently determines the routing path to reduce the total wiring area.

Outline

Introduction Preliminary

Terminology Problem Formulation

Algorithms Experimental Result Conclusion and Future Work

Terminology(1) - Adjust Line

If we can not find the feasible path by two pattern routing, the shorter line is applied.

Terminology(1) - Adjust Line

The length from the source and target. is computed as follows [9],

where and are the additional wire lengths of the upper-L and low-L routing paths from source to target with the obstacle k,

1

( , ) | | | |

(min ( , , , ))) ( , ,

i j i j

k

ilu lenlen

d

i

i j x x

j k

y

i j

y

k

( , , )llen i j k( , , )ulen i j k

Terminology(2) - Wiring area To avoid the EM, the wire width is proportional to

current value. We have the formula,

where and are the wire width and

current value for source i and target j, respectively. Therefore, the wiring area is computed as,

where is the constant.

1S

6t

(1,6) 2c

(100,200)

(150,250) = (1,6) (1,6)

= 2 (|150 100 | | 250 200 |)

= 200

A c d

( , ) ( , )w i j c i j

, ,

A ( , ) ( , ) ( , ) ( , )i j i j

w i j d i j c i j d i j

( , )w i j ( , )c i j

Terminology(3) - Interference Predefined IP is regards as the obstacles To avoid the interference Space reserve the dead-space for obstacles

interfserious erence

wires in IP (obstacle)wires in chip

virtual obstacleoriginal obstacle

space reservation interferless ence

Problem Formulation

Given:

A set of sources S = {s1 , s2 ,…, sn} with their corresponding

root-mean-square (RMS) current values {O1 , O2 ,…, On}.

A set of targets T = {t1 , t2 ,…, tm} with their corresponding

root-mean-square (RMS) current values {I1 , I2 ,…, Im}.

A set of rectangular obstacles B = { b1 , b2 ,…, bk}.

Objective: To construct an wire planning result with minimal wiring area

by consideration of the obstacles and electromigration

(abbreviated as EM).

Outline

Introduction Preliminary Algorithms

ILP-based Algorithm Graph-based Algorithm

Experimental Result Conclusion and Future Work

ILP-based Algorithm(1)

Input: (1) A set of sources and a set of targets (2) Their equivalent RMS current values (3) A set of obstaclesOutput: A EM-aware wire planning with minimal area Method: Step 1. Perform space reservation for obstacle;

Step 2. Calculate the Length for Source-Target pairs;

Step 3. Determine the Topology by ILP Formulations ;

Step 4. Transform the M-architecture Results;

Perform space reservation for obstacle

The user-defined space Construct a better wire planning with less

interference

dU

Initial circuits

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

(150,250)

(100,200)

(100,100)

(200,150) (250,150)

(200,50)

Construct the bipartite graph

1s

2s-5

-6

1S

2S

5

6


1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Calculate all source-to-target wirelengths

The wirelength of each source-target is computed The length is integrated into the ILP formulations.

d(1,3)=250;

d(1,4)=150;

d(1,5)=200;

d(1,6)=100;

d(2,3)=180;

d(2,4)=150;

d(2,5)=200;

d(2,6)=200;

ILP formulations

1

( , ) | | | |

(min ( , , , ))) ( , ,

i j i j

k

ilu lenlen

d

i

i j x x

j k

y

i j

y

k

1S

2S2S

1S

Determine the topology with proper wire width

Determine the topology with proper wire width by ILP formulations.

,

( , ) ( , )i j

Minimize A c i j d i j

1

( , ) m

ij

c i j O

1

( , ) n

ji

c i j I

Subject to

Kirchoff’s current law

Total wiring Area

Source driving current constraint

Target sinking current constraint

:

( , ) : Current from source to target

( , ) : Manhattan distance from source to target

: RMS Current values of source

i

j

where

c i j i j

d i j i j

O i

I : RMS Current values of target

: Coefficient between current value and the wire width

j

Wire width

1

,

( , ) ( , ), {1,2,..., }, {1,2,..., }i j

A c i j d i j i n j m

1 1

m n

j ij i

I O


min=wiring_area;wiring_area=c(1,4)*d(1,4)+c(1,5)*d(1,5)+c(1,6)*d(1,6)+c(1,7)*d(1,7)+c(1,8)*d(1,8)+C(1,9)*d(1,9)+c(1,10)*d(1,10)+c(2,4)*d(2,4)+c(2,5)*d(2,5)+c(2,6)*d(2,6)+c(2,7)*d(2,7)+c(2,8)*d(2,8)+c(2,9)*d(2,9)+c(2,10)*d(2,10)+c(3,4)*d(3,4)+c(3,5)*d(3,5)+c(3,6)*d(3,6)+c(3,7)*d(3,7)+c(3,8)*d(3,8)+c(3,9)*d(3,9)+C(3,10)*d(3,10);d(1,4)=18;d(1,4)=2070;d(1,5)=10850;d(1,6)=15190;d(1,7)=14570;d(1,8)=14190;d(1,9)=10200;d(1,10)=9330;d(2,4)=8850;d(2,5)=8270;d(2,6)=5950;d(2,7)=5450;d(2,8)=8850;d(2,9)=12780;d(2,10)=10290;d(3,4)=5030;d(3,5)=5430;d(3,6)=10390;d(3,7)=9770;d(3,8)=9070;d(3,9)=5700;c(1,4)+c(1,5)+c(1,6)+c(1,7)+c(1,8)+c(1,9)+c(1,10)=14;c(2,4)+c(2,5)+c(2,6)+c(2,7)+c(2,8)+c(2,9)+c(2,10)=32;c(3,4)+c(3,5)+c(3,6)+c(3,7)+c(3,8)+c(3,9)+c(3,10)=43;c(1,4)+c(2,4)+c(3,4)=10;c(1,5)+c(2,5)+c(3,5)=10;c(1,6)+c(2,6)+c(3,6)=9;c(1,7)+c(2,7)+c(3,7)=14;c(1,8)+c(2,8)+c(3,8)=16;c(1,9)+c(2,9)+c(3,9)=13;c(1,10)+c(2,10)+c(3,10)=17;

c(1,3) = 0; d(1,3)= 250

c(1,4) = 0; d(1,4)=150

c(1,5) = 3; d(1,5)= 100

c(1,6) = 2 ; d(1,6)= 200

c(2,3) = 2; d(2,3)= 180;

c(2,4) = 3; d(2,4)= 50;

c(2,5) = 0; d(2,5)=200;

c(2,6) = 1; d(2,6)= 200;

ILP solver

ILP formulations

Result

Wiring area

wirelenth

Source driving current constraint

Target sinking current constraint


After solving the ILP formulations , the connection is not exist if the current capacity is equal to zero.

Result

c(1,3) = 0; d(1,3)= 250

c(1,4) = 0; d(1,4)=150

c(1,5) = 3; d(1,5)= 100

c(1,6) = 2 ; d(1,6)= 200

c(2,3) = 2; d(2,3)= 180;

c(2,4) = 3; d(2,4)= 150;

c(2,5) = 0; d(2,5)=200;

c(2,6) = 1; d(2,6)= 200;

1S

2S

6t

4t 5t

3t

32

2

3 1

1

Final EM-Oriented results

Wiring area is 1710

3 1001S

2S

6t

4t 5t

3t

2 200

2 180

3 150

1 200

Outline

Introduction Preliminary Algorithms

ILP-based Algorithm Graph-based Algorithm

Experimental Result Conclusion and Future Work

Algorithm

Input: (1) A set of sources and a set of targets (2) Their equivalent RMS current values (3) A set of obstaclesOutput: A EM-aware wire planning with minimal area Method: Step 1. Perform space reservation for obstacle; Step 2. Construct the bipartite graph; Step 3. Sort the weights of all edges; Step 4. Update weights of the relative edges; Step 5. Terminates until sources current are zero; Step 6. Adjust the invalid edges Step 7. Transform virtual obstacle into original one

Perform space reservation for obstacle

The user-defined space Construct a better wire planning with less

interference

dU

Initial circuits

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

(150,250)

(100,200)

(100,100)

(200,150) (250,150)

(200,50)


1s

2s-5

-6

1S

2S

5

6


1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2


To minimize total wiring area, the weights of all edges in the complete bipartite graph are assigned by the formula,

where is the Manhattan distance for source i and target j. is a user-defined constant.

( , ) ( , )weight i j d i j

1S

6t

5

3(100,200)

(150,250)( , ) 1 (|150 100 | | 250 200 |)

100

weight i j

( , )d i j


1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1 0 01S

2S

6t

4t 5t

3t

5

6

3

3 3

2

(1,6) 1 100weight


1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1 0 0

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Sort the weights of all edges

The edge with smallest weight is first selected. 100(s1t6) The other weights are 150,150,150,200,200,200

1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1 0 0

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

Remove the edge – iteration 1

The wire is built.

1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

1 0 0

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Update weights of the relative edges – iteration 1

The current of source and target are updated.

1s

6t

5t

2s-2

-6

+0

+3

4t

3t

+3

+2

1 0 0

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Update weights of the relative edges- iteration 1

The selected edge is removed .

1s

6t

5t

2s-2

-6

+0

+3

4t

3t

+3

+2

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2


The edge with small weight is selected.

1s

6t

5t

2s-2

-6

+0

+3

4t

3t

+3

+2

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2


The wire is built.

1s

6t

5t

2s-2

-6

+0

+3

4t

3t

+3

+2

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2


The current of source and target are updated.

1s

6t

5t

2s-0

-6

+0

+3

4t

3t

+1

+2

2 0 0

150

150

2 0 0

2 0 0

1 5 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Update weights of the relative edges– iteration 2

The selected edge is removed .

1s

6t

5t

2s-0

-6

+0

+3

4t

3t

+1

+2

2 0 0

150

150

2 0 0

2 0 0

2 5 0

1S

2S

6t

4t 5t

3t

5

6

3

3 3

2

Terminates until sources current are zero

The similar method is performed until the current of all sources have been assigned.

1s

6t

5t

2s-5

-6

+3

+3

4t

3t

+3

+2

100

150

200

150

150

1S

2S

6t

4t 5t

3t

3

2

1

2

3

Adjust the invalid edges

The invalid edge is adjusted by the push_line algorithm mentioned before.

1S

2S

6t

4t 5t

3t

EM-oriented (long lifetime)

Wiring are = 1830

Transform virtual obstacle into original one

The invalid edge is adjusted by the push_line algorithm mentioned before.

EM-oriented (long lifetime)

Wiring are = 1830

Less interference

1S

2S

6t

4t 5t

3t

Comparison of graph and ILP-based methods

Wiring area =1830

ILP-based method (Effective) Graph-based method (Efficient)

Wiring area = 1710

Outline

Introduction Problem Formulation Algorithms Experimental Result Conclusion and Future Work

Outline

Introduction Preliminary Algorithms Experimental Result Conclusion and Future Work

Experimental Result(cont’d) Platform

Name Specification

HardwareIBM Personal

ComputerPentium (R) D – 3GHz with

2GB RAM

OSMicrosoft

WindowsXPMicrosoft WindowsXP

Language C++ language Visual C++ 6.0

ILP Solver Lingo 11 Lingo 11

Experimental Result (cont’d)

( / ) 100ob ob chipR A A

: all area of obstacles

: chip areaob

chip

A

A

Circuit No. of obstacle

Rob (%) No. of source

No. of target

r1 10 8.2 3 7

r2 10 50.7 10 20

r3 10 21.7 16 34

r4 10 39.4 23 47

r5 10 29.2 33 67

r6 300 10.7 66 134

[7] H.H. Huang, S.P. Chang, Y.C. Lin and T.M. Hsieh, “Timing-Driven X-Architecture Router among Rectangular Obstacles,” in Proc. of IEEE International Symposium on Circuits and Systems, pp. 1804-1807, 2008.

Experimental Result (cont’d)

Comparison of the wiring area of graph-based and ILP-based method, the additional wiring area is reduced by 13.24%.

The ILP-based method works efficiently.

Outline

Introduction Problem Formulation Algorithms Experimental Result Conclusion and Future Work

Conclusions and future work

First, the proposed ILP formulations determines the wire connections with the proper wire width by RMS current values of sources and targets . Our ILP-based method optimize wiring area without

obstacles.

Second, our method integrates the electromigration with obstacle for analog circuits to minimize the wiring area.

Third, the space reservation technique is used to avoid the interference between the wires and obstacles.

Compared to the results of greedy graph-based method, the proposed ILP-based method improved 13.24% wiring area on average.

Future work

The concept of signal integrity is considered to reduce the percentage of transformed edges[11].

How to obtain the better X-architecture results?

0tR 0.5tR

(a) signal loss (b) signal integrity

[11] J. Lienig, “Introduction to Electromigration-Aware Physical Design,” in Proc. of ACM International Symposium on Physical Design, pp.39-46, 2006.

Thank for your listening!

Wire Planning with consideration of Electromigration and Interference Avoidance in Analog Circuits

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