9/13/05 ELEC5970-001/6970-001 Lecture 6 1

ELEC 5970-001/6970-001(Fall 2005)Special Topics in Electrical EngineeringLow-Power Design of Electronic Circuits

Dynamic Power

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University

http://www.eng.auburn.edu/~vagrawalvagrawal@eng.auburn.edu

9/13/05 ELEC5970-001/6970-001 Lecture 6 2

CMOS Dynamic PowerDynamic Power = Σ 0.5 αi fclk CLi VDD

2

All gates i

≈ 0.5 α fclk CL VDD2

≈ α01 fclk CL VDD2

where α average gate activity factorα01 = 0.5α, average 0→1 trans.fclk clock frequencyCL total load capacitanceVDD supply voltage

9/13/05 ELEC5970-001/6970-001 Lecture 6 3

Example: 0.25μm CMOS Chip

• f = 500MHz

• Average capacitance = 15fF/gate

• VDD = 2.5V

• 106 gates

• Power = α01 f CL VDD2

= α01×500×106×(15×10-15×106) ×2.52

= 46.9W, for α01 = 1.0

9/13/05 ELEC5970-001/6970-001 Lecture 6 4

Signal Activity, α

T=1/f

Clock α01= 1.0

α01= 0.5

α01= 0.5

Comb.signals

9/13/05 ELEC5970-001/6970-001 Lecture 6 5

Reducing Dynamic Power

• Dynamic power reduction is– Quadratic with reduction of supply voltage– Linear with reduction of capacitance

9/13/05 ELEC5970-001/6970-001 Lecture 6 6

0.25μm CMOS Inverter, VDD=2.5V

0

-4

-8

-12

-16

-20

Vin (V)

Vou

t (V

)

Vin (V)

2.5

2.0

1.5

1.0

0.5

00 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 1.5 2.0 2.5

Gai

n

9/13/05 ELEC5970-001/6970-001 Lecture 6 7

0.25μm CMOS Inverter, VDD< 2.5V

0.2

0.15

0.1

0.05

0

Vin (V)

Vou

t (V

)

Vin (V)

2.5

2.0

1.5

1.0

0.5

00 0.5 1.0 1.5 2.0 2.5 0 0.05 0.1 0.15 0.2

Vou

t (V

)

Gain = -1

9/13/05 ELEC5970-001/6970-001 Lecture 6 8

Lower Bound on VDD

• For proper operation of gate, maximum gain (for Vin = VDD/2) should be greater than 1.

• Gainmax = -(1/n)[exp(VDD /2ΦT) – 1] = -1 • n = 1.5

• ΦT = kT/q = 26mV

• VDD = 48V

• VDDmin > 2 to 4 times kT/q or ~100mV at room temperature (27oC)

• Ref.: J. M. Rabaey, A. Chandrakasan and B. Nikolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003.

9/13/05 ELEC5970-001/6970-001 Lecture 6 9

Impact of VDD on Performance

CLVDD

Inverter delay = K ───────(VDD – Vt )α

0.6V 1.8V 3.0V VDD

Power

Delay

40

30

20

10

0

Del

ay (

ns)

VDD=Vt

9/13/05 ELEC5970-001/6970-001 Lecture 6 10

Optimum Power × Delay VDD

3

Power × Delay, PD = constant × ─────── (VDD – Vt)α

For minimum power-delay product, d(PD)/dVDD = 0

3VtVDD = ───

3 – α

For long channel devices, α = 2, VDD = 3Vt

For very short channel devices, α = 1, VDD = 1.5Vt

9/13/05 ELEC5970-001/6970-001 Lecture 6 11

Transistor Sizing for Performance

• Problem: If we increase W/L to make the charging or discharging of load capacitance, then the increased W increases the load for the driving gate

Cin CL

9/13/05 ELEC5970-001/6970-001 Lecture 6 12

Fixed-Taper Buffer

VinVout

CLCin

1 α α2 αi-1 αn-1

Ci = αi-1Cin

CL = αnCin

Delay= t0

Ref.: J. Segura and C. F. Hawkins, CMOS Electronics, How It Works,How It Fails, Piscataway, New Jersey: IEEE Press, 2004.

9/13/05 ELEC5970-001/6970-001 Lecture 6 13

Buffer (Cont.)

αn = CL/Cin

ln (CL/Cin)n = ──────

ln α

ith stage delay, ti = αt0, i = 1, . . . n, because each stage drives a stage α times bigger than itself.

9/13/05 ELEC5970-001/6970-001 Lecture 6 14

Buffer (Cont.)

nTotal delay = Σ ti = nαt0

i=1

= ln(CL/Cin) αt0/ln(α)

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Buffer (Cont.)

Differentiating total delay with respect to α and equating to 0, we get

αopt = e ≈ 2.7

The optimum number of stages is

nopt = ln(CL/Cin)

9/13/05 ELEC5970-001/6970-001 Lecture 6 16

Further Reading

B. S. Cherkauer and E. G. Friedman, “A Unified DesignMethodology for CMOS Tapered Buffers,” IEEE Trans.VLSI Systems, vol. 3, no. 1, pp. 99-111, March 1995.