USB OTG 晶片設計 指導教授 : 詹景裕 教授 研究生 : 柳彥祺 國立台灣海洋大學...

Click here to load reader

download USB OTG 晶片設計 指導教授 : 詹景裕 教授 研究生 : 柳彥祺 國立台灣海洋大學 資訊工程所.

of 14

  • date post

    21-Dec-2015
  • Category

    Documents

  • view

    293
  • download

    1

Transcript of USB OTG 晶片設計 指導教授 : 詹景裕 教授 研究生 : 柳彥祺 國立台灣海洋大學...

  • Slide 1
  • USB OTG : :
  • Slide 2
  • Outline USB USB OTG USB OTG USB OTG
  • Slide 3
  • USB USB (Master/slave system) (PC) USB-IF 2001 12 USB 2.0 On-The-Go (OTG) (Dual-role Device) HNP (Host Negotiation Protocol) SRP (Session Request Protocol) USB (Host) (Peripheral)
  • Slide 4
  • USB 1.1 USB 1.1 SIE (Serial Interface Engine) I2C USB 1.1control UTMI (USB 2.0 Transceiver Macrocell Interface) UTMI+ OTG USB 1.1 OTG
  • Slide 5
  • USB USB OTG (mini) USB ID pin ID A-device B- device
  • Slide 6
  • USB OTG USB OTG USB OTG VBUS USB OTG SRP USB OTG VBUS (Session) USB OTG HNP
  • Slide 7
  • USB OTG USB OTG USB 1.1 (Verilog HDL) USB OTG
  • Slide 8
  • USB OTG USB OTG Chip Architecture
  • Slide 9
  • USB OTG Verilog RTL Synopsys FPGA Compiler (synthesis) ALTERA Quartus II FPGA Verilog Model Technology Inc ModelSim Altera (FPGA) Apex 20K400 EBC1-X Philips ISP1301 USB OTG
  • Slide 10
  • USB OTG FPGA
  • Slide 11
  • USB OTG FPGA CATC
  • Slide 12
  • USB OTG ASIC (CIC) Cell Based IC Design CIC TSMC 0.35 m cell library Synopsys Design Compiler Synopsys DFT compiler Scan Chain (layout) Synopsys Astro DRC/ERC LVS Dracula ModelSim TimeMill (Post-Layout simulation) PowerMill
  • Slide 13
  • USB OTG USB OTG Layout Technology0.35um 2P4M Max. frequency48.1 MHz Power dissipation16.081 mW I/Oasynchronous Die size (with DFT; without I/O pad) 2.2552.255 mm 2 Chip size (with DFT and I/O pad) 3.0833.083 mm 2 Average # of clock cycles 160
  • Slide 14
  • USB OTG USB USB OTG 8051 ARM ROM USB OTG PDA (Personal Digital Assistant) OTG Software Embedded System