Synthesis Methodology - mspic.ee.nchu.edu.twmspic.ee.nchu.edu.tw/dip_ppt/TOPIC2_SYNTHESIS/5.pdf ·...

DIP

1

Synthesis Methodology

DIP

2

Objectives

Learn logic synthesis in the real world.Develop the required expertise to use Synopsys Design CompilerChip synthesis methodology.Synthesis strategy for timing optimization.Timing closure and links to layout problems.

DIP

3

Text Books

Logic Synthesis Using Synopsys by PranKurup and Taher Abbasi

Advanced ASIC Chip Synthesis by Himanshu Bhathagar.

DIP

4

Topics

ASIC Design MethodologyPartitioning and Coding StylesConstraining and Optimizing DesignsLinks to Layout & Post Layout OptimizationInterfacing between CAD toolsDesign Re-Use using Design Ware

DIP

5

Topics

ASIC Design MethodologyBasic Concepts in Design CompilerPartitioning and Coding StylesConstraining and Optimizing DesignsLinks to Layout & Post Layout OptimizationInterfacing between CAD tools.Design Re-Use using Design Ware

DIP

6

What does Synthesis do?Synthesis = Translation + Optimization + Mapping

X

DIP

7

Synthesis problems are NPPoorStartpoint Better

Startpoint

BestStartpoint

Good

The quality of sources (RTL codes, script fileand constraint) are important.

DIP

8

Synthesis problems in SOC

Todays EDA tool flow, functional realm and physical world is separateIn deep-submicron the dominating factor is interconnect, not gates.The effects of inaccurate wire-loadmodels are not discovered until after placement and routing.

DIP

9

Begin With a Chip Specification

Operating frequency Chip function Chip I/O target Test requirements

- CPU Specification

Freq: 66 Mhz I/O: 40

Fault Coverage: 99%Operating Conditions:

Worst Case Commercial Functional Description:

DIP

10

Partition Chip

RTL description for each block. Floorplan for wire load estimation.

BUS_XFACE

BUSDECODE

STATE_MACHINE

ALU_BLOCK

ALU

TOP

DIP

11

RTL SynthesisWrite RTL

Source Code

HDL

Simulate

Floorplanner(create new wireload)

Synthesize To Gates

Check Constraints

Check for Test

GTECH Analysis

Mapped Analysis

DesignWareLibraries

TechnologyLibrary

Script Files

Constraints

DIP

12

Build Chip Hierarchy by Integrating BlocksIntegration may cause fanout problems.

Re-optimize to fix any problems.

BUS_XFACE

STATE_MACHINE

ALU_BLOCK

DIP

13

Insert Test Structures

Scan insertion swaps flip-flops with scannable filp-flops => cause timing violation=>re-optimize

TOP

JTAG

DIP

14

Insert I/O Pads

Peripheral timing paths can be affected, and hence re-optimized.

TOP

JTAG

DIP

15

Floorplan Chip Floorplan top levels for global loading on nets.

JTAG

TOPALU_BLOCKBUS_

XFACE

STATE_MACHINE

Completed Chip Netlist

Re-Optimize

Next StepYes

Floorplan Design

BackAnnotate RCs,Timing Physical Hierarchy

NoConstraints Met?

DIP

16

Place & Route Chip

Discrepancies may still exist. Back annotation.

Chip-Level Netlist

Place & Route

Constraints Met?

Re-Optimize

Next StepYes

No

Back Annotate RCs, Timing

DIP

17

Topics


DIP

18

What is Partitioning?Partitioning is dividing a design into smaller parts.

DIP

19

Why/How to partition

Why partition?Functionality/readability of RTL codes.Partition for design reuse. (IP)Obtain good synthesis results?

How to partition?In the HDL CodesBy the command in the tool

DIP

20

Partitioning Within HDL Description

module ADR_BLK(..U1:DEC(ADR,CLK,INST)U2:OK(ADR,CLK,AS,OK)end module;

DEC

OK

ADRCLK

ASOK

INST

ADR_BLK

Module statements create hierarchical design blocksInstantiating an entity or module creates a level of hierarchyConcurrent/continuous assignments and process/always @ statements do not create hierarchy

DIP

21

Partitioning Within Design Compiler

groupungroup

Re-partition a design in Design CompilerThe group and ungroup commands manipulate hierarchywithin Design Compiler

DIP

22

Why Partition for Synthesis?Produce the best synthesis result?

Speed up optimization run times.

Simplify the synthesis process.

DIP

23

Rule: No Hierarchy in Combinational Path Bad Example

REGA

Optimization is limited because hierarchical boundariesprevent sharing of common terms.

COMBOLOGIC

ACLK

A

REGC

COMBOLOGIC

C CLK

C

COMBOLOGIC

B

B

Bad Example

DIP

24

Rule :No Hierarchy in Combinational Paths Better Example

C

REGA

COMBO LOGIC A & B & CCLK

A

Better Example

REGCCLK

Related combinational logic is grouped into one block

DIP

25

Rule :No Hierarchy in Combinational Paths Best Example

REGC

COMBO LOGIC A & B & C

CLK

A C

Best Example

REGACLK

Combinational logic is grouped with the destination flip-flop.

Allows for sequential mapping during optimization.

DIP

26

Rule: No Glue Logic Between Blocks - Bad Example

REGA

COMBOLOGIC

ACLK

A

Bad Example

REGC

COMBOLOGIC

CCLK

C

Top Glue Logic

A NAND bridges the two instantiated lower-level blocks.Glue logic cannot be passed to the lower-level blocks where it might be absorbed.

DIP

27

Rule : Separate Designs with Different Goals

SPEED

REGB

CLK

CRITICAL

PATHSpeed

Optimized

AREA

REGA

CLK

NO

CRITICAL

PATHArea

Optimized

Rule : Isolate State Machines

DIP

28

FSMUse FSM

Optimization

ToolREG

BCLK

AUse Standard

Compile

Techniques

REGACLK

RANDOM

LOGIC

DIP

29

Rule 6: Maintain a Reasonable Block Size (250-5000 gates)

BIGGESTSMALL BIG

5,000Gates

250Gates

4,000Gates

DIP

30

Partitioning Rules for Synthesis

No hierarchy in combinational paths.

Register all outputs.

No glue logic between locks.

Separate designs with different goals.

Isolate state machines.

Maintain a reasonable block size.

Separate core logic, pads, clocks and JTAG.

DIP

31

RTL Coding Style

DIP

32

Topics

Basic Coding practicesCoding for portabilityGuild lines for clock and resets.Coding for synthesisPartition for synthesisDesigning with memoriesCode profiling.

DIP

33

Overview

Basic goal => simple and regularUse simple constructs, and simple clocking schemes.Consistent coding style, consistent naming and state machines.Regular partitioning schemeEasy to understand by comments and meaningful names. No hard coded number.

DIP

34

Naming Conventions.Document the naming convention.Lowercase letter for signal names, variable names and port names.Uppercase for constants and user-defined types.Meaningful names for signals

Ex: ram_addr, not raUse short but descriptive names.Clk for clock signals.

Ex: clk1, clk2Active low signals-> end with _nRst for reset. Rst_n for reset with active low.

DIP

35

Naming convention

Use wire [n:0] instead of [0:n];Use the same or similar name for those connected together

Ex: assign a

DIP

36

Coding styles.Include headers in source files.

Filename, authors, description of functions, date, modification history

Use commentsIndentation,Port Ordering

Declare one port per line and follow by a comment Declare port in some order

Inputs:Clocks, reset, enables, control signals, data, and addressOutputs: clocks, resets, enables, control signals, data

DIP

37

Coding StylesPort Maps

Use named association rather than position association..a(in1), .b(in2), .ci(carry_in), .sum(sum), .co(carry_out)

Leave a blank line between the I/O ports to improve the readability.

Use functions as much as possible to save the coding lines.Use Loops and arrays.Use meaningful labels.Do not use hard-coded numeric values.

DIP

38

Coding styles.

Use technology indep. Library.Inferrable arithmetic components such as Adders, multipliers, comparators, incrementers and decrementers.Additional arithmetic components: sin, cos, modulus, divide, square root, barrel shifters, FIFO, FIFO controllers, ECC, CRC, JTAG.Avoid instantiating gates in the design. (hard to read)Isolate instantiated gates in some module.

DIP

39

Guidelines for clocks

Avoid use positive and negative edge clocks.Post problem for timing analysis.Problems for scan.Model accurately the worst case accurately.Separate pos and neg ffs in different modules.

Avoid clock buffers in synthesis.Avoid gated clocks.Avoid internally generated clocks.

DIP

40

Specify explicit vendor macro cell

ifdef IMPLEMENTATION

else

endififdef IMPLEMENTATION

wire t1, t2, t3;XOR3 U1 (t1, in[0], in[1], in[2]);XOR3 U2 (t2, in[3], in[4], in[5]);XOR3 U3 (t3, in[6], in[7], in[8]);XOR3 U4 (perr, t1, t2, t3);

elseassign perr = ^in; //calculate parity on in

endif

DIP

41

RTL ifdef implementation

Define the implementation text macro during the synthesis process and un define it during simulationPreserves clarity and optimizes the RTL for simulation performance.

DIP

42

Coding for SynthesisNo initial in the RTL codeFFs are preferred.Avoid unnecessary latches.

Complete sensitivity list.Avoid combinational Feedback.For sequential blocks use non-blocking statements.For combinational blocks use blocking statements.Coding state machines

Two procedure blocks: one for the sequential and one for the combinational.Keep FSM logic and non-FSM logic in separate modules.Assign a default state.

DIP

43

Example of a finite state machine

Module fsm(clock, rst, x, z);Input clock, rst, x;Output z;Reg [1:0] current_state;Reg [1:0] next_state;Reg z;Parameter [1:0] State_0 =0,State_1 =1,State_2 =2,State_3 = 3;Always @(crrent_state or x) Case (current_state)

State_0: If (x) begin endelse begin end

state_1:if (x) begin endelse begin end

Default:

Alywas @(posedge clock or negedge rst_a)

begin if (!rst_na)

current_state

DIP

44

Partitioning for Synthesis.

Register all outputsLocate related combinational logic in a single machine.Separate modules that have different design goals.Avoid asynchronous logicPartitioning for synthesis runtime.Avoid point-to-point excepts and false paths.

Avoid multi-cycle paths in your designSet_multicycle_path from D_reg to S_reg.Avoid false paths in the design.

Eliminate glue logic at the top level.Top: I//O pad, JTAG, clock generation, Core.

DIP

45

Code Profile

Tracking how often each line of code is executed during a given simulation run.Reveal bottleneck area of your design.Code coverage tools that measure path coverage as well as statement coverage can be useful.

DIP

46

The Importance of Good Coding Style on Synthesis

HDL Source Code implies initial structure.Cannot rely on DC to fix a poorly coded design.(Quality of Results QoR) relies on good coding style (Quality of Source QOS).

Lint QOSQoR

DIP

47

Think Hardware !

Write HDL functional descriptions.Do not write HDL models.

After 20ns and

2 clock cycles

Output = inputs

YES!

NO!

DIP

48

Think Synchronous Hardware !

AsynchronousAddress Decoder

How am I going to synthesize this?

ADDRDECODE

GND

ACK_SET

ADDR_IN

+5

ACK

AS

ACK_CLR

ACK_SET

ACK_CLR

ASGND ACK

+5

ADDRDECODE

ADDR_IN

DIP

49

Think RTL Description of Synchronous Hardware!

COMBO1

COMBO2

COMBO3A B C Z

GIZMO

module GIZMO (A, CLK, Z);always@ (A) begin: COMBO1always@ (posedge CLK)always@ (B) begin : COMBO2always@ (posedge CLK)always@ (C) begin:COMBO3end module;

Verilog RTL Code

A

B CZ

COMB1

COMB2

COMB3

GIZMO

DIP

50

Organize Your Design Workspace

Define a file naming convention.Create a directory structure for storing HDL source, simulation libraries,

synthesis scripts and synthesis dbs.

design

hdl analyzed

vhdl verilog.vhd .v

syn SimInvokeDesignCompilerFrom thisDirectory!

.mra

.sim

.syn

synopsys_dc.setup

DB.db

Netlist.edif.v.vhd

Scripts.con.scr.setup_dc

Log.log.rpt

DW_cache

DIP

51

Define a Naming Convention

Suggestion:Use a syntax-directed editor to HDL files.

/* Module CONVENTION *//* created by scchang Designer *//* version 1.0 08.01.99 */

Module CONVENTION (CLK_MAIN, DATA_INTERRUPT, RAM_INTERRUPT_N);

// Check interrupt to produce a master RAM// interrupt that is registered.

input CLK_MAIN, DATA_INTERRUPT;output RAM_INTERRUPT_N;

Reg [1:0] PROCESSOR_INTERRUPT_NEXT;

Module Name inUPPERCASE

Use UppercaseNames with Noun/Verb Paradigm

_N IndicatesNegative Polarity

Use Commentsfor Revision

Control and toDescribeFunction

Start Clocks with CLK

signal_NEXT IndicatesPre-Registered Value

DIP

52

Recommend:Separate Combo From Sequential Logic

Comb_blockDATA1

DATA2

CLK

QDATA

Combinational Logic

Sequential Logic

DATA_1

DATA_2

CLKSequential Logic

Q

Combinational Logic

DATAComb_block

always @ ( DATA1, DATA2)begin:COMBO

DATA = Comb_block (DATA1,DATA2);end

always @ (posedge CLK)begin: SEQUENTIAL

Q

DIP

53

Know what will be translated

if-else => priority encodercase Synthesis =>general selectorfor loop Synthesis=> duplicationInferring Sequential DevicesVerilog:block & non-blocking assignments

DIP

54

Writing technology indep. HDL

No instantiated gates/FFs (easy porting).Synopsys directives

Infer_muxFull cases & parallel casesAsynchronous set/reset

DIP

55

Dont rely on DC for timing

Especially for mux and xor gates

fast signal

Late signal

DIP

56

if - then - elseif Synthesis

If-then-elseif statements infer priority-encoded cascading MUXs.

always@ (SEL or A or B or C or D)

if (SEL[2] == 1b1)OUTI = A;

else if (SEL[1] == 1b1)OUTI = B;

else if (SEL[0] == 1b1)OUTI = C;

elseOUTI = D;

D

B

A

SEL

C

0

1

SEL[0]='1'

SEL[2]='1'

0

1

SEL[1]='1'0

1OUTI

2

D

C

Sel

B

A OUT

0

1

0

1

0

1

SEL[2]=1

SEL[1]=1

SEL[0]=1

DIP

57

Case Synthesis

00

01

10

11

OUTC

B

A

C

D

SEL2

A

B

C

D

Sel

00

01

10

11

OUTC

2

always@ ( SEL or A or B or C or D)begin

case (SEL)2b00 : OUTC = A;2b01 : OUTC = B;2b10 : OUTC = C;default : OUTC = D;

endcaseend

Imbedded Directives for Verilog case Statement

DIP

58

The full_case directive => all cases listed. The parallel_case directive => mutually exclusive

(therefore dont build priority logic)

always @ (A1 or A2 or A3)begin

case(1b1) //synopsys full_case parallel caseA1 : OUT = 3b001;A2 : OUT = 3b010;A3 : OUT = 3b100;

endcaseend

DIP

59

for loop Synthesis

a(0)b(5)a(1)b(4)a(2)b(3)a(3)b(2)a(4)b(1)a(5)b(0)

example(0)

example(1)

example(2)

example(3)

example(4)

example(5)

integer i;always @ (a or b) begin

for ( i=0; i

DIP

60

Inferring Registers

Left hand side signal assignments become the output of the registers.Right hand side expressions become the combinational logic feeding the input of the register.

A+ D Qalways @ (posedge CLK) begin

S1

DIP

61

Recommend:Use Signals and Non-Blocking Assigns

Non-blocking assignments exclusively within sequential always @ blocks.Blocking assignments as much as possible within combinational always @ blocks.

Design Ware

DIP

62

Libraries of high-level functions, such as adders, multipliers, comparators, FIFOs, and RAMs. Infer high level functions instead of instantiating them .Users can create their own Design Ware parts for design reuse or for licensing to other customers.

AND Gates,OR Gates,Flip-Flops

TechnologyLibrary

Adders,Multipliers,Comparators..

Design WareLibrary

Coding with Design Ware Parts

DIP

63

Through HDL inferencing:

Mult_OUTPUT

Sample of Available Design Ware Parts

DIP

64

To Infer or Instantiate:AdderAdder / Subtractor2-Function ComparatorDecrementorIncremetorIncremetor/DecrementorSubtractorMultiplier6-Fuction Comparator

To Instantiate ONLY:Absolute ValueArithmetic ShifterBarrel ShifterDecoderMultipiler AccumulaterVector AdderUser-Defined Sequential CellsRAMsFIFOsFIFO ControllerUp-Down CounterPCI Bus InterfaceMoudles

DIP

65

Topics


DIP

66

Describing the Design Environment

Area & Timing GoalsEnvironmental AttributesTiming Analysis

DIP

67

Design EnvironmentSimultaneously specify the worst-case and the best-case library

Set_min_library -min_version Used for fixing the hold-time violation.

Set_operating_conditionsDescribes the process, voltage, temperature conditions.Set_operating_conditions min BEST max WORST

Set_wire_loadUsed to provide estimated statistical wire load information.

DIP

68

Area and Timing GoalsArea Goal (set_max_area)To constrain timing paths

Define the clock (create_clock)Define the I/O timing relative to clock (set_input_delay, set_output_delay)

Set_dont_touch_network:used for the clock and reset network.Set_dont_touch find(cell, sub1)Set_dont_touch find(net, gated_rst)

Set_input_delaySpecifiies the input arrival time of a signal related to clkSet_input_delay max 23.0 clock clk {datain}.

Set_output_delayDefine the time it takes for the data to be available fore the clock edge

DIP

69

Constraints

Set_max_delayMaximum delay required in terms for a particular path.Set_max_delay 5 from all_inputs() to all_outputs()Pure combinational blocks

Set_min_delayThe opposite of the set_max_delay

DIP

70

Describing Environmental Attributes

Set_wire_loadSets the wire load model forThe current design

Set_driving_cell

Set_fanout_load

Set_load load_of()

Set_loadSet_drive

Default drive is infinite

DIP

71

Describing Design ConstraintsSet_max_capacitance set_max_transition &

set_max_fanout on current design

Set_wire_loadSets the wire load model forThe current design

Clk

Create_clock &

Set_clock_skew

Set_input_delay

Set_output_delay on outputs

DIP

72

Drive and Load

Set_driving_cell cell INV all_inputs()Set_load 5 find( port OUT1).Set_load load_of (chip/AND2/A) find (port OUT1).Set_load load_of(chip/INV/A)*3 find (port OUT1).

DIP

73

Modeling Wire Loads

Estimate capacitance/resistance of nets.

Statistically average length of a net for # of fanouts.

10x10

10x20

5x5

DIP

74

The Wire Load Model

Wire_load (10x10) {resistance : 5.0capacitance : 1.1area : 0.05slope : 0.5fanout_length (1, 2.6)fanout_length (2, 2.9)fanout_length (3, 3.2)fanout_length (4, 3.9)fanout_length (5, 4.1)fanout_length (6. 4.7)}

Fanout=8

1 2 3 4 5 6 7 8

5.7

4.7

4.1

3.2

2.6Slopinterpolation

Length = 4.7+((8-6)x 0.5) = 5.7 lengthCapacitance =5.7(length) x1.1 (cap coeff.)=6.27 load units

DIP

75

Summary of Design Environment

Timing and Area Goal (set_max_area)Environment Attributes (set_load)Design Rule (set_max_fanout)Reports (report_timing)

DIP

76

How Do You Know if Your Design Met Its Goals?

A & E RTL Code

Apply Constraints

Recode RTL

Constraints Met? Identify Problem

Optimize

RTL Block Synthesis Flowno

Next Stepyes

DIP

77

Static Timing Analysis (PT)

PT is a stand alone tool.Purposes

Checks the design for required constraint. (hold/setup time)Comprehensive analysis for the design. (critical paths analysis).

Static vs Dynamic timing analysisCircuit vs component delays

DIP

78

Timing verification subtopics

They are all

interrelated...

Its a mess!

Clocking Overall clocking schemeLatches and Flip-flopsTiming constraints for proper operationClock generation/distributions, clock skew.

Delay modeling (component delay)of transistors, gates, interconnectup/down/ min/max, variability vs process

Timing verification: (circuit delay)Static timing analysis (transition-mode vs floating mode).Dealing with false paths, multi-cycle paths.Pre-layout clock specification.Post-layout (back annotation).Clock-gating check, bottleneck analysis.

DIP

79

Calculate Cell delay?

Cell delays are calculated using one of four different cell delay

Linear Delay ModelTwo Piece Linear Delay ModelPiecewise Linear Delay ModelNon-Linear Delay Model

The cell delay model is chosen by the Foundry .

DIP

80

Simple Schematic Converted into a Timing Graph

Each arrow represents a net or cell delay (timing arc)

DIP

81

Chip Synthesis SummaryChip Spec

Partition Chip

Insert Test/IO pins

Floorplan

Place & Route

Final Verification

Structure SynthesisRTL Synthesis

Integrate Blocks

Code each block=>simulate=>optimize

RTL codes

script, constraints

Load/drive problem =>optimize

Back annotate=>re-optimize

DIP

82

Architectural

Gate

Logic

High Level Synthesis

StructureFlattenHDL Description

Optimized Gate-Level Netlist

Gate-Level Netlist

Constraint-Based Optimization

Map

DIP

83

Architectural Level Optimization

Resource Sharing

Design Ware Implementation Selection

Sharing Common Sub-Expressions

Inferring Adders with Carry-In

Re-Ordering Operators

DIP

84

Resource Sharing : An Example

MUX

if(SELECT) thenSUM

DIP

85

Sharing CSEs Limitations

1.Sharable terms must be in the same order :

2.Sharable terms must be in the same position (or use parentheses to guide):

SUM1

DIP

86

DesignWare Implementation Selection

Design Compiler selects the smallestimplementation that satisfies timing goals.

Carry LookAheadfastest

+

RippleCarry

SyntheticModule

smallest

DIP

87

Operator Re-Ordering

Order Arithmetic operators for the fastestdesigns.

Example: Z

DIP

88

Optimization

Resource Sel.Resource SharingArchitectural-Level

Logic-Level

Gate-Level

StructureFlatten

MappingSequential Mapping

DIP

89

What is Flattening?

Two-level, sum of products (SOP) implementation.Does not collapse the hierarchy.Useful for speed optimization, but can be very area-intensive.

ABC

DSTR

DIP

90

What is Structuring?

Multi-level implementation.Useful for speed optimization as well as area optimization.

A

BC

D

STR

DIP

91

What is Mapping?

1.The process of generating a gate-level implementation of a design that meets timing and area goals.

2.Mapping rearranges components, combining and re-combining logic into different components, keeping those which move the circuit toward your goals.

A

BT T

AB

AB

CR

ABC

R

ASLOW

BS

AB

SLOWS

AB F AB F

DIP

92

Sequential Mapping

Mapping to sequential cells from tech. library.Absorb the logic by using a more complex sequential cell.Utilizes the attributes within HDL to map to user-preferred sequential cells.

AB A

B

JK

DIP

93

How Does the Design Compiler Know When to Stop?

Answer: Constraint Driven (DC 98)DelayDesign rule fixingArea

Total Negative Slack Vs Worst slack

Realistic constraints. 10% over tighter than required.

area

delay

DIP

94

Are All Constraints Equal ?

area

Speed

No! Constraints, in order of priority, are :

1. set_dont_touch , Design Rule Constraints

2. Maximum Delay (Setup)

3. Minimum Delay (hold)

4. Maximum Area

5. Minimum Porosity (% feedthrough)

( The gray items are Users Goals )

DIP

95

Chip Synthesis SummaryChip Spec

Partition Chip

Insert Test/IO pins

FloorplanPlace & Route

Final Verification

Structure SynthesisRTL Synthesis

Integrate Blocks

Code each block=>simulate=>optimize

Load/drive problem =>optimize

Back annotate=>re-optimize

DIP

96

Compile Strategies

Top-down hierarchical compile method (can do more than 100k )Time-budget compile method.Compile-characterize-wire-script-recompile method.

DIP

97

Top-Down Hierarchical

Read in entire design. Resolve multiple references. Apply constraints and attributes,based on design specification,to top level. Compile.

DIP

98

What Happens When You CompileDesign in the hierarchy are mapped to gates.

DESIGNA

Y=A+B

DESIGNB

Y=A+B

DESIGNC

Y=A+B

Top

U3

U1 U2

DIP

99

First Phase of Compile (Map to gates)Top

DESIGNA DESIGNB

Y=A+B

DESIGNC

Y=A+B

U3

U1 U2 TopDESIGNA DESIGNB

DESIGNC

Y=A+B

U3

U1 U2

TopDESIGNA DESIGNB

DESIGNC

U3

U1 U2

Hierarchy is Preserved

DIP

100

Second Phase of CompileThe second phase of compile characterizes surroundings.

TopDESIGNA DESIGNB

DESIGNC

U3

U1 U2

TopDESIGNA DESIGNB

DESIGNC

U3

U1 U2

DIP

101

Top-Down Hierarchical Compile

Advantages:Simple. (Easy push button)Better result

Disadvantages:Long compile time.Incremental changes requires to completely re-synthesis.

If there are multiple clocks or generated clocks. => do not perform well.

DIP

102

Time Budgeting (Budgeting tools)

Define an accurate timing specification for each module.Create a script file containing the attributes and constraints to implement this spec.Compile each module with its corresponding script file.

15ns

5ns 7ns 3ns

MODULEA

MODULEB

MODULEC

set_input_delay 5 -clock \CLK find (port, INPUTB)

set_input_delay 12 -clock \CLK find (port, INPUTC)

read -f Verilog A.vinclude A.scrcompile

read -f Verilog A.vinclude A.scrcompile...

DIP

103

Proc / Cons of Time Budgeting

AdvantagesEasier to manage the design Incremental changes do NOT need re-synthesisGood quality results

DisadvantagesTedious to update and maintain multiple scripts.Have to know the system spec.

DIP

104

Compile-Characterize-write-script-recompile(Before We Start :Two definitions that we need:

Characterize examines an instances surroundings and applies the appropriate timing information to the design being characterized.

characterize constraints timing find(cell, U1)

write_script saves the information from a characterize into an ASCII file using dc_shell command format.

current_design design_name

write_script > filename.scr

.

DIP

105

The characterize Command

A2

Top

input Delay Timesand Drive on inputs

Output Load andDelay constraints

characterize calculates and applies the attributes and constraints that describe an instances design environment.

characterize constraints timing find(cell, Aw)

DIP

106

Use characterize Only When Gates Exist

Automatically Saving the Results of Characterize

DIP

107

Write_script creates an script file of all the constraints and attributes that have been defined so far for the current design.

/***************************************************************************************************************//* Set the current_design */current_ design = MICROWAVEcreate_clock period 45 find (port,CLK)set_input_delay_10 max clock CLK\

find(port,START_COOK)set_input_delay 5\

-min clock CLK find (port,START_CLOCK)set_input_delay_10 max clock CLK\

find(port,SET_TIME)set_output_delay 4 clock CLK find(port,SEC_LSB[0])set_output_delay 4 clock CLK find(port,SEC_LSB[1]).set_drive 2 find (port,INBUS[0]);set_load 35 find (port,SEC_LSB[0]);

DIP

108

Characterize & write_script Work together

Instances

A BU1 U2Top

Reference Designs

current_design TOPcharacterize constraint timing find(cell {U1 U2})current_design Awrite_script > A.scrcurrent_design Bwrite_script >B.scr

DIP

109

Characterize NOT develop time budgets

Example:

CLK Q2ns

14nsA

U1

12nsB

U2

SETUP1ns

12nsC

U3

IN

CLK

TOP

S T OUT

CLK= 50 MHz (20 ns)

run.scr B.scrcurrent_design TOPcharacterize { U2}current_design Bwrite_script > B.scr..

create_clock p n CLK w{0 10}set_input_delay c CLK 16 find(port S)set_input_delay c CLK 17 find(port T)

Bottom-Up Hierarchical Compile

DIP

110

Compile sub-blocksindependentlyRead in the entire compiled design and apply top-level constraints.Characterize one sub_block.Use write_script to save the information from characterize.Clear memory and re-compilethe sub-block using saved script.Read in the entire compiled design without the old sub-block; use recompiled sub-block. Pick another sub-block and repeat step 3-7 until sub-blocks are recompiled using their actual environment.

MICROWAVE

MICRO_FSM TIMER SEGS_REG

COUNTER4 DECODER CONVSEGS

read microwave.db, timer.db include defaults.scrcharacterize -cons -time {TIMER_BLK}current_design TIMERwrite_script > timer.wsrcremove_design -designsanalyze -lib AN -format verilog timer.velaborate -lib AN timerinclude timer.wscrcompileread microwave.db, timer.db include defaults.scrcharacterize -cons -tim micro_fsm_blkcurrent_design MICRO_FSMwrite_script > micro_fsm.wscr...

DIP

111

CCWSR scriptAll_instances = {C, D, top}Characterize constraint all_instancesForeach (module, all modules) {

Current_design moduleChar_module_script = module + .wscrWrite_script > char_module_scriptForeach(module, all modules) {

remove_design allmodule_source = module +.vread format verilog SRC+/+module_source

Current_design modulelinkuniquifychar_module_script = module+ .wscrinclude char_module_scriptcompile

}

DIP

112

CCWSR

AdvantagesLess memory intensiveGood quality Produce individual scripts which may be modified by the user

DisadvantagesScripts are not easily readableMay not convergeA change at the lower level block generally requires compete re-synthesis of the entire design.

DIP

113

Topics


DIP

114

Links to Layout and post Layout Optimization

DIP

115

Links to Layout

A virtual wall existed between front-end and backendDesigns need the LTL interface to conduct optimization.After synthesis,

Q1: how close is the wire load model to the actual data from layout

LTL: exchange relevant data: timing constraints and/or placement information.

Generating netlist for layout

DIP

116

UniquificationThe clocks referenced multiple times. Exist physically at separate locationsProblem for clock tree generation.

Changing the namesDefine_name_rules BORG allowed A-Za-z0-9_-first_restricted_ last_restricted _-maxlength 30-map {{\*cell\*, mycell}, {-return}, }myreturn}}}

Remove unconnected portsAll pin names are visible:

Verilogout_show_unconnected_pins = true

DIP

117

Generating net list for layout

No assign statementSet_fix_multiple_port_nets all buffer_constraints

Un-intentional gating of clocks or resetsReport_transitive_fanout from resetReport_transitive_fanout clock_tree

Check for unresolved references.

DIP

118

Post Layout ResultsHelp!

My design was synthesized,and met its timing constraints.

But after place & torte,it did not meet timing!

How close arethe estimated Wire loads comparedto the actual delay after layout

Traditional Synthesis to Layout Flow

DIP

119

MetConstraints?

Layout

MetConstraints?

Manual Edits

yes

noyes

Netlist

no

DONE

HDL Description Constraints

Re-doSynthesis

Synthesis

Wire load model not accurate

Path timing information not available

DIP

120

Links-to-Layout Methodology

Path DelayTiming Constraint

Design CompileFloorplan Manager Physical Tools

Cell LocationsCell ObstructionsAccurate Timing Information

DIP

121

Links-to-Layout Methodology Flow

PerformDetailed

Implementation

Gain TimingClosure

Develop Physical

Information

DIP

122

Physical Information Development

HDLConstraint

QuickSynthesis

Early Phy. Design

Back-AnnotateTo Floor plan

DesignBudgeting

Create CustomWire load Model

Constraint

Detail Implementation

DIP

123

HDLConstraint

CustomWire Load

Synthesis

Phy. Design

Timing Verification

Net list+SDF constraint

DIP

124

Timing Closure

Detailed Phy.Info.

Net list

Re-Optimization

Timing Verification

ECO (place & route) Do notMeet Timing

DIP

125

Create Forward Annotation InformationDesignCompiler

Netlist

Place &Route Tool

SDF, Constraint File

Help Increase Predictability Route Critical Paths First:

Forward annotate SDF, or a constraint file , to layout tool.Constraint file contains a list of net priorities.Effectiveness depends on capabilities of layout tool.

Generate Physical Information (Back Annotation)

DIP

126

DesignCompiler

RCs

NetlistFloorplanner

RCcNetlist

Place &Route Tool

Back annotate RC parasitic from Place & Route or Floorplanner. (SDF, PDEF)Replace wireload estimates.If the net changes, the back-annotated data is invalidated. Design Compiler will resort to the wireload model.

DIP

127

Routing and Extraction FlowSynthesis and Optimization

Floor Planning, Placement and

Clock Tree Insertion

Global Routing

Extract Estimated Delays

Timing ok

Maj

or T

imin

g V

iola

tion

s

Min

or T

imin

g vi

olat

ion

Detailed Routing

Extract Real Delays

Timing ok

DIP

128

Layout (Floor planning)

Floor PlanningThe most critical step within the entire layout.Consists of placement of cells and macros(RAMS and ROMs) Objective: reduce net RC delays and routing capacitance.Hierarchical placement and routing of the design

Place and Route small blocks first and then fixed as a macro

Layout (Timing Driven Placement)

DIP

129

Timing driven layout (TDL) Forward annotating the timing information of the design generated by DC to the layout tool.The layout tool gives priority to timing while placing the cells and tries not to violate the path constraint.

Write_constraint format -cover design from -to < to list> -through < through list> -output (TIMINGCHECK

(PATHCONSTRAINT INPUT1 U751/A3 U751/ZN U754/I1 U754/ZN REG0/D (1.523: 1.523: 1.523))

(PATHCONSTRANIT INPUT2 U )Time consuming for generating the constraint file.Let the layout tool generate the timing constraint based on the boundary conditions.

DIP

130

Layout (TDL)

Back annotation of floorplan informationFor post-layout optimization, it is necessary for DC to know the physical location of each sub-block. (PDEF)The PDEF file contains the cluster information and location of cells in the layout.Physical hierarchy may be different from the logical hierarchy.Read_clusters design Write_clusters design -output

DIP

131

Layout (Clock tree Insertion)

Clock tree synthesisIt is essential to control the clock latency and the skew.Some design can take advantage of skews for optimization.CTS is performed immediately after the placement of the class and before routing these cells.Generally, designers are asked for the number of levels along with the types of buffers used.Be careful of gated clocks.

Routing& extraction

DIP

132

1. Global Routing 2. Detail routingWhat to extract

1. Detailed parasitic in DSPF or SPEF format.Detailed standard parasitic format contains RC information of each segment (multiple Rs and Cs)

2. Reduced parasitic in RSPF or SPEF formatReduced standard parasitic format) represents RC delays in terms of a pi model (2 Cs and 1R)

NET and cell delays in SDF formatDC does not know the parasitic capacitances associated with each net

Net delay in SDF format + lumped parasitic capacitances.DC makes use of the net loading information during the post-layout optimization.

RecommendedNet RC delays in SDF. Capacitive net loading in set_load formatParasitic information for clock and other critical nets in DFPF or RSPF

DIP

133

Re-optimization flow

Read_sdf postlayout.sdfRead_clusters postlayout.pdefInclude set_load.fileCreate_wire_load hierarchyReoptimize_design

DIP

134

Utilizing Physical Hierarchy During Compile

The reoptimize_design command:Similar to compile-incremental except it recognizes physical clusters and wont allow changes to nets/cells that cross a physical boundary.Options: -tolerance,-in_place(IPO) and post_layout_opto(PLO)tolerance:indicates willingness of design to change. Low,med,& highin_place:Resizes cells that have the same physical footprint in order to meet timing constraints without affecting placement of design. Does not change the structure of the designPost_layout_opto:More flexible incremental optimization process.

Performs IPO as well as allows critical path resynthesis of paths that fall within the physical hierarchy boundaries.

Note: reoptimize design requires a DC-Expert and a Floorplan-Management License.

DIP

135

In place OptimizationIPO is an method to fine tune a design. The concept is to keep the structure of the design intact while modifying the failing parts of the design.Minimum impact on the layoutResize cells or insert, delete existing cells.technology library attribute

In_place_swap_mode: match_footprintTwo cells with the same functionality and same size.

Other variablesCompile_ignore_footprint_during_inplace_optCompile_ok_to_buffer_during_inplace_optCompile_ignore_area_during_inplace_optCompile_disable_area_opt_during_inplace_opt

DIP

136

IPO

Compile in_placeUse the library wire-load models

Reoptimize_design in_placeUse custom wire-load models.

DIP

137

IPO vs. PLOInitial Design

IVA NR2ANA2A

IVB

After IPO

After PLO

NR2BNA2A

IVBNA2A

Sizing Transformation

NR2A

IVA NR2R Net fanoutschanged

DIP

138

Pre-Compile Checklist

Checklist:

Good Synthesis Realistic Constraints & Attributes

Good Synthesizable HDL Code Multicycle and False Paths Identified

Good Synthesis Libraries Wireloads Reflect Physical Placement

DIP

139

You Are HereSelect Block

SpecifyConstraints

Report_timing,Check_timing

Optimize

Modify CompileOptions

ModifyConstraints

Re-partitoinBlock(s)

RewriteHDL Description

BalanceRegisters

Timing Analysis:Identify Problem

YOUAREHERE

GoodResults?

Yes

No

Done!

DIP

140

Identify Problems Using Timing Analysis

Spot the whales in the timing report: why are they there?Point Incr Path--------------------------------------------------------------------------------------clock (input port clock) (rise edge) 0.00 0.00input external delay 22.42 22.42addr31 (in) 0.00 22.42proc/dcl/int_add[8] (dcl) 0.00 22.42proc/dcl/U100/Q (INVF) 0.48 22.90proc/dcl/U233/Q (NBF) 0.85 23.75proc/dcl/U156/Q (BF) 0.46 24.21proc/dcl/U210/Q (BF) 0.43 24.64proc/dcl/U112/Q (NBF) 0.81 25.45proc/ctl/ctl_rs_N (ctl) 0.00 25.45proc/ctl/U160/Q (AND2B) 10.77 36.22proc/int_cs (proc) 0.00 36.22int/U58/Q (NBF) 1.25 37.47int/U12/Q (INVB) 1.79 39.26int/U61/Q (INVB) 1.82 41.08

LATE arrival for 30 ns period!

5 buffers back to back?

11 ns delay for an AND gate is not good.

Three hierarchical partitions.

DIP

141

Topics


DIP

142

Standard Delay Format( SDF)

Outline

DIP

143

Introduction How to generate the SDF ? From Design Analyzer From Design Compiler By get_sdf script From Cadence AmbitSDF formatSDFFor GL SimulationTiming CompareHow to Run GL SimulationSDF to CadenceExamples

Introduction

DIP

144

SDF contains timing information of all cells Provide timing information for gate-level simulationThe basic timing data comprises the following : IOPATH delay INTERCONNECT delay SETUP timing check HOLD timing check

How to generate the SDF ?

DIP

145

From Design Analyzer by command windows mode by paragraph interface mode From Design Compiler By get_sdf scriptFrom Cadence Ambit

DIP

146

How to generate the SDF ?- by command windows mode(1)

DIP

147

How to generate the SDF ?- by command windows mode(2)

Write out the timing information> write_timing format sdf output > write_sdf output

Write out the constraints information> write_constraints format sdf max_paths_timing \

-max_paths 1 output

DIP

148

How to generate the SDF ?- by paragraph mode (1)

Write out the timing information

DIP

149

How to generate the SDF ?- by paragraph mode (2)

Write out the constraints information

DIP

150

SDF format- Write out the timing information(1)

(DELAYFILE(SDFVERSION "OVI 2.1")(DESIGN "adder")(DATE "Fri May 18 22:43:36 2001")(VENDOR "cb35os142")(PROGRAM "Synopsys Design Compiler cmos")(VERSION "1999.10-5")(DIVIDER /)(VOLTAGE 3.30:3.30:3.30)(PROCESS "NCCOM")(TEMPERATURE 25.00:25.00:25.00)(TIMESCALE 1ns)(CELL

(CELLTYPE "adder")(INSTANCE)(DELAY

(ABSOLUTE(INTERCONNECT var3 sum2_reg\[1\]/SD (0.000:0.000:0.000))(INTERCONNECT var4 sum2_reg\[1\]/SC (0.000:0.000:0.000))(INTERCONNECT U13/Z sum2_reg\[1\]/CP (0.000:0.000:0.000))(INTERCONNECT var1 sum1_reg\[1\]/SD (0.000:0.000:0.000))

MinTyp

Max

DIP

151


(INTERCONNECT var3 sum2_reg\[1\]/SD (0.000:0.000:0.000))(INTERCONNECT var4 sum2_reg\[1\]/SC (0.000:0.000:0.000))(INTERCONNECT U13/Z sum2_reg\[1\]/CP (0.000:0.000:0.000))

DIP

152


(CELL(CELLTYPE "xr02d1")(INSTANCE U20)(DELAY

(ABSOLUTE(IOPATH A1 Z (0.212:0.353:0.353) (0.207:0.320:0.320))(IOPATH A2 Z (0.239:0.345:0.345) (0.243:0.344:0.344)))

))

DIP

153


(CELL(CELLTYPE "dfnrq1")(INSTANCE sum2_reg\[0\])(DELAY

(ABSOLUTE(IOPATH (posedge CP) Q (0.522:0.522:0.522) (0.568:0.568:0.568)))

)

(TIMINGCHECK(WIDTH (posedge CP) (0.437:0.437:0.437))(WIDTH (negedge CP) (0.446:0.446:0.446))(PERIOD CP (0.883:0.883:0.883))(SETUP (posedge D) (posedge CP) (0.187:0.188:0.188))(SETUP (negedge D) (posedge CP) (0.171:0.174:0.174))(HOLD (posedge D) (posedge CP) (0.004:0.004:0.004))(HOLD (negedge D) (posedge CP) (0.004:0.004:0.004))

))

DIP

154

SDF format- Write out the constraint information

(DELAYFILE(SDFVERSION "OVI 1.0")(DESIGN "adder")(DATE "Fri May 18 22:44:24 2001")(VENDOR "cb35os142")(PROGRAM "Synopsys Design Compiler cmos")(VERSION "1999.10-5")(DIVIDER /)(VOLTAGE 3.30:3.30:3.30)(PROCESS)(TEMPERATURE 25.00:25.00:25.00)(TIMESCALE 1ns)(PATHCONSTRAINT path (time)))

SDF--For GL Simulation

DIP

155

Example: Two stage pipeline

a

b

c

d

First Seconde

g

f

DIP

156

Timing Compare(1)~ Without SDF

DIP

157

Timing Compare(2)~ With SDF

DIP

158

How to Run GL SimulationWith SDF?

In your test file :initialbegin$sdf_annotate(your_sdf_file",top_instance);end

:top_instance is the top level module instance name of your test file

DIP

159

SDF to CadanceSDF constraints in order for Qplace to work most effectivelyIf for large design(>10k components) full SDF constraint is not recommendedYour GL file should sent to

Verilog InThen cadance can read SDF file

Floorplan-Qplace or Placement RC information gate

sizing(PBS) Redo until timing is satisfactory

DIP

160

Timming Driven placement FlowGate level file

Verilog In

Read SDF

floorplan

Placement or Qplace

rounting

layout

Timing ok

Timiongfail

Write SDF

Timing ok

DIP

161

How to import SDFSDF file name

The name of

Subblock

Format:Verilog

DIP

162

Standard Delay Format

Generate SDF from Layout Tool (CDN)

DIP

163

TOPIC

What command & files (SDF) to back annotate layout-generated information to the design present in DC ?

How to generate SDF format ?

Commands & files

DIP

164

Use the command to read SDF format in DC .

read_timing f sdf < RC file name in SDF format >

or

read_sdf < RC file name in SDF format >

How to generate SDF ?

DIP

165

CTLF

Preview RC extractor RSPF CDC SDF

initial filepaTable

RSPF : Reduced Standard Parasitic FormatCDC : Central Delay CalculatorSDF : Standard Delay FormatCTLF : Compiled Timing Library Format

Input file : CTLF , RSPF(from Preview) , initial file(control file)Output file : SDF

DIP

166

Preview Parasitic Extraction

Parasitic extraction includes two steps-- wire length estimation/calculation-- calculate the parasitic capacitance/

resistance of a net according to thetechnology information

DIP

167

Preview Wire Length Estimation

Wire topology mode-- determine the method used to estimate

wire length-- two mode

* fast mode* best mode

DIP

168


Fast design for a placed design Best design for a placed design

L1

Does not look up thepaTable ; use the netlength

Multiple the half Perimeterof L1 by the factor from thepaTable

DIP

169


paTable is a text file

; Table for estimating length for net with placed status.bBoxTable

(2 0.82893 0.96724 1.0248

.)

factornumber ofpins in a net

DIP

170


Example for fast estimation

L1

(paTable(

2 0.10843 0.18954 0.2295

The fast estimated wire length = 0.5*1000*0.2259

L1=1000um

DIP

171


CTLF libraryCTLF contains timing information associated

with any cell in a technology library (cell library).

used by Preview parasitic extractor and centraldelay calculator.

DIP

172

Preview Parasitic Calculation

CTLF Wire length

calculator

Total net capacitance( for next step )

DIP

173

Write Reduced SPF (RSPF)

Logical circuit

U 8U 7

n30

Extract RSPF

R1 C1 C2

R2U7

C3

R3

E3

U8

DIP

174

RSPF Example.SUBCKT BEH_AOI OUT IN

*|GROUND_NET VSS

*Net Section

*|NET |d 0.000209PF

..*|NET |n30 0.000072PF

*|DRIVER |U7:ZN |U7 ZN

*|S (|U7:ZN:1 0.0 0.0)

R1 |U7:ZN VSS 0.000000

R2 |U7:ZN |U7:ZN:1 3.566271

C1 |U7:ZN VSS 0.000004PF

C2 |U7:ZN:1 VSS 0.000068PF

*

*|LOAD |U8:A2 |U8 A2

*|S (|U8:A2:1 0.0 0.0)

E1 |U8:A2:1 VSS |U7:ZN VSS 1.0000

R3 |U8:A2:1 |U8:A2 1.0000

C3 |U8:A2 VSS 0.000283PF

DIP

175

Initial File for CDCLIBRARY_NAME "SDF_EX"

TIMING_LIBRARY "cb35os142.ctlf"

CELL_NAME "BEH_AOI"

LIBRARY_PATH "/vlsi-user/vlsi-data/cell_libraries/CIC_CBDK35_V3/Cadence/PreSE/CTLF"

VIEW_NAME "layout"

LEVEL 1

MODE "ALL"

REPORT_VERBOSE

REPORT_INTRINSIC_IO

PARASITIC_FILE "~/cadence/SDF_EX/BEH_AOI/BEH_AOI.rspf"

DEFAULT_RISETIME 2.5

DEFAULT_FALLTIME 2.5

WARN_RF_TIME 3.0

ERROR_RF_TIME 5.0

WARN_OUT_LOAD 10.0

ERROR_OUT_LOAD 20.0

TEMPERATURE (0 25 85)

PROC_VAR (1 1 1)

VOLTAGE (5.0 5.0 5.0)

DIP

176

Central Delay Calculator (CDC)

Used for circuit delay calculationTo predict and verify the performanceof ICs.The time to use CDC extends from front-end logic design to back-end layout tools like SE.

DIP

177

Standard Delay Format file(SDF)(ABSOLUTE

(INTERCONNECT

\|U7/ZN

\|U8/A2

(0.000093:0.000093:0.000093) (0.000050:0.000050:0.000050)

)

(INTERCONNECT

\|U9/ZN

\|U8/A1

(0.000029:0.000029:0.000029) (0.000015:0.000015:0.000015)

) ) ) ) )

(DELAYFILE

(SDFVERSION "3.0")

(DESIGN "BEH_AOI")

(DATE "Thu May 10 20:38:47 2001 ")

(VENDOR "Cadence")

(PROGRAM "Preview Floorplanner")

(VERSION "4.4.1")

(DIVIDER /)

(TIMESCALE 1ns)

(CELL

(CELLTYPE "BEH_AOI")

(INSTANCE )

(DELAY

DIP

178

Topics


DIP

179

Design Re-Use Using Design Ware

Design Ware LibrariesDesignWare ComponentsInferring Complex Cells.Creating your own DesignWare Library

DIP

180

-12


DIP

181

-9

ASIC Design MethodologyCoding StylesConstraining and Optimizing DesignsLinks to Layout & Post Layout OptimizationDesign Re-Use using Design Ware

DIP

182

-6

ASIC Design Methodology (Mini)Coding StylesConstraining and Optimizing Designs (Mini)Links to Layout & Post Layout Optimization (Mini)Design Re-Use using Design Ware

DIP

183

DC shell script writing.a generic synthesis script for sub-modulesSynthesis script for the top level moduleScript for pre-layout SDF generationScript for incremental synthesis of the designScript to fix the hold time violationsScript for the worst-case post-layout SDF generation

Synthesis MethodologyObjectivesText BooksTopicsTopicsWhat does Synthesis do?Synthesis problems are NPSynthesis problems in SOCBegin With a Chip SpecificationPartition ChipRTL SynthesisBuild Chip Hierarchy by Integrating BlocksInsert Test StructuresInsert I/O PadsFloorplan ChipPlace & Route ChipTopicsWhat is Partitioning?Why/How to partitionPartitioning Within HDL DescriptionPartitioning Within Design CompilerWhy Partition for Synthesis?Rule: No Hierarchy in Combinational Path Bad ExampleRule :No Hierarchy in Combinational Paths Better ExampleRule :No Hierarchy in Combinational Paths Best ExampleRule: No Glue Logic Between Blocks - Bad ExampleRule : Separate Designs with Different GoalsRule : Isolate State MachinesRule 6: Maintain a Reasonable Block Size (250-5000 gates)Partitioning Rules for SynthesisRTL Coding StyleTopicsOverviewNaming Conventions.Naming conventionCoding styles.Coding StylesCoding styles.Guidelines for clocksSpecify explicit vendor macro cellRTL ifdef implementationCoding for SynthesisExample of a finite state machinePartitioning for Synthesis.Code ProfileThe Importance of Good Coding Style on SynthesisThink Hardware !Think Synchronous Hardware !Think RTL Description of Synchronous Hardware!Organize Your Design WorkspaceDefine a Naming ConventionRecommend:Separate Combo From Sequential LogicKnow what will be translatedWriting technology indep. HDLDont rely on DC for timingif - then - elseif SynthesisCase SynthesisImbedded Directives for Verilog case Statementfor loop SynthesisInferring RegistersRecommend:Use Signals and Non-Blocking AssignsDesign WareCoding with Design Ware PartsSample of Available Design Ware PartsTopicsDescribing the Design EnvironmentDesign EnvironmentArea and Timing GoalsConstraintsDescribing Environmental AttributesDescribing Design ConstraintsDrive and LoadModeling Wire LoadsThe Wire Load ModelSummary of Design EnvironmentHow Do You Know if Your Design Met Its Goals?Static Timing Analysis (PT)Timing verification subtopicsCalculate Cell delay?Simple Schematic Converted into a Timing GraphChip Synthesis SummaryConstraint-Based OptimizationArchitectural Level OptimizationResource Sharing : An ExampleSharing CSEs LimitationsDesignWare Implementation SelectionOperator Re-OrderingOptimizationWhat is Flattening?What is Structuring?What is Mapping?Sequential MappingHow Does the Design Compiler Know When to Stop?Are All Constraints Equal ?Chip Synthesis SummaryCompile StrategiesTop-Down HierarchicalWhat Happens When You CompileFirst Phase of Compile (Map to gates)Second Phase of CompileTop-Down Hierarchical CompileTime Budgeting (Budgeting tools)Proc / Cons of Time BudgetingCompile-Characterize-write-script-recompileThe characterize CommandUse characterize Only When Gates ExistAutomatically Saving the Results of CharacterizeCharacterize & write_script Work togetherCharacterize NOT develop time budgetsBottom-Up Hierarchical CompileCCWSR scriptCCWSRTopicsLinks to Layout and post Layout OptimizationLinks to LayoutGenerating netlist for layoutGenerating net list for layoutPost Layout ResultsTraditional Synthesis to Layout FlowLinks-to-Layout MethodologyLinks-to-Layout Methodology FlowPhysical Information DevelopmentDetail ImplementationTiming ClosureCreate Forward Annotation InformationGenerate Physical Information (Back Annotation)Routing and Extraction FlowLayout (Floor planning)Layout (Timing Driven Placement)Layout (TDL)Layout (Clock tree Insertion)Routing& extractionRe-optimization flowUtilizing Physical Hierarchy During CompileIn place OptimizationIPOIPO vs. PLOPre-Compile ChecklistYou Are HereIdentify Problems Using Timing AnalysisTopicsSDF--For GL SimulationTiming Compare(1)~ Without SDFTiming Compare(2)~ With SDFHow to Run GL SimulationWith SDF?SDF to CadanceTimming Driven placement FlowHow to import SDFStandard Delay FormatTOPICCommands & filesHow to generate SDF ?Preview Parasitic ExtractionPreview Wire Length EstimationPreview Wire Length EstimationPreview Wire Length EstimationPreview Wire Length EstimationPreview Wire Length EstimationPreview Parasitic CalculationWrite Reduced SPF (RSPF)RSPF ExampleInitial File for CDCCentral Delay Calculator (CDC)Standard Delay Format file(SDF)TopicsDesign Re-Use Using Design Ware-12-9-6

Synthesis Methodology - mspic.ee.nchu.edu.twmspic.ee.nchu.edu.tw/dip_ppt/TOPIC2_SYNTHESIS/5.pdf ·...

Documents

Transcript of Synthesis Methodology - mspic.ee.nchu.edu.twmspic.ee.nchu.edu.tw/dip_ppt/TOPIC2_SYNTHESIS/5.pdf ·...