Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1 Intel IXP1200 Network Processor q Lab 12,...
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Transcript of Shivkumar Kalyanaraman Rensselaer Polytechnic Institute 1 Intel IXP1200 Network Processor q Lab 12,...
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Intel IXP1200 Network Processor
Lab 12, Introduction to the Intel IXA
Jonathan Gunner, Sruti Gorappa, Kerry Wood Shiv Kalyanaraman Yong Xia (TA) [email protected] http://www.ecse.rpi.edu/Homepages/shivkuma
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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First: What’s a Network Processor Router vendors have built speed into their devices by
pushing functionality down into hardware (ASICs). ASIC: Application Specific Integrated Circuits
They’re fast, but they’re custom-made for each application and expensive to build.
Time to market for new implementations is extremely long, since algorithms must be implemented at the transistor/gate level.
Network processors look to avoid these pitfalls by introducing specialized, software controlled devices
that can be customized quickly. But they also process packets at near-wire speeds!
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Intel Internet Exchange Architecture Microengine technology — a subsystem of
programmable, multi-threaded RISC microengines that enable high-performance packet processing in the data plane through Intel® Hyper Task Chaining. This multi-processing technology features software pipelining and low-latency sequence management hardware.
The Intel IXA Portability Framework — an easy-to-use modular programming framework providing the advantages of software investment protection and faster time-to-market through code portability and reuse between network processor-based projects, in addition to future generations of Intel IXA network processors.
Intel® XScale™ technology — providing the highest performance-to- power ratio in the industry.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Intel’s Gear (1)
IXP2850Designed for use in virtual private networks,
secure web services, and storage area networks.
IXP2800Able to handle line rates ranging from OC-48
to OC-192. IXP2400
Designed for OC-12 to OC-48 network access and edge applications.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Intel’s Gear (2) The IXP 1200 product line represents Intel’s first
attempt in the area (it was actually inherited when they purchased Digital)
The IXP 1200 is a single-board chip, designed with abstractions in mind.
Since this is a new area, and it’s designed to be used with many different types of hardware and software, the documentation is incomplete/unavailable/or just plain wrong.
To achieve wire-fast speeds with software, the goal is to hide latency with parallelism. Processing packets is inherently parallel, and necessary for fast applications.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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How does the IXP 1200 simplify the ASIC based design ?
A Typical ASIC Based DesignA processor to handle routing information and
higher level processingASICs to handle each packet
An IXP 1200 DesignStrongArm Core to handle routing algorithms
and higher level processingMicroengines to handle packet processing
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Conceptually: Two LevelsThe IXP1200 is designed to process packets at wire speed, but also to handle control-plane information.
1. Strong ARM Core (1): Designed to handle control-plane and slow-path processing. Update host tables, forwarding tables, filtering, running routing protocols.Runs an OS from a wide variety of sources (Linux derivatives / VxWorks).Has limited access to certain resources on board. Development is done using
WindRiver’s Tornado Embedded Linux ARM Software development kit C/C++
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Conceptually: Two Levels..
2. Micro Engines (6): Data-plane and fast-path processing.Run no OS. Our model has a 2K instruction-store per microengine.Multithreaded, 4 threads per engine.Has access to all resources on board. Since there is no OS, and these are virtually unrestricted, we must carefully avoid thread traps!Microengine Development Tools
Can write “microcode” or uEngine C Microcode Assembler Workbench
Write symbolic microcode Assemble and optimize
Transactor Debug and Simulation Engine
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Misc.
IX Bus:Provides interface to network ports, hardware shortcuts (like hardware hash unit), super-fast and super-small scratch memory area.StrongARM access to this is limited. It forces you to use the microEngines when you really don’t want to.
Interface DevicesIntel does not specify a type of interface to be used. These could be ATM, Ethernet, FastE, GigE, wireless, etc.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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IXP 1200 Building Blocks
SRAM Store packet headers
SDRAM Store packet data
PCI Interface For accessing the control processor
Microengines and StrongArm Core make requests to SRAM and SDRAM. The IX Bus and PCI Bus also make requests to SDRAM.
Different type of queues for arbitration. Programmers can choose the queues depending upon their requirements.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Design Solutions
Enterprise Routers Streaming Video Server
Manipulation of digitized video. Media Gateway
Seamless transport of voice from circuit-switched to packet-switched networks
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16 Port Store and Forward Design Receive Threads (16)
Receive packet from MAC port Verify IP Header Perform IP forwarding Place packet on transmit queue
Transmit Scheduler Threads (2) One per Microengine Determine which transmit queue has packets Assign work to each of three transmit threads
Transmit Threads (6) Three per microengine Send packet data to MAC port
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Rx: Lookup and Queuing
Lookup the forwarding information in SRAM based on header fields
Read the forwarding information from SDRAM Modify the header and writes it to buffer in SDRAM Write packet descriptor to SRAM Lock Transmit Queue in SRAM Enqueue packet onto the corresponding Transmit Queue
in SRAM Set Port With Packets bit in scratch indicating that port
has packets Unlock Transmit Queue in SRAM
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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Tx
Transmit SchedulerSequentially checks each port for data by
reading “Ports With Packets” in scratch memory.
Issues transmit assignments to the transmit threads.
Transmit threads.Lock the transmit queue, dequeue packet,
unlock queue.Move packet from SDRAM to TFIFO and set
TFIFO control bit.
Shivkumar KalyanaramanRensselaer Polytechnic Institute
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For more info….
Jonathan Gunner ([email protected]) Slide Contributions from Kerry Wood and Shruti
Gorappa