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Sequential Logic
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1 Sequential Sequential Logic Logic Lecture #7 Lecture #7
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Sequential Logic. Lecture #7. 강의순서. Latch FlipFlop Shift Register Counter. SR Latch. Most simple “ storage element ” . Q next = (R + Q ’ current ) ’ Q ’ next = (S + Q current ) ’. NOR. In1In2Out 001 010 100 110. Function Table. Storing. SR latches are sequential. - PowerPoint PPT Presentation
Transcript of Sequential Logic
1
Sequential Sequential LogicLogic
Lecture #7Lecture #7
모바일컴퓨팅특강 2
강의순서강의순서 Latch FlipFlop Shift Register Counter
모바일컴퓨팅특강 3
모바일컴퓨팅특강 4
SR LatchSR Latch
Most simple “storage element”.
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’
In1 In2 Out0 0 10 1 01 0 01 1 0
NOR
S R Q
0 0 No change0 1 0 (reset)1 0 1 (set)
Function Table
Storing
모바일컴퓨팅특강 5
SR latches are sequentialSR latches are sequential
For inputs SR = 00, the next value of Q depends on the current value of Q.
So the same inputs can yield different outputs.
This is different from the combinational logics.
I nputs Current NextS R Q Q’ Q Q’
0 0 0 1 0 10 0 1 0 1 0
0 1 0 1 0 10 1 1 0 0 11 0 0 1 1 01 0 1 0 1 0
S R Q
0 0 No change0 1 0 (reset)1 0 1 (set)
모바일컴퓨팅특강 6
Timing Diagram for S-R Timing Diagram for S-R LatchLatch
S
R
Q
Q’Set Reset
모바일컴퓨팅특강 7
SR latch simulationSR latch simulation
모바일컴퓨팅특강 8
What about SR = 11?What about SR = 11?
Both Qnext and Q’next will become 0.
If we then make S = 0 and R = 0 together,
Qnext = (0 + 0)’ = 1Q’next = (0 + 0)’ = 1
But these new values go back into the NOR gates, and in the next step we get:
Qnext = (0 + 1)’ = 0Q’next = (0 + 1)’ = 0
The logic enters an infinite loop, where Q and Q’ cycle between 0 and 1 forever. (Unstable)
This is actually the worst case, so we have to avoid setting SR=11.
Qnext = (R + Q’current)’Q’next = (S + Qcurrent)’
0
0
0
0
0
0
1
1
모바일컴퓨팅특강 9
An SR latch with a control An SR latch with a control inputinput(Gated SR latch)(Gated SR latch)
The dotted blue box is the S’R’ latch from the previous slide. The additional NAND gates are simply used to generate the corr
ect inputs for the S’R’ latch. The control input acts just like an enable.
C S R S’ R’ Q
0 x x 1 1 No change1 0 0 1 1 No change1 0 1 1 0 0 (reset)1 1 0 0 1 1 (set)1 1 1 0 0 Avoid!
모바일컴퓨팅특강 10
D latch (Gated D latch)D latch (Gated D latch)
D latch is based on an S’R’ latch. The additional gates generate the S’ and R’ signals, based on inputs D (“data”) and C (“control”).
When C = 0, S’ and R’ are both 1, so the state Q does not change.
When C = 1, the latch output Q will equal the input D. Single input for both set and reset
Also, this latch has no “bad” input combinations to avoid. Any of the four possible assignments to C and D are valid.
C D Q
0 x No change1 0 01 1 1
모바일컴퓨팅특강 11
Timing diagram for D Timing diagram for D LatchLatch
Q follows D while EN is HIGH.
모바일컴퓨팅특강 12
D latch with BDFD latch with BDF
모바일컴퓨팅특강 13
D latch simulation with D latch simulation with PrimitivePrimitive Insert the
symbol latch
모바일컴퓨팅특강 14
Simulation result with Simulation result with PrimitivePrimitive
모바일컴퓨팅특강 15
D latch simulation with D latch simulation with VHDL fileVHDL file
모바일컴퓨팅특강 16
The D Flip-Flop : Edge The D Flip-Flop : Edge triggeringtriggering
• The D flip-flop is said to be “edge triggered” since the output Q only changes on the rising edge (positive edge) of the clock signal
DLatch
D1
C
Q1
Q’
DLatch
D2
C
Q2
Q2’
D
C
Q
모바일컴퓨팅특강 17
Timing Diagram for a D-Timing Diagram for a D-FFFF
C
D
Q
Q1
shift
shift
Positive Edge Triggering
모바일컴퓨팅특강 18
D-FF with Direct Inputs D-FF with Direct Inputs
Most flip-flops provide direct, or asynchronous, inputs that immediately sets or clears the state.
The below is a D flip-flop with active-low direct inputs.S’ R’ C D Q
0 0 x x Avoid!0 1 x x 1 (set)1 0 x x 0 (reset)
1 1 0 x No change1 1 1 0 0 (reset)1 1 1 1 1 (set)
Direct inputs to set or reset the flip-flop
S’R’ = 11 for “normal” operation of the D flip-flop
모바일컴퓨팅특강 19
D-FF with BDFD-FF with BDF
Insert the symbol dff
Edge-trigger symbol
모바일컴퓨팅특강 20
D-FF with VHDL fileD-FF with VHDL file
모바일컴퓨팅특강 21
D-FF D-FF with active-high Clock &with active-high Clock & asynchronous asynchronous ClearClear
library ieee;use ieee.std_logic_1164.all;entity dff_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_1 ;architecture a of dff_1 isbegin
process(nclr,clk)begin if( nclr='0') then
q <='0'; elsif(clk'event and clk='1') then
q <= d; end if;end process;
end a;
모바일컴퓨팅특강 22
D-FF D-FF with active- low Clock &with active- low Clock & asynchronous asynchronous ClearClear
library ieee;use ieee.std_logic_1164.all;entity dff_fall_1 is port( d, clk, nclr : in std_logic; q : out std_logic );end dff_fall_1 ;architecture a of dff_fall_1 isbegin
process(nclr,clk)begin if( nclr='0') then
q <='0'; elsif(clk'event and clk=‘0') then
q <= d; end if;end process;
end a;
모바일컴퓨팅특강 23
D-FF D-FF with active-high Clock &with active-high Clock & asynchronous asynchronous PresetPreset
library ieee;use ieee.std_logic_1164.all;entity dff_ preset_1 is port( d, clk, npre : in std_logic; q : out std_logic );end dff_ preset_1 ;architecture a of dff_ preset_1 isbegin
process(npre,clk)begin if( npre='0') then
q <=‘1'; elsif(clk'event and clk=‘1') then
q <= d; end if;end process;
end a;
모바일컴퓨팅특강 24
D-FF D-FF with active-high Clock &with active-high Clock & asynchronous Clear & asynchronous Clear & PresetPresetlibrary ieee; use ieee.std_logic_1164.all;entity dff_ presetclr_1 is port( d, clk, npre,nclr : in std_logic; q : out std_logic );end dff_ presetclr_1 ;architecture a of dff_ presetclr_1 isbegin
process(npre, nclr, clk)begin if( npre='0') then
q <=‘1'; elsif( nclr='0') then
q <=‘0'; elsif(clk'event and clk=‘1') then
q <= d; end if;end process;
end a;
모바일컴퓨팅특강 25
JK-FF & T-FFJK-FF & T-FF
JK=11 are used to complement the flip-flop’s current state.
A T flip-flop can only maintain or complement its current state. C T Qnext
0 x No change1 0 No change1 1 Q’current
C J K Qnext
0 x x No change1 0 0 No change1 0 1 0 (reset)1 1 0 1 (set)1 1 1 Q’current
모바일컴퓨팅특강 26
7474 Dual D-FF7474 Dual D-FF
Insert the symbol others > quartus II > 7474
모바일컴퓨팅특강 27
7474 Dual D-FF “Datasheet” 7474 Dual D-FF “Datasheet” from Philipsfrom Philips Plastic dual in-line package
모바일컴퓨팅특강 28
7474 Dual D-FF “Datasheet” 7474 Dual D-FF “Datasheet” from Philipsfrom Philips
모바일컴퓨팅특강 29
Set-up and hold timesSet-up and hold times
For proper operation the D input to a D flip-flop should be stable for certain prescribed times before and after the rising clock edge. These are referred to as the set-up and hold times respectively
모바일컴퓨팅특강 30
Set-up time (tSet-up time (tss))
The logic level must be present on the D input for a time equal to or greater than ts before the triggering edge of the clock pulse for reliable data entry.
모바일컴퓨팅특강 31
Hold time (tHold time (thh))
The logic level must remain on the D input for a time equal to or greater than th after the triggering edge of the clock pulse for reliable data entry.
모바일컴퓨팅특강 32
D-FF timing constraintsD-FF timing constraints
Set-up time
Hold time
C
D
Q
Propagation delay
모바일컴퓨팅특강 33
Propagation Delay (1)Propagation Delay (1)
As with any other circuit there will be a propagation delay between the rising edge of the clock and the time that the outputs of the flip-flop are stable.
모바일컴퓨팅특강 34
Propagation delay (2)Propagation delay (2)
모바일컴퓨팅특강 35
7474 Timing characteristics from 7474 Timing characteristics from datasheetdatasheet
모바일컴퓨팅특강 36
Clock SignalClock Signal
Periodic signal, generated by an oscillator which acts as the heartbeat of a synchronous digital system
Clock Period
Clock Frequency = 1 / Clock Period
모바일컴퓨팅특강 37
Synchronous SystemsSynchronous Systems
In a synchronous system, all of the state elements are connected to the same clock signal.
This means that they all change state at the same time.
모바일컴퓨팅특강 38
Propagation delays through logic components (gates) through interconnects (routing delays)
tp gates tp routing
Gates Gates Gates
Total propagation delay through combinational logic
Timing Characteristics Timing Characteristics (1)(1)
모바일컴퓨팅특강 39
Total propagation delay of logic (Sum of tp gate) depends on the number of logic levels and delays of logic components
Number of logic levels is the number of logic components (gates) the signal propagates through
Routing delays (tp routing) depend on: Length of interconnects Fanout
Timing Characteristics (2)Timing Characteristics (2)
모바일컴퓨팅특강 40
Fanout – Number of inputs connected to one output• Each inputs has its capacitance• Fast switching of outputs with high fanout requires higher c
urrents This makes a larger delay.
Gates Gates
Gates
Gates
Timing Characteristics (3)Timing Characteristics (3)
모바일컴퓨팅특강 41
In Current Technologies Routing Delays Make 50-70% of the Total Propagation Delays
Timing Characteristics (4)Timing Characteristics (4)
모바일컴퓨팅특강
Critical path: the slowest path between any two storage devices
Cycle time is a function of the critical path must be greater than:
Clock-to-Q + Longest Path through Combinational Logic + Setup
Clk
.
.
.
.
.
.
.
.
.
.
.
.
Critical Path & Cycle TimeCritical Path & Cycle Time
모바일컴퓨팅특강 43
Min. Clock Period = Length of The Critical Path
Max. Clock Frequency = 1 / Min. Clock Period
Critical PathCritical Path
모바일컴퓨팅특강 44
Rising Edge of The Clock Does Not Occur Precisely Periodically May cause faults in the circuit
clk
Clock JitterClock Jitter
모바일컴퓨팅특강 45
Clock SkewClock Skew
Rising Edge of the Clock Does Not Arrive at Clock Inputs of All Flip-flops at The Same Time
D Qin
clk
D Qout
delay
D Qin
clk
D Qout
delay
모바일컴퓨팅특강 46
Dealing With Clock Dealing With Clock ProblemsProblems Use Only Dedicated Clock Nets for Clock
Signals
Do Not Put Any Logic in Clock Nets
모바일컴퓨팅특강 47
RegisterRegister
Flip-Flip 을 응용한 데이터 저장장치 가장 기본적인 순차논리회로
Multi-bit Register Shift Register Counter Register
모바일컴퓨팅특강 48
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY reg8 ISPORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END reg8 ;
ARCHITECTURE Behavior OF reg8 ISBEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENQ <= "00000000" ;
ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;
END IF ;END PROCESS ;
END Behavior ;`
Resetn
Clock
reg8
8 8
D Q
8-bit register with 8-bit register with asynchronous resetasynchronous reset
모바일컴퓨팅특강 49
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn ISBEGIN
PROCESS ( Resetn, Clock )BEGIN
IF Resetn = '0' THENQ <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;
END IF ;END PROCESS ;
END Behavior ;
Resetn
Clock
regn
N N
D Q
N-bit register with N-bit register with asynchronous resetasynchronous reset
모바일컴퓨팅특강 50
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn ISBEGIN
PROCESS (Clock)BEGIN
IF (Clock'EVENT AND Clock = '1' ) THENIF Enable = '1' THEN
Q <= D ;END IF ;
END IF;END PROCESS ;
END Behavior ;
QD
Enable
Clock
regn
N N
N-bit register with EnableN-bit register with Enable
모바일컴퓨팅특강 51
Shift registerShift register
D QSin
Clock
D Q D Q D Q
Q(3) Q(2) Q(1) Q(0)
Enable
모바일컴퓨팅특강 52
Shift Register With Parallel Shift Register With Parallel LoadLoad
D(3)
D Q
Clock
Enable
SinD(2)
D Q
D(1)
D Q
D(0)
D Q
Q(0)Q(1)Q(2)Q(3)
Load
모바일컴퓨팅특강 53
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY shift4 ISPORT ( D : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END shift4 ;
Q
Enable
Clockshift4
4
D
Load
Sin
4
4-bit shift register 4-bit shift register with parallel load (1)with parallel load (1)
모바일컴퓨팅특강 54
ARCHITECTURE Behavior_1 OF shift4 ISBEGIN
PROCESS (Clock)BEGIN
IF Clock'EVENT AND Clock = '1' THENIF Load = '1' THEN
Q <= D ;ELSIF Enable = ‘1’ THEN
Q(0) <= Q(1) ;Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= Sin;
END IF ;END IF ;
END PROCESS ;END Behavior_1 ;
Q
Enable
Clockshift4
4
D
Load
Sin
4
4-bit shift register 4-bit shift register with parallel load (2)with parallel load (2)
모바일컴퓨팅특강 55
LIBRARY ieee ;USE ieee.std_logic_1164.all ;
ENTITY shiftn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END shiftn ;
Q
Enable
Clockshiftn
N
D
Load
Sin
N
N-bit shift register N-bit shift register with parallel load (1)with parallel load (1)
모바일컴퓨팅특강 56
ARCHITECTURE Behavior OF shiftn ISBEGIN
PROCESS (Clock)BEGIN
IF (Clock'EVENT AND Clock = '1' ) THENIF Load = '1' THEN
Q <= D ;ELSIF Enable = ‘1’ THEN
Genbits: FOR i IN 0 TO N-2 LOOPQ(i) <= Q(i+1) ;
END LOOP ;Q(N-1) <= Sin ;
END IF;END IF ;
END PROCESS ;END Behavior ;
Q
Enable
Clockshiftn
N
D
Load
Sin
N
N-bit shift register N-bit shift register with parallel load (2)with parallel load (2)
모바일컴퓨팅특강 57
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount IS
PORT ( Clear, Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;
END upcount ;
ARCHITECTURE Behavior OF upcount ISBEGIN
upcount: PROCESS ( Clock )BEGIN
IF (Clock'EVENT AND Clock = '1') THENIF Clear = '1' THEN
Q <= "00" ;ELSE
Q <= Q + “01” ;END IF ;
END IF;END PROCESS;
END Behavior ;
QClear
Clock
upcount
2
2-bit up-counter 2-bit up-counter with synchronous with synchronous
resetreset
모바일컴퓨팅특강 58
LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;
ENTITY upcount ISPORT ( Clock, Resetn, Enable : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;END upcount ;
Q
Enable
Clockupcount
4
Resetn
4-bit up-counter 4-bit up-counter with asynchronous with asynchronous
reset (1)reset (1)
모바일컴퓨팅특강 59
ARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
BEGINPROCESS ( Clock, Resetn )BEGIN
IF Resetn = '0' THENCount <= "0000" ;
ELSIF (Clock'EVENT AND Clock = '1') THENIF Enable = '1' THEN
Count <= Count + 1 ;END IF ;
END IF ;END PROCESS ;Q <= Count ;
END Behavior ;
Q
Enable
Clockupcount
4
Resetn
4-bit up-counter 4-bit up-counter with asynchronous with asynchronous
reset (2)reset (2)
모바일컴퓨팅특강 60
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;entity cnt161_4bits is port( d3,d2,d1,d0 : in std_logic; nld,ent,enp : in std_logic; clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic; rco : out std_logic);end cnt161_4bits;architecture a of cnt161_4bits is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)variable d : std_logic_vector(3 downto 0);begin
d := d3&d2&d1&d0;if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then
if(nld='0') then q <= d;elsif(ent='1' and enp='1') then
q <= q+'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0); rco <= ent and q(3) and q(2) and q(1) and
q(0);end a;
74161 은 실제로 가장 널리 사용되는 4 비트
카운터임
74161 은 실제로 가장 널리 사용되는 4 비트
카운터임
4 bits Universal Counter: 4 bits Universal Counter: 7416174161
모바일컴퓨팅특강 61
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod16cnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod16cnt;architecture a of mod16cnt is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)begin
if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then
q <= q+'1';end if;
end process;q3<=q(3); q2<=q(2); q1<=q(1);
q0<=q(0); end a;
Modulo 16 Up CounterModulo 16 Up Counter
모바일컴퓨팅특강 62
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod16dncnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod16dncnt;architecture a of mod16dncnt is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)begin
if( nclr='0') then q <="0000";elsif(clk'event and clk='1')
thenq <= q-'1';
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1);
q0<=q(0); end a;
Modulo 16 Down CounterModulo 16 Down Counter
모바일컴퓨팅특강 63
Modulo 16 Up Down Modulo 16 Up Down countercounter
library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity UpDncnt4 is port( clk,nclr : in std_logic;
UpDn : in std_logic; q3,q2,q1,q0 : out std_logic);end UpDncnt4;architecture a of UpDncnt4 is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)begin
if( nclr='0') then q <="0000";elsif(clk'event and clk='1') then
if( UpDn='1') then q <= q+'1';else q <= q-'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1); q0<=q(0);
end a;
1 이면 증가
1 이면 증가
0 이면 감소
0 이면 감소
모바일컴퓨팅특강 64
library ieee; use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mod15cnt is port( clk,nclr : in std_logic; q3,q2,q1,q0 : out std_logic);end mod15cnt;architecture a of mod15cnt is
signal q : std_logic_vector( 3 downto 0);begin
process(nclr,clk)begin
if( nclr='0') thenq <="0000";
elsif(clk'event and clk='1') thenif( q="1110") then
q<="0000";else q <= q+'1';end if;
end if;end process;q3<=q(3); q2<=q(2); q1<=q(1);
q0<=q(0); end a;
14에서 0
으로 증가
14에서 0
으로 증가
Modulo 15 Up CounterModulo 15 Up Counter
