Digital System Ch5-1 Chapter 5 Synchronous Sequential Logic Ping-Liang Lai ( 賴秉樑 ) Digital...

Digital System Ch5-1

Chapter 5 Synchronous Sequential Logic

Ping-Liang Lai (賴秉樑 )

Digital System數位系統


Outline of Chapter 5

5.1 Introduction 5.2 Sequential Circuits 5.3 Storage Element: Latches 5.4 Storage Element: Flip-Flops 5.5 Analysis of Clocked Sequential Circuits 5.7 State Reduction and Assignment 5.8 Design Procedure


5-1 Introduction

Combinational circuits Contains no memory elements The outputs depends on the inputs


5-2 Sequential Circuits

Sequential circuits

A feedback path The state of the sequential circuit (inputs, current state) (outputs, next state) Synchronous: the transition happens at discrete instants of time Asynchronous: at any instant of time


Synchronous sequential circuits A master-clock generator to generate a periodic train of clock pulses The clock pulses are distributed throughout the system Clocked sequential circuits Most commonly used No instability problems The memory elements: flip-flops

» Binary cells capable of storing one bit of information.» Two outputs: one for the normal value and one for the complement value.» Maintain a binary state indefinitely until directed by an input signal to switch

states.

Digital System Ch5-6Fig. 5.2 Synchronous clocked sequential circuit


5-3 Latches (栓鎖器 )

Basic flip-flop circuit Two NOR gates

More complicated types can be built upon it Directed-coupled RS flip-flop: the cross-coupled connection An asynchronous sequential circuit (S, R)= (0, 0): no operation (S, R)=(0, 1) : reset (Q=0, the clear state) (S, R)=(1, 0) : set (Q=1, the set state) (S, R)=(1, 1) : indeterminate state (Q=Q'=0) Consider (S, R) = (1, 1) (0, 0)


SR latch with NAND gates

Fig. 5.4 SR latch with NAND gates


SR latch with control input En=0, no change En=1,

0/1

1/S'

1/R'

Fig. 5.5 SR latch with control input


D Latch Eliminate the undesirable conditions of the indeterminate state in the RS flip-flop D: data Gated D-latch D Q when En=1; no change when En=0

Fig. 5.6 D latch

S

R

0/1

1/D'

1/D


Fig. 5.7 Graphic symbols for latches


5-4 Flip-Flops (正反器 )

A trigger The state of a latch or flip-flop is switched by a change of the control

input. Level triggered – Latches Edge triggered – Flip-Flops

Fig. 5.8 Clock response in latch and flip-flop


If level-triggered flip-flops are used (準位觸發 ) The feedback path may cause instability problem

Edge-triggered flip-flops (邊緣觸發 ) The state transition happens only at the edge Eliminate the multiple-transition problem


Edge-triggered D flip-flop

Master-slave D flip-flop Two separate flip-flops A master flip-flop (positive-level triggered) A slave flip-flop (negative-level triggered)

Fig. 5.9 Master-slave D flip-flop


CP = 1: (S, R) (Y, Y'); (Q, Q') holds. CP = 0: (Y, Y') holds; (Y, Y') (Q, Q'). (S, R) could not affect (Q, Q') directly. The state changes coincide with the negative-edge transition of CP.

第三版內容，參考用 !


Edge-triggered flip-flops The state changes during a clock-pulse transition

A D-type positive-edge-triggered flip-flop

Fig. 5.10 D-type positive-edge-triggered flip-flop


Three basic flip-flops (S, R) = (0, 1): Q = 1 (S, R) = (1, 0): Q = 0 (S, R) = (1, 1): no operation (S, R) = (0, 0): should be avoided

Fig. 5.10 D-type positive-edge-triggered flip-flop


10

0

10

01

1

11

1

1

1

11

1

1

01

1

0

0

0

1

Holding data

Set Reset

Clk=0 Clk=0

Clk=1 Clk=1

positive-edge-triggered


Setup and Hold Time for FF

The setup time D input must be maintained at a constant value prior to the application of

the positive CP pulse. Data to the internal latches.

The hold time D input must not changes after the application of the positive CP pulse. Clock to the internal latch.

QD

CK

D

CK

Tsetup Thold

D

Q

Tpropagation delay


Summary CP=0: (S, R) = (1, 1), no state change CP=↑: state change once CP=1 and ↓ : state holds Eliminate the feedback problems in sequential circuits

All flip-flops must make their transition at the same time


Other Flip-Flops

The edge-triggered D flip-flops The most economical and efficient Positive-edge and negative-edge

Fig. 5.11 Graphic symbols for edge-triggered D flip-flop


JK FF

JK flip-flop

D=JQ’+K’Q J=0, K=0: D=Q, no change J=0, K=1: D=0 Q=0 J=1, K=0: D=1 Q=1 J=1, K=1: D=Q' Q=Q'

Fig. 5.12 JK flip-flop

J K Q(t+1)

0 0 Q(t) (No change)

0 1 0 (Reset)

1 0 1 (Set)

1 1 Q’(t) (Complement)


T FF

T (toggle) flip-flop

D = T⊕Q = TQ'+T'Q» T=0: D=Q, no change» T=1: D=Q' Q=Q'

Fig. 5.13 T flip-flop T Q(t+1)

0 Q(t) (No change)

1 Q’(t) (Complement)


Summary

Characteristic tables


Characteristic equations D flip-flop

» Q(t+1) = D JK flip-flop

» Q(t+1) = JQ'+K'Q T flop-flop

» Q(t+1) = T⊕Q


Direct inputs

Asynchronous set and/or asynchronous reset

Fig. 5.14 D flip-flop with asynchronous reset


5-5 Analysis of Clocked Sequential Circuits

A sequential circuit (inputs, current state) (output, next state). A state equation (also called transition equation) specified the next state as

a function of the present state and inputs. A state transition table or state transition diagram.


State Equations

State Equations A(t+1) = A(t)x(t) + B(t)x(t) B(t+1) = A'(t)x(t)

A compact form A(t+1) = Ax + Bx B(t+1) = A'x

The output equation y(t) = (A(t)+B(t))x'(t) y = (A+B)x'

Fig. 5.15 Example of sequential circuit


State Table

State transition table = State equations

A(t + 1) =Ax + BxB(t + 1) = Axy = Ax + Bx


State Equation

A(t + 1) =Ax + BxB(t + 1) = Axy = Ax + Bx


State Diagram

State transition diagram A circle: a state. A directed lines connecting the circles: the transition between the states

» Each directed line is labeled “ inputs/outputs ”.

A logic diagram a state table a state diagram.

Fig. 5.16 State diagram of the circuit of Fig. 5.15


Flip-Flop Input Equations

The part of circuit that generates the inputs to flip-flops Also called excitation functions DA = Ax +Bx

DB = A'x

The output equations To fully describe the sequential circuit y = (A+B)x'

Note Q(t+1)=DQ

DA

DB

y


Analysis with D FFs

The input equation DA=A⊕x⊕y

The state equation A(t+1)=A⊕x⊕y

Fig. 5.17 Sequential circuit with D flip-flop


Analysis with JK flip-flops

The next-state can be derived by following procedure1. Determine the flip-flop equations in terms of the present state and input

variables (用目前狀態和輸入變數的觀點決定正反器的輸入方程式 );

2. List the binary values of each input equation (列出每一個輸入方程式的二進位值 );

3. Use the corresponding flip-flop characteristic table to determine the next state values in the state table (使用相對應的的正反器特性表，決定狀態表中的次一狀態值 ).


Analysis with JK Flip-Flops

An sequential circuit with JK FFs Determine the flip-flop input function in terms of the present state and

input variables; Used the corresponding flip-flop characteristic table to determine the next

state.

Fig. 5.18 Sequential circuit with JK flip-flop

JA=B, KA=Bx’JB=x’, KB=A’x+Ax’


JA = B, KA= Bx' JB = x', KB = A'x + Ax' Derive the state table

Or, derive the state equations using characteristic equation.

J K Q(t+1)


0 1 0 (Reset)

1 0 1 (Set)



State transition diagram

State equation for A and B:

( 1) ( )A t BA Bx A A B AB Ax

( 1) ( )B t x B A x B B x ABx A Bx

Fig. 5.19 State diagram of the circuit of Fig. 5.18

( 1)

( 1)

A t JA K A

B t JB K B

JA=B, KA=Bx’JB=x’, KB=A’x+Ax’


Analysis with T Flip-Flops

The characteristic equation Q(t+1)= T⊕Q = TQ'+T'Q

Fig. 5.20 Sequential circuit with T flip-flop


The input and output functions TA=Bx

TB= x y = AB

The state equations A(t+1) = (Bx)'A+(Bx)A' =AB'+Ax'+A'Bx B(t+1) = x⊕B


State Table

T Q(t+1)

0 Q(t) (No change)



Mealy and Moore Models

The Mealy model (密利模型 ): the outputs are functions of both the present state and inputs (Fig. 5-15). The outputs may change if the inputs change during the clock pulse

period.» The outputs may have momentary false values unless the inputs are

synchronized with the clocks.

The Moore model (莫爾模型 ): the outputs are functions of the present state only (Fig. 5-20). The outputs are synchronous with the clocks.


Mealy and Moore Models

Fig. 5.21 Block diagram of Mealy and Moore state machine


5-7 State Reduction and Assignment

State Reduction (狀態簡化 ) Reductions on the number of flip-

flops and the number of gates. A reduction in the number of

states may result in a reduction in the number of flip-flops.

An example state diagram showing in Fig. 5.25.

Fig. 5.25 State diagram


State Reduction

Only the input-output sequences are important.

Two circuits are equivalent» Have identical outputs for all

input sequences;» The number of states is not

important.

Fig. 5.25 State diagram

State: a a b c d e f f g f g a

Input: 0 1 0 1 0 1 1 0 1 0 0

Output:

0 0 0 0 0 1 1 0 1 0 0


Equivalent states Two states are said to be equivalent

» For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state.

» One of them can be removed.


Reducing the state table e = g (remove g); d = f (remove f);


The reduced finite state machine

State: a a b c d e d d e d e a

Input: 0 1 0 1 0 1 1 0 1 0 0

Output:

0 0 0 0 0 1 1 0 1 0 0


The checking of each pair of states for possible equivalence can be done systematically (section 9-5).

The unused states are treated as don't-care condition fewer combinational gates.

Fig. 5.26 Reduced State diagram


State Assignment

State Assignment (狀態指定 ) To minimize the cost of the combinational circuits. Three possible binary state assignments. (m states need n-bits, where 2n >

m)


Any binary number assignment is satisfactory as long as each state is assigned a unique number.

Use binary assignment 1.


5-8 Design Procedure

Design Procedure for sequential circuit (設計程序 ) The word description of the circuit behavior to get a state diagram; ( 從文字敘述及所需的操作規格，獲得電路的狀態圖 )

State reduction if necessary; (如果需要，簡化狀態數量 ) Assign binary values to the states; (指定狀態的二進位值 ) Obtain the binary-coded state table; (獲得二進位編碼的狀態表 ) Choose the type of flip-flops; (選擇欲使用的正反器形式 ) Derive the simplified flip-flop input equations and output equations; (推導出已化簡的輸入方程式，及輸出方程式 )

Draw the logic diagram; (繪製邏輯圖 )


Synthesis using D flip-flops

An example state diagram and state table: design a circuit to detect a sequence of three or more consecutive 1’s.

Fig. 5.27 State diagram for sequence detector


The flip-flop input equations A(t+1) = DA(A, B, x) = (3, 5, 7)

B(t+1) = DB(A, B, x) = (1, 5, 7)

The output equation y(A, B, x) = (6, 7)

Logic minimization using the K map DA= Ax + Bx

DB= Ax + B'x y = AB


Fig. 5.28 Maps for sequence detector


Sequence Detector

The logic diagram

Fig. 5.29 Logic diagram of sequence detector


Excitation Tables (激勵表 )

A state diagram flip-flop input functions Straightforward for D flip-flops. We need excitation tables for JK and T

flip-flops.

J K Q(t+1)


0 1 0 (Reset)

1 0 1 (Set)


T Q(t+1)

0 Q(t) (No change)



Synthesis using JK FFs

The same procedure with D FFs, but a extra excitation table must be used.

The state table and JK flip-flop inputs.


JA = Bx'; KA = Bx JB = x; KB = (A⊕x)‘ y = ?

Fig. 5.30 Maps for J and K input equations

Digital System Ch5-59Fig. 5.31 Logic diagram for sequential circuit with JK flip-flops


Synthesis using T flip-flops

A n-bit binary counter The state diagram. No inputs (except for the clock input).

Fig. 5.32 State diagram of three-bit binary counter


The state table and the flip-flop inputs


Fig. 5.33 Maps of three-bit binary counter


Logic simplification using the K map TA2 = A1A2

TA1 = A0

TA0 = 1

The logic diagram

Fig. 5.34 Logic diagram of three-bit binary counter

陳澄波—嘉義公園 <公園 (嘉義遊園地 )> 1937‧ 年‧油彩、畫布‧ 130×162cm‧台灣省立美術館收藏。 (Source: http://www.aerc.nhcue.edu.tw/)

陳澄波 [1895 ~ 1947]

http://www.aerc.nhcue.edu.tw/

Digital System Ch5-1 Chapter 5 Synchronous Sequential Logic Ping-Liang Lai ( 賴秉樑 ) Digital...

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