SOC Design for Digital Surveillance System

2007/6/6

王逸竹

Outline

Digital video recording (DVR) system Surveillance application Features

SOC design and challenge Architecture HW/SW partition issue Verification issue

Summary

What is Digital Video Recorder (DVR) 取代傳統類比式閉路電視系統

及時監看 , 錄影 回播

數位化 壓縮 , 保存 , 傳輸

Market trend

Demand 國際恐怖事件頻傳 安全意識抬頭 對生活品質要求的提升

應用 交通要道 ( 車站 , 機場 ) 金融機構 工廠 社區住家

安控市場成長趨勢

DVR 市場成長趨勢

Application examples

Surveillance 尋找車禍肇事者 紀錄事實 319 槍擊案 , 鎖定嫌疑犯 尋找特定事件 草山行館火災 , 燒毀主機 異地備份

Intelligent processing 辨識 ( 車牌 , 人臉 , 特殊行為 , 遺留物品 ) 計數 ( 車流量 , 人潮 ) 自動追蹤

DVR system

Picture from: http://safeland.en.ec21.com/

Market segment

High-end (group A) Stability High recording

speed

Low-end (group C) Reasonable prices Reasonable

recording quality

Picture from: http://www.asmag.com/

PC-based v.s. standalone DVR

PC-based Standalone

flexibility high low

power high low

stability low high

UI complex friendly

cost high low

Our DVR SOC

Target single chip for low-end DVR 可擴充 ( 串接 , 或外加 host CPU) 以實現 middle-end, high-

end DVR

Our strength Multimedia processing engines

First hardware MPEG-4 full-D1 encoder in Taiwan Analog/digital video processing

System know-how Customer’s requirement

Key PadAlarm

Sensor

HDD

Monitor

Camera

4-ch DVR SOC

record

playback

Target product: 4-ch DVR

preview

Extend product: 8/16-ch DVR

4-ch DVR SOC

4-ch DVR SOC

4-ch DVR SOC

4-ch DVR SOC

FPGA

video (quad or full)

bitstreamcommand

Key PadAlarm

Sensor

Monitor

HDD

Extend product: Network DVR

4-ch DVR SOC

Network-enabled platform

Key PadAlarmHDD

LANWANWEB

Remote monitor

IP camera

NASCentral monitor

Extent product: other types

Mobile DVR Compact size Shock-proof

POS DVR Overlap text (sale items or transaction data) and

video

Design for DVR SOC

Target specification (1)

4 cameras and microphone input MPEG-4 video codec

Resolution: half-D1 or CIF Audio codec (ADPCM) Triplex: preview + record + playback Display on TV / VGA

Full screen / quad display

Recording mode Manual / Scheduled / Alarm / Motion

Adjustable recording quality and frame rate Adjustable motion detection parameters

Target specification (2)

Playback mode Search by recording list / time / motion Normal / pause / fast forward / fast rewind / A-B repeat

Support up to 2 HDD 1 HDD endless recording “HOT Swap” with 2 HDD

CF backup (AVI format)

Built-in OSD Built-in 8-bit Turbo 8051 MCU Host interface

Block diagram

Video in/out

Capture CCIR-656 format

Transform YCbCr422 interleave to YCbCr 420 planer transform

Decimation ½ horizontal sub-sample

Cropping De-interlace

Edge detection

MPEG-4 encoder (1)

G ate count: 75K @ 27M Hz

ME

HyRISC

MEDM A

SRAMSRAMSRAM

MCBlock

EngineBitstream

UnitSDRAMC TRL

Off-chipSDRAM

Off-chipSDRAM

Off-chipSDRAM

RISC BUS (16-bit)

DATA BUS (32-bit)

SRAMSRAMFirmware

MPEG-4 encoder (2)

Support MPEG-4 Simple Profile Encode 4-ch source as 4 independent streams Variable picture resolution

From 64*64 to 720*480 (16-pixel steps) Computation power

Real time encoding Full-D1 @ 30fps when operate at 54 MHz Flexible bit rate and frame rate control

Platform-based architecture Embedded HyRISC for global control, mode decision and encodi

ng algorithms Hardware accelerators for computation-extensive tasks

MPEG-4 decoder (1)

HyRISC

DM A

SRAMSRAMSRAM

MCBlock

EngineVLD

SDRAMC TRL

Off-chipSDRAM

Off-chipSDRAM

Off-chipSDRAM

RISC BUS (16-bit)

DATA BUS (32-bit)

SRAMSRAMFirmware

MPEG-4 decoder (2)

Support MPEG-4 Simple Profile without error resilience

Maximum output resolution Full-D1 (720x480 progressive), 30fps at 27MHz

Variable picture resolution 16x16 to 720x480

Support JPEG decode as well Auto recovery when decoding error

File system (1)

Simple file system

HDD allocation Global table: disk

information Table1: recording

information Table 2: time index table Video data Backup area: Duplicate

tables

Global table

Table 1

Table 2

Video data

Backup area

HDD

File system (2)

Special case Endless record HDD exception

當錄影時遇到壞軌 當放影時遇到壞軌 Index table 遇到壞軌

System bus

High-speed bus 166 MHz Video data Multi-channel DM

A

Low-speed bus 27 MHz Bitstream, comm

and HDD, CF

HW/SW partition

Software decision, system control, user command

Hardware computation-intensive task (ex: codec) regular operation (ex: DMA)

Example ( 放影 ): file-level 以上由 SW 處理， file-level 以下由 HW 處理 SW: 依播放時間搜尋檔案，計算播放起始位置，啟動相關硬

體模組 HW: 從硬碟中取出資料， 解碼， 播放

Design Challenge (1)

SOC integration audio/video pre-processing/post-processing audio/video compression SDRAM controller OSD embedded RISC IDE IF flash memory controller

Design Challenge (2)

Complexity real-time compression audio & video synchronization full-duplex recording & playback high speed SDRAM controller

video in + MPEG-4 codec + VGA display: 166M DW/s file system

Design challenge (3)

Simulation is time-consuming Video pattern

Take 3 day for 1-sec behavior!! Many design cases Create behavior models to speed up simulation

We have developed about 30 models, but... Create model also takes some efforts And, what if the model is not qualified?

Design challenge (4)

Hardware/Software co-design 不同的思維方式 Partition trade-off (large solution space)

Physical design Timing (ex: SDRAM) Testing

Design challenge (5)

系統相容性 Camera HDD 嚴苛的環境

系統穩定性 Keep it simple and stupid…

Verification challenges

Corner case 思考的盲點 Corner case maybe not easy to create Corner case maybe very very deep, need long

time to simulated it Ex: buffer overflow

球員兼裁判

Design phase review

Overlap in specification/architecture phase and RTL-design phase; multiple design changes

SW development starting late in the project

RTL Closure Tape-Out

Specification & Architecture

Hardware Dev.

Software Dev.

Physical Design

New design methodology/concept Design document

Confirm spec. as early as possible

System modelling ESL (Electronics System Level) Verify architecture as early as possible

Property check Assertion

Coverage functional coverage Assertion coverage

Tape-OutRTL Closure

Time Savings

Quality

Architecture Closure

Specification& Architecture

Create Executable Specifications

Hardware Dev.

Software Dev.

Physical Design

New SOC design phase

Architecture closure Achieve a reduction # of RTL iterations Can perform concurrent HW and SW design Shorten the time it takes to get to golden RTL

Run SW on the architecture model

Summary

Introduce digital video recorder system Present our DVR SOC design

What I have learned in this project From IP to SOC From design to verification From one to team

Thank you