Sequential Circuit Design - National Chiao Tung...

Introduction to VLSI and System-on-Chip Design

Sequential Circuit Design

Lan-Da Van (), Ph. D.Department of Computer ScienceNational Chiao Tung University

Taiwan, R.O.C.Fall, 2009

[email protected]

http://www.cs.nctu.edu.tw/~ldvan/

Lan-Da Van VLSI-06-2

Lecture 6


OutlinesIntroductionSequencing MethodsLatches and Flip-FlopsSequential System DesignConclusion


Lecture 6


Sequential MachinesUse memory elements to make primary output values depend on (state + primary inputs).Varieties:

Mealy machines outputs function of present state and inputs;Moore machines outputs depend only on state.

Machine computes next state N, primary outputs O from current state S, primary inputs I.

Next-state function:N = (I,S).

Output function (Mealy):O = (I,S).

Duty cycle: fraction of clock period for which clock is active (e.g., for active-low clock, fraction of time clock is 0).


Lecture 6


FSM Structure


Lecture 6


Sequencing Elements

Latch: level sensitiveTransparent latch, D latch

Flip-flop: edge triggeredMaster-slave flip-flop, D flip-flop, D register

Timing DiagramsTransparentEdge-trigger D Flo

p

Latc

h

Q

clk clk

D Q

clk

D

Q (latch)

Q (flop)


Lecture 6


Memory Elements

Store a value as controlled by one or more control inputs.May have multiple control inputs.

Clock, Load, S-R, In CMOS, memory is created by:

capacitance (dynamic);feedback (static).

Storage elementLatch: transparent when internal memory is being set from input.Flip-flop: not transparent reading input and changing output are separate events.


Lecture 6


Memory Categories

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory(CAM)

Read/Write Memory(RAM)

(Volatile)

Read Only Memory(ROM)

(Nonvolatile)

Static RAM(SRAM)

Dynamic RAM(DRAM)

Shift Registers Queues

First InFirst Out(FIFO)

Last InFirst Out(LIFO)

Serial InParallel Out

(SIPO)

Parallel InSerial Out

(PISO)

Mask ROM ProgrammableROM

(PROM)

ErasableProgrammable

ROM(EPROM)

ElectricallyErasable

ProgrammableROM

(EEPROM)

Flash ROM


Lecture 6


Setup & Hold TimesSetup time: time before clock during which data input must be stable.Hold time: time after clock event for which data input must remain stable.

clock

data


Lecture 6


Sequencing Methods

Flip-flops2-Phase LatchesPulsed Latches

Flip-Flops

Flop

Latc

h

Flop

clk

1

2

p

clk clk

Latc

h

Latc

h

p p

1 12

2-Phase Transparent Latches

Pulsed Latches

Combinational Logic

CombinationalLogic

CombinationalLogic

Combinational Logic

Latc

h

Latc

h

Tc

Tc/2

tnonoverlap tnonoverlap

tpw

Half-Cycle 1 Half-Cycle 1


Lecture 6


Timing Diagrams

Contamination and Propagation Delays

Flop

A

Y

tpdCombinational

LogicA Y

D Q

clk clk

D

Q

Latc

hD Q

clk clk

D

Q

tcd

tsetup thold

tccq

tpcq

tccq

tsetup tholdtpcq

tpdqtcdq

tpd Logic Prop. Delay

tcd Logic Cont. Delay

tpcq Latch/Flop Clk-Q Prop Delay

tccq Latch/Flop Clk-Q Cont. Delay

tpdq Latch D-Q Prop Delay

tpcq Latch D-Q Cont. Delay

tsetup Latch/Flop Setup Time

thold Latch/Flop Hold Time


Lecture 6


Max-Delay: Flip-Flops

F1 F2

clk

clk clk

Combinational Logic

Tc

Q1 D2

Q1

D2

tpd

tsetuptpcq

( )setupsequencing overhead

pd c pcqt T t t +14243


Lecture 6


Max-Delay Example (1/2)

Suppose the registers are built from flip-flops with a setup time of 62ps, hold time of -10ps, propagation delay of 90nps and contamination delay of 75ps.


Lecture 6


Max-Delay Example (2/2)

setuppdpcqc tttT ++

pst pd 1000701008010060590 =+++++=

psTc 115262100090 =++


Lecture 6


Max Delay: 2-Phase Latches

Tc

Q1

L1

1

2

L2 L3

1 12

CombinationalLogic 1


Q2 Q3D1 D2 D3

Q1

D2

Q2

D3

D1

tpd1

tpdq1

tpd2

tpdq2

( )1 2sequencing overhead

2pd pd pd c pdqt t t T t= + 123


Lecture 6


Max Delay: Pulsed Latches

L1 L2


max ,pd c pdq pcq pwt T t t t t + 14444244443


Lecture 6


Max-Delay Example

Re-compute the ALU self-bypass path cycle time if the flip-flop is replaced with a pulsed latch. The pulsed latch has a pulse width of 150 ps, a setup time of 40 ps, a hold time of 5 ps, a clk-to-Q propagation delay of 82 psand contamination delay of 52 ps, and a D-to-Q propagation delay of 92 ps.Solution:


max ,pd c pdq pcq pwt T t t t t + 14444244443

psTc 1092)15040100082,100092max( =+++


Lecture 6


Min-Delay: Flip-Flops

holdcd ccqt t t CL

clk

Q1

D2

F1clk

Q1F2

clk

D2

tcd

thold

tccq


Lecture 6


Min-Delay Example

In the ALU self-bypass example with the flip-flop from Fig. 7.6, the earliest input to the late bypass multiplexer is the imm value coming from another flip-flop. Will this path experience any hold time failures? Solution: No. The late bypass mux has tcd=45 ps. The flip-flops have thold=-10ps and tccq=75 ps. Hence, tcd=45 ps is larger than (thold-tccq=-10-75=-85 ps).


Lecture 6


Min-Delay: 2-Phase Latches

1, 2 hold nonoverlapcd cd ccqt t t t t

CL

Q1

D2

D2

Q1

1

L12

L2

1

2

tnonoverlap

tcd

thold

tccq

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops.

But a flop is made of two latches!


Lecture 6


Min-Delay: Pulsed Latches

holdcd ccq pwt t t t +

CL

Q1

D2

Q1

D2

p tpw

pL1

p

L2

tcd

thold

tccq

Hold time increased by pulse width


Lecture 6


Time Borrowing

In a flop-based system:Data launches on one rising edgeMust setup before next rising edgeIf it arrives late, system failsIf it arrives early, time is wastedFlops have hard edges

In a latch-based systemData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycle


Lecture 6


Time Borrowing Example

Latc

h

Latc

h

Latc

h

Combinational Logic CombinationalLogic

Borrowing time acrosshalf-cycle boundary

Borrowing time acrosspipeline stage boundary

(a)

(b) Latc

h

Latc

h

Combinational Logic CombinationalLogic

Loops may borrow time internally but must complete within the cycle

1

2

1 1

1

2

2


Lecture 6


How Much Borrowing?2-Phase Latches

Q1

L1

1

2

L2

1 2

Combinational Logic 1Q2D1 D2

D2

Tc

Tc/2 Nominal Half-Cycle 1 Delay

tborrow

tnonoverlap

tsetup

( )borrow setup nonoverlap2cTt t t + borrow setuppwt t t

Pulsed Latches


Lecture 6


Clock Skew

We have assumed zero clock skewClocks really have uncertainty in arrival time

Decreases maximum propagation delayIncreases minimum contamination delayDecreases time borrowing

Clock must arrive at all memory elements in time to load data.


Lecture 6


Clock Skew: Flip-Flops

F1 F2

F1

F2

( )setup skewsequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

+ +

+

144424443


Lecture 6


Clock Skew: Latches

Q1

L1

1

2

L2 L3

1 12



Q2 Q3D1 D2 D3

( )

( )

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

2

,

2

pd c pdq

cd cd ccq

c

t T t

t t t t t t

Tt t t t

+

+ +

123

( )

( )

setup skew

sequencing overhead

hold skew

borrow setup skew

max ,pd c pdq pcq pw

cd pw ccq

pw

t T t t t t t

t t t t t

t t t t

+ +

+ +

+

1444442444443

Pulsed Latches

2-Phase Latches


Lecture 6


Two-Phase Clocking

If setup times are violated, reduce clock speedIf hold times are violated, chip fails at any speedIn this class, working chips are most important

No tools to analyze clock skew

An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesCall these clocks 1, 2 (ph1, ph2)


Lecture 6


Signal SkewMachine data signals must obey setup and hold times avoid signal skew.


Lecture 6


Data Shoot ThroughLatches do not cut combinational logic when clock is active.Latch-based machines must use multiple ranks of latches.Multiple ranks require multiple phases of clock.Data shoot through occurs if single-phase latch is used.


Lecture 6


Unbalanced Delays

Logic with unbalanced delays leads to inefficient use of logic:

short clock period long clock period


Lecture 6


Retiming Solution

Retiming moves memory elements through combinational logic:

Property:Retiming changes encoding of values in registers, but proper values can be reconstructed with combinational logic.Retiming must preserve number of latches OR registers around a cycle.


Lecture 6


Summary

Flip-Flops:Very easy to use, supported by all tools

2-Phase Transparent Latches:Lots of skew tolerance and time borrowing

Pulsed Latches:Fast, some skew tol & borrow, hold time risk


Lecture 6


OutlinesIntroductionSequential MethodsLatches and Flip-FlopsSequential System DesignConclusion


Lecture 6


Dynamic Latch (1/3)Pass Transistor LatchPros

TinyLow clock load

ConsVt dropLeakage awayBackdrivingDiffusion input

D Q

Used in 1970s

D Q

Transmission gateNo Vt dropLeakage awayBackdrivingDiffusion inputRequires inverted clock


Lecture 6


Dynamic Latch (2/3)Store charge on inverter gate capacitance:

= 0: transmission gate is off, inverter output is determined by storage node. = 1: transmission gate is on, inverter output follows D input.


Lecture 6


Dynamic Latch (3/3)

Inverting bufferNo Vt dropLeakage awayNo backdrivingFixes either

Diffusion input (upper side)Output noise sensitivity with inverted output (bottom side)

Setup and hold times determined by transmission gate must ensure that value stored on transmission gate is solid.


Lecture 6


Stick Diagram

VDD

QD

VSS


Lecture 6


Physical Layout

VDD

D Q

VSS


Lecture 6


Multiplexer Dynamic Latch


Lecture 6


Static Latch (1/3)Must use feedback to restore value.Some latches are static on one phase (pseudo-static) load on one phase, activate feedback on other phase.

SR Latch


Lecture 6


Static Latch (2/3)Tristate feedback

No Vt dropLeakage compensationBackdriving riskDiffusion inputNon-isolated from output noiseRequires inverted clock

Buffered inputNo Vt dropLeakage compensationNo backdrivingNo diffusion inputNon-isolated from output noiseRequires inverted clock

QD X

QD X


Lecture 6


Static Latch (3/3)

Buffered outputNo Vt dropLeakage compensationNo backdrivingNo diffusion inputIsolated from output noiseRequires inverted clock

Widely used in Artisan standard cells

Very robust (most important)Rather largeRather slow (1.5 2 FO4 delays)High clock loading

Q

D X


Lecture 6


Multiplexer Static Latches

Negative Latch

Mux Static LatchNo Vt dropLeakage compensationNo backdrivingNo diffusion inputRequires inverted clock

Positive Latch


Lecture 6


Recirculating Quasi-Static LatchEliminate the problem: the value stored on the capacitor leaks away over time on dynamic latchQuasi-static: the latch data will vanish if the clocks are ceased. (i.e. static on one phase)


Lecture 6


Clocked Inverter

= 0: If both clocked transistors are off, output is floating. = 1: If both clocked inverters are on, acts as an inverter to drive output.

symbol

circuit


Lecture 6


Clocked Inverter Latch

= 0: i1 is off, i2-i3 form feedback circuit. = 1: i2 is off, breaking feedback; i1 is on, driving i3 and output.Static Latch is transparent when = 1.


Lecture 6


Flip-FlopsNot transparentuse multiple storage elements to isolate output from input.Edge-Trigger:

master-slave


Lecture 6


Master-Slave Flip-Flop

D Q

master slave

= 0: master latch is disabled; slave latch is enabled, but master latch output is stable, so pop the output of the master. = 1: master latch is enabled, loading value from input; slave latch is disabled, maintaining old output value.


Lecture 6


Latch-Based Flip-FlopThe storage nodes have to be refreshed at periodic intervals


Lecture 6


Resettable Latches and Flip-Flop


Lecture 6


Static Latch-Based Flip-Flop: Clock Skew Problem

D-Latch D-Latch

The 1-1 clock overlap introduces a race condition.During the 1-1 overlap, node A is driven by both D and B.


Lecture 6


OutlinesIntroductionSequencing MethodsLatches and Flip-FlopsSequential System DesignConclusion


Lecture 6


Sequential Machine Design Procedure

Step1: SpecificationStep2: Formulation

Obtain a state diagram or state tableStep3: State Assignment

Obtain state table if only a state diagram is available previously and assign binary codes to the states

Step4: Flip-Flop Input Equation Determination Select flip-flop types and derive flip-flop equations from next state entries in the table

Step5: Output Equation Determination Derive output equations from output entries in the table

Step6: Optimization Optimize the equations

Step7: Technology Mapping Find circuit from equations and map to flip-flops and gate

Step8: Verification Verify correctness of final design


Lecture 6


State Transition Graphs/TablesBasic functional description of FSM.Symbolic truth table for next-state, output functions:

no structure of logic;no encoding of states.

State transition graph and table are functionally equivalent.


Lecture 6


State AssignmentMust find binary encoding for symbolic states state assignment.State assignment affects:

combinational logic area;combinational logic delay;memory element area.

May also encode some machine inputs/outputs.


Lecture 6


Example: One-bit Counter (1/4)Easy to specify as one-bit counter.Harder to specify n-bit counter behavior.Can specify n-bit counter as structure made of 1-bit counters.State table:

Count Cin Next Count Cout (Carry Out)

0 0 0 00 1 1 01 0 1 01 1 0 1


Lecture 6


One-bit Counter Implementation (2/4)

XOR computes next value of this bit of counter.NAND/inverter computes carry-out.


Lecture 6


One-bit Counter Sticks Diagram (3/4)

l1(latch) n(NAND) i(INV) x(XOR) l2(latch)

Cin

Cout

VDD

VSS

1 1 2 2


Lecture 6


n-bit Counter Structure (4/4)


Lecture 6


Example: 01 String Recognizer (1/5)

Behavior of machine which recognizes 01 in continuous stream of bits.Operation:

Waits for 0 to appear in state bit1.Goes into separate state bit2 when 0 appears.If 1 appears immediately after 0, cant have a 01 on next cycle, so can go back to wait for 0 in state bit1.

Time 0 1 2 3 4 5

Input 0 0 1 1 0 1

State Bit1 Bit2 Bit2 Bit1 Bit1 Bit2

Next Bit2 Bit2 Bit1 Bit1 Bit2 Bit1

Output 0 0 1 0 0 1


Lecture 6


State Transition Table (2/5)Operation:

Waits for 0 to appear in state bit1.Goes into separate state bit2 when 0 appears.If 1 appears immediately after 0, cant have a 01 on next cycle, so can go back to wait for 0 in state bit1.

Input Present Next Output

0 Bit1 Bit2 0

1 Bit1 Bit1 0

0 Bit2 Bit2 0

1 Bit2 Bit1 1


Lecture 6


State Transition Graph (3/5)Equivalent to state transition table:


Lecture 6


01 Recognizer Encoding (4/5)Choose bit1=0, bit2=1, and then truth table is as follows:

Input Present Next Output

0 0 1 0

1 0 0 0

0 1 1 0

1 1 0 1


Lecture 6


01 Recognizer Logic Implementation (5/5)

After encoding, truth table can be implemented in gates:

DQ

DQ


Lecture 6


Power Optimization

Memory elements stop glitch propagation:

Glitch


Lecture 6


Conclusions

You should learn in depth about the following topics:

LatchFlip-FlopSequencing Sequential CircuitsSequential system clock discipline

Sequential Circuit DesignOutlinesSequential MachinesFSM StructureSequencing ElementsMemory ElementsMemory CategoriesSetup & Hold TimesSequencing MethodsTiming DiagramsMax-Delay: Flip-FlopsMax-Delay Example (1/2)Max-Delay Example (2/2)Max Delay: 2-Phase LatchesMax Delay: Pulsed LatchesMax-Delay ExampleMin-Delay: Flip-FlopsMin-Delay ExampleMin-Delay: 2-Phase LatchesMin-Delay: Pulsed LatchesTime BorrowingTime Borrowing ExampleHow Much Borrowing?Clock SkewClock Skew: Flip-FlopsClock Skew: LatchesTwo-Phase ClockingSignal SkewData Shoot ThroughUnbalanced DelaysRetiming SolutionSummaryOutlinesDynamic Latch (1/3)Dynamic Latch (2/3)Dynamic Latch (3/3)Stick DiagramPhysical LayoutMultiplexer Dynamic LatchStatic Latch (1/3)Static Latch (2/3)Static Latch (3/3)Multiplexer Static LatchesRecirculating Quasi-Static LatchClocked InverterClocked Inverter LatchFlip-FlopsMaster-Slave Flip-FlopLatch-Based Flip-FlopResettable Latches and Flip-FlopStatic Latch-Based Flip-Flop: Clock Skew ProblemOutlinesSequential Machine Design ProcedureState Transition Graphs/TablesState AssignmentExample: One-bit Counter (1/4)One-bit Counter Implementation (2/4)One-bit Counter Sticks Diagram (3/4)n-bit Counter Structure (4/4)Example: 01 String Recognizer (1/5)State Transition Table (2/5)State Transition Graph (3/5)01 Recognizer Encoding (4/5)01 Recognizer Logic Implementation (5/5)Power OptimizationConclusions

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