삼성전자㈜ Memory-EDS팀¹€규열.pdf · 2014-10-20 ·...
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2014.10.15/삼성전자/김규열 책임 삼성전자㈜ Memory-EDS팀 ‘14. 10. 15 2014 TEST TECHNOLOGY WORKSHOP “Future IC Test Challenges”
Transcript of 삼성전자㈜ Memory-EDS팀¹€규열.pdf · 2014-10-20 ·...
2014.10.15/삼성전자/김규열 책임
삼성전자㈜ Memory-EDS팀
‘14. 10. 15
2014TEST TECHNOLOGYWORKSHOP
“Future IC Test Challenges”
2014.10.15/삼성전자/김규열 책임
Contents
Ⅰ. Trend of Market, ATE, Probe Card
Ⅱ. PI Consideration on ATE
Ⅲ. SI Considerations on ATE
Ⅳ. Summary
2014.10.15/삼성전자/김규열 책임- 2/18 -
13년약24억불
13년약12.3억불
반도체 P/Card 시장 점유율
반도체 ATE 시장 점유율
Ⅰ. Trend of Market, ATE, Probe Card
[Source:VLSI Research]
ME
LSI횡보
감소
1) Industry Trend[억달러]
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[Source:ITRS] [Source:ITRS]
2) Probe Card and Device Trend
Ⅰ. Trend of Market, ATE, Probe Card
2014.10.15/삼성전자/김규열 책임- 4/18 -
항목 ATE-A ATE-B ATE-C ATE-D
PCB 330mm 440mm 480mm 520mm
Parallel 32 64 64 96
Speed 71MHz 144MHz 266MHz 400MHz
OTA ±800ps ±400ps ±300ps ±300ps
Ch/DUT 52 58 60 64
Total Ch. 1664 3712 3840 6144
PPS128 256 256 768
0.8A 0.8A 0.8A 1.2A
TPD Serial Serial Parallel Parallel
Util. Power 25A 25A 25A 60A
I/F Pogo ZIF ZIF ZIF※. PPS (Programmable Power Supply), TPD(Time of Propagation Delay), ZIF(Zero Insertion Force)
3) ATE Trend
Ⅰ. Trend of Market, ATE, Probe Card
2014.10.15/삼성전자/김규열 책임- 5/18 -
On-chip capLower currentLesser Active cells
More de-capsLower ImpedanceMore P/G pinsHigh CCC Probes
High CurrentMore PPS Number
Lower Impedance
Ⅱ. PI Consideration on ATE
1) Power Integrity of Wafer Test
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Ⅱ. PI Consideration on ATE
2014.10.15/삼성전자/김규열 책임- 7/18 -
2) Case Study : PI of ATE
Ⅱ. PI Consideration on ATE
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1) Transmission Lines
dTZ ,0
Ⅲ. SI Consideration on ATE
2014.10.15/삼성전자/김규열 책임- 9/18 -
Dr
Dr
Dr
TPD CAL보정
2) Calibration-①
Ⅲ. SI Consideration on ATE
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ATE Internal Timing Error
DRpin set DRpin reset IOpin set IOpin reset
0.2V 822 878 705 823
0.4V 807 810 703 761
0.7V 727 723 649 683
1.0V 630 622 578 592
2.0V 303 299 284 289
3.0V 0 0 0 0
5.0V -575 -566 -539 -549
8.0V -1471 -1444 -1266 -1384
Driver Linearity
2) Calibration-②
Ⅲ. SI Consideration on ATE
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-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
7.00 8.00 9.00 10.00 11.00 12.00 13.00
[V]
[ns]-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
7.00 8.00 9.00 10.00 11.00 12.00 13.00
[V]
[ns]
2) Calibration-③
Ⅲ. SI Consideration on ATE
2014.10.15/삼성전자/김규열 책임- 12/18 -
Trace length：ｔｐｄＡ
(Max length)
Trace length：ｔｐｄＢ
(Min length)
MT6121 MT6532
Trace length：ｔｐｄC
(Max length)
Trace length：ｔｐｄD
(Min length)Length Control Length Non-Control
ZIF Connector
Probe Card
Contact for ProbingDEVICE
Full lengths adjustments of the Probe Card is necessary.
ｔｐｄ：２.３ｎｓ±０.８ｎｓ ｔｐｄ：０.０～６.０ｎｓ
Lengths adjustments of the Probe Card is unnecessary. ※The common pin becomes the exception for non-measurement. ※The characteristic of the waveform must consider.
3) TPD Compensation Capability
TPD Deviation, < 2.0ns TPD Deviation, < 6.0ns
Ⅲ. SI Consideration on ATE
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~ 20 min < 5 sec
4) TPD Measurement-①
Serial TPD Measure Parallel TPD Measure
Ⅲ. SI Consideration on ATE
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WMB P/C
WMB P/C
ATE-A
ATE-B
TPD Measure & Compensation Method !!!
4) TPD Measurement-②
Ⅲ. SI Consideration on ATE
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5) TDR Shmoo & TDR_Test
for ( STRB Timing )for ( VOH Level )
TDR_Test(strb, voh)
Ⅲ. SI Consideration on ATE
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6) Defect detection using TDR_Test-①
TDR_Test(63ns, 1.0V)
TDR_Test(74ns, 1.0V)
TDR_Test(65ns, 2.0V) TDR_Test(65ns, 1.7V)
Ⅲ. SI Consideration on ATE
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DRV1
DRV2
DRV3
DRV4
DUT.1
DUT.3
DUT.5
DUT.2
DUT.4
DUT.6
Twin Driver
6) Defect detection using TDR_Test-②
Ⅲ. SI Consideration on ATE
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Impedance of PPS
TPD
- Compensation Capability
- Measure Method (Serial vs. Parallel)
- Measure Condition between ATE Models
- TDR Shmoo & TDR Test
Ⅳ. Summary
2014.10.15/삼성전자/김규열 책임2014 TEST TECHNOLOGY WORKSHOP
