ANALOG VLSI LAB 2 REPORT

PRIYANKA NAIDU

EHTESHMAM SHAREEF

02/24/2015

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LAB 2

DESIGN OF COMMON SOURCE AMPLIFIER AND BW ESTIMATION

AIM:

Design the common source amplifier of Fig. 1 in 0.18μm for CL=10pF and Rsource=5kΩ and AV=-10 V/V, BWmin=20MHz and perform transient simulations to calculate distortion for sinusoidal input signals with frequencies 20kHz, 200KHz and 2MHz and amplitudes Ap with values Vinmax/10, Vinmax/20, Vinmax/100

.TOOL USED: Cadence

CIRCUIT:

Fig: Common Source Amplifier

PROCDURE:

A Common Source amplifier circuit is made by calculating the sub-elements. Firstly, the load resistor RL value is calculated. This assumes the BW is determined solely by the output pole Overdesign by 30% according to RL=0.7/(2π*BW*CL). Then Quiescent current IDQ is calculated in order to maximize output swing assuming the value of quiescent voltage of drain to

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source is 0.15<VDSQ<0.3. Now calculating gm by using gain formula, Av= -gm*RL which neglects ro, for this reason we overdesign gain by 30% and assume AV≈-1.3gmRL. Then VDSsat, transistor’s size W/L and ro are calculated using required design formulas. The parasitic capacitances which includes CGD, CDB, and CGS are then calculated and from which we get CIN & COUT. Then the DC transfer characteristics VOUT vs VIN of the CMOS common source amplifier is plotted and a biasing voltage VGSQ that allows maximum symmetrical output swing is selected. An AC analysis is plotted using the selected value for VGSQ. The low frequency gain Av and the 3dB frequency (BW) of the amplifier are determined. These values are estimated from Av=-gmRL||ro and with the 3dB frequency obtained from the open circuits time constant's method are compared. Later we determine the maximum signal amplitude |Vin| according to the small signl approximation by using |Vin|max<<2(VGSQ-VT) for the selected VGSQ. Then Perform transient simulations to calculate distortion for sinusoidal input signals with frequencies 20kHz, 200KHz and 2MHz and amplitudes Ap with values Vinmax, Vinmax/2, Vinmax/10 are performed.

DESIGN:

Using the following procedure, we get the values as

RL ≈1/(2πCL BW) = 0.557kohms

IDQL=(VDD-VDSQ)/2RL = 1.43mA

AV≈-1.3gmRL

gm=23.33m

VDSSat =2IDQ/( gm)VDSsat=0.122v

(W/L) = IDQ/((μCox/2) VDSsat2) = 640.50

Where we take L=0.4um,we getW=256.2um

ro=1/(λIDQ) = 8.74kohms

AV=-gmRL||ro = 12.21

Cin=Cgs+Cgd(1+|A|) = 2.19pf

Cout=CL+Cdb+ Cgd(1+1/|A|) = 10.36pf

BW≈1/(RsourceCin+RL||roCout) = 11.8MHZ, 16.7MHZ (Neglecting CL)

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|Vin|max<<2(VGSQ-VT)

Apdistortion = Ap/4(VGSQ-VT)

Distortion(%) = [Ap/4(VGSQ-VT)]*100

SIMULATION RESULTS:

SCHEMATIC DIAGRAM

Fig2: Common Source Amplifier Circuit(DC Circuit)

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Fig3: Common Source Amplifier Circuit(AC Circuit)

Fig4: DC Analysis

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Fig6: AC Analysis

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Fig7: AC Analysis with no load

Fig8.1: Transient Analysis

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Fig8.2: Transient Analysis

Fig8.3: Transient Analysis

RESULT TABLE:Table shows different theoretical & practical values for the Design

Gain Bandwidth Gain-Bandwidth product

With CL Without CL

With CL Without CL

With CL

Without CL

Theoretical calculation

12.21 11.8MHz 16.7MHz

Practical calculation

11.69MHz 15.34MHz

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The table below shows various distortion values in percentage for varying frequencies

Frequencies 2MHz 20MHz 200MHz

Vinmax/10 1.826% 1.954% 2.01%

Vinmax/20 0.947% 0.994% 1.033%

Vinmax/100 0.4% 0.41% 0.4%

DISCUSSION:

Designed the common source amplifier for the given configurations and determined the distortion in the outputs by varying the frequency of Analog signals given as input. We have also observed variations in gain & bandwidth practical values and theoretical values.

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