Introduction of FPGA

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Transcript of Introduction of FPGA

  • === ===

  • FPGALinuxAndroidAndroidBOTImaocande

    @imaocaimaoca@gmail.com

  • Agenda FPGA Overview FPGA Design Flow HDL(Hardware Definiton Language) IP(intelligent property) FPGA Design environment Demonstrations (altera CPLD MAX II)

  • ASIC

    ASIC(application specific integrated circuit) 1

  • FPGA

    FPGA(field-programmable gate array)

    PLD

  • ASSP ASIC FPGA

    CPU+SW

    ASSP(Application Specific Standard Product)

  • FPGA design flow

  • Schematic Entry

    HDL(Hardware Definiton Language)-VHDL

    -VerilogHDL

    FPGA Design Entry

  • Schematic Entry

  • VHDL

    VHDL[1] EDA FPGA ASIC IEEE 1076-2008 http://ja.wikipedia.org/wiki/VHDL

  • Verilog

    http://ja.wikipedia.org/wiki/Verilog#Verilog_2005

  • Verilog-HDL Code example

    module add(input A,B,Cin,output S,Cout );assign t = A^B;assign S = t^Cin;assign Cout = (t&Cin)|(A&B);

    endmodule

  • add0A0B0

    S0

    add1A1B1

    S1

    add2A2B2

    S2

    add3A3B3

    S3

    Cout

    Cout

    Cout

    module add4(input A0,A1,A2,A3,B0,B1,B2,B4, output S0,S1,S2,S3,C3);add add0(A0,B0,0,S0,C0);add add1(A1,B1,C0,S1,C1);add add2(A2,A2,C1,S2,C2);add add3(A3,A3,C2,S3,C3);

    endmodule

    4bit full addermodule add(input A,B,Cin,output S,Cout );

    assign t = A^B;assign S = t^Cin;assign Cout = (t&Cin)|(A&B);

    endmodule

    module add4(input [3:0]A,input [3:0]B,output[4:0]S);

    assign S = A+B;endmodule

  • FPGA vs CPLDFPGA CPLD

    CPU Ethernet Cntroller

  • LCD!!CPLD

    http://ascii.jp/elem/000/000/308/308293/

    () 2000124 CPLD(Complex Programmable Logic Device)CoolRunner XPLA3(eXtended Programmable Logic Array)

  • Ulrich Radig have developed simple CPLD VGA graphics board which is able to generate 256256 64 color graphics on standard 640480 with 60 Hz monitor. He used a CPLD XC9572PC84 from Xilink which is clocked with 32mHz crystal.

    http://www.embedds.com/cpld-8-bit-vga-graphics/

    CPLD Examples byEmbedded projects from around the web

  • http://www.64hdd.com/projects/hardware/c64-cpld.html

    Commodore C64 Projects

  • 1 MSX1chipMSX MSX2FPGA(Field Programmable Gate Array)MSX2MSX

  • http://www.youtube.com/watch?v=Gx-QNfjYg5Q

    FPGA1MSX

  • Maker movement

  • IP(intelligent property)

    1990LSI

    IPLSIIPLSIIP

    IP: intellectual property coreLSIIPASIC

  • FPGA VenderIP

    CPUDSPCPU DMA SRAMDRAMI/F UARTSPIICUSBATMJTAGI/F PCIPCI ExpressAHB I/FI/F FFT/ AESDESRSARC5SHA1MD5SSL CODECJPEGCODEC MPEG CODECMP3AAC-lawA-law

  • Altera Quartus II MegaWizard Plug-In Manager

  • http://www.altera.co.jp/products/ip/ipm-index.html

  • 1 IBM and others - PowerPC 123322 Sun Microsystems and others - OpenSPARC 44413 Xilinx 8504 ARM 7405 Rambus 4036 TSMC 3997 Altera 3898 Cadence Design Systems 3319 On2 Technologies 28610 MIPS Technologies - MIPS 220

    http://top-topics.thefullwiki.org/Top_semiconductor_IP_core_vendors:_All

    Top semiconductor IP core vendors: All Rank Topic Wikipedia views Oct 21 2010

  • FPGA Design Environment

    Design Tool Altera Quartus2 Web Editionhttps://www.altera.com/download/software/quartus-ii-we/ja

    ProgrammerUSB Blasterhttp://www.hdl.co.jp/ACC/TB1/index.html

  • Demonstrations (altera CPLD MAX II)

    http://optimize.ath.cx/max2/index.html

    module rc_counter(output OUT1,output OUT2);reg [19:0] counter;assign OUT1 = counter[19];assign OUT2 = osc;assign oscen=1;rc_osc rc_osc(oscen,osc); // use IP corealways @(posedge osc) counter[19:0] = counter[19:0]

    + 1;endmodule

  • SupplementationDebug or Simulation

    How to use logic AnalyzerVerilog porgramming

    Consept of State machineTrend

    Xilinx ZynqAltera Arria V SoC FPGA, Cyclone V SoC FPGA

  • Thank you.

    Do you have any questions?