Instruction Classification and Instruction Classification and Addressing ModeAddressing Mode

计算机学院 李征计算机学院 李征TelTel ：： 1388215376513882153765

EmailEmail ：： lizheng@cs.scu.edu.cnlizheng@cs.scu.edu.cnOICQ: 1340915OICQ: 1340915

Assembler and Machine InstructionAssembler and Machine Instruction

In principle, assembler instruction In principle, assembler instruction correspond with machine instruction one correspond with machine instruction one by one.by one.

However, there are few exceptions.However, there are few exceptions.

Because it is easy to remember, Because it is easy to remember, programmer only learn assembler programmer only learn assembler instructions.instructions.

Assembler and Machine InstructionAssembler and Machine Instruction

The syntax restriction in assembler The syntax restriction in assembler instructions are introduced from instructions are introduced from corresponding machine instructions.corresponding machine instructions.

These These syntax restrictions is decided by syntax restrictions is decided by CPU architectureCPU architecture..

Instruction CompositionInstruction Composition

OPR DEST, SRCOPR DEST, SRC

OPR: Operation Code to present instruction OPR: Operation Code to present instruction functionfunction

SRC: Source data for operationSRC: Source data for operation

DEST: Destination address for operation result, DEST: Destination address for operation result, maybe provide source data toomaybe provide source data too

Instruction Classification (1)Instruction Classification (1)

1) Instruction with two operation data1) Instruction with two operation data

OPR DEST, SRCOPR DEST, SRC

DEST can be register, memory cellDEST can be register, memory cell

SRC can be register, memory cell, SRC can be register, memory cell, immediate data (immediate data ( 立即数立即数 ))

1) Instruction with two operation 1) Instruction with two operation datadata

DEST and SRC can be 8-bit or 16-bit. DEST and SRC can be 8-bit or 16-bit.

The length of DEST and SRC must be The length of DEST and SRC must be consistent.consistent.

Only one memory cell can appear at Only one memory cell can appear at DEST or SRC.DEST or SRC.

1) Instruction with two operation 1) Instruction with two operation datadata

Example:Example:MOV AX, BX ;1 SRC, 1 DESTMOV AX, BX ;1 SRC, 1 DESTMOV VAR1, BLMOV VAR1, BLMOV AL, 08HMOV AL, 08HADD AL, BL ;2 SRC, 1 DESTADD AL, BL ;2 SRC, 1 DEST

Error Usage:Error Usage:MOV 32H, ALMOV 32H, ALMOV AL, 9A4BHMOV AL, 9A4BHMOV VAR1, VAR2MOV VAR1, VAR2

Instruction Classification (1)Instruction Classification (1)

2) Instruction with one operation data2) Instruction with one operation data

OPR DESTOPR DESTActually, one or two data are both possible.Actually, one or two data are both possible.

DEST can be register or memory cell, 8-bit or DEST can be register or memory cell, 8-bit or 16-bit16-bit

Note: Immediate data can not used in Note: Immediate data can not used in instructions with one data.instructions with one data.

2) Instruction with one operation 2) Instruction with one operation datadata

Examples:Examples:

NEG AX ; 1 SRC, 1 DESTNEG AX ; 1 SRC, 1 DEST

PUSH AX ; 1 SRC, 1 implied DESTPUSH AX ; 1 SRC, 1 implied DEST

Error Usage:Error Usage:

PUSH 2A45HPUSH 2A45H

Instruction Classification (1)Instruction Classification (1)

3) Instruction with no operation data3) Instruction with no operation data

OPROPR

Actually, one or two data are possible too.Actually, one or two data are possible too.

3) Instruction with no operation 3) Instruction with no operation datadata

Example:Example:

NOP ; No SRC and DESTNOP ; No SRC and DEST

CLC ; 1 implied DESTCLC ; 1 implied DEST

POPF ; 1 implied SRC, 1 implied DESTPOPF ; 1 implied SRC, 1 implied DEST

Instruction Classification (2)Instruction Classification (2)

1) Transfer instruction1) Transfer instruction

2) Arithmetic instruction2) Arithmetic instruction

3) Bit Manipulation instruction3) Bit Manipulation instruction

4) String instruction4) String instruction

5) Program transfer instruction5) Program transfer instruction

6) Processor control instruction6) Processor control instruction

Addressing ModeAddressing Mode

Addressing mode means how CPU obtain Addressing mode means how CPU obtain the operation data in instructions.the operation data in instructions.

(1) Register Addressing(1) Register Addressing(2) Immediate Addressing(2) Immediate Addressing(3) Memory Addressing(3) Memory Addressing(4) String Addressing(4) String Addressing(5) I/O Port Addressing(5) I/O Port Addressing

Addressing ModeAddressing Mode

Addressing Mode is a concept for operation Addressing Mode is a concept for operation data, not for instruction.data, not for instruction.

If there are two operation data in an instruction, If there are two operation data in an instruction, there may be two different addressing modes.there may be two different addressing modes.

Example: MOV AX, VAR1Example: MOV AX, VAR1

DEST: Register Addressing DEST: Register Addressing

SRC: Memory AddressingSRC: Memory Addressing

(1) Register Addressing(1) Register Addressing

If operation data is in CPU register, the If operation data is in CPU register, the addressing mode is register addressing.addressing mode is register addressing.

Example:Example:

mov al, blmov al, bl

DEST: Register addressingDEST: Register addressing

SRC: Register addressingSRC: Register addressing

(1) Register Addressing(1) Register Addressing

Because no bus operation needed in Because no bus operation needed in register addressing, it is the fastest register addressing, it is the fastest addressing mode of CPU.addressing mode of CPU.

(2) Immediate Addressing(2) Immediate Addressing

If the operation data is immediate data in If the operation data is immediate data in instructions, the addressing mode is instructions, the addressing mode is immediate addressing.immediate addressing.

Example:Example:

mov al, 02hmov al, 02h

DEST: Register AddressingDEST: Register Addressing

SRC: Immediate AddressingSRC: Immediate Addressing

(2) Immediate Addressing(2) Immediate Addressing

Because immediate data is part of instruction, it Because immediate data is part of instruction, it will be loaded to instruction queue in instruction will be loaded to instruction queue in instruction reading cycle (not execution cycle).reading cycle (not execution cycle).

Bus operation is needed for reading data.Bus operation is needed for reading data.

However, because EU and BIU can work However, because EU and BIU can work synchronously, synchronously, the time consumed in the time consumed in immediate data reading can be ignored in immediate data reading can be ignored in some situationssome situations..

Memory AddressingMemory Addressing

When operation data is in memory, the When operation data is in memory, the addressing mode is memory addressing.addressing mode is memory addressing.

Bus operation is neededBus operation is needed in this addressing in this addressing mode, and memory mode, and memory Addressing must be Addressing must be executed in execution cycleexecuted in execution cycle of instruction. of instruction.

Then, memory addressing is less effective than Then, memory addressing is less effective than register or immediate addressing.register or immediate addressing.

Memory AddressingMemory Addressing

Memory logic address is composed of Memory logic address is composed of segment base valuesegment base value and and offset offset (effective address)(effective address)..

There are There are five different memory five different memory addressing modesaddressing modes, and they have , and they have different offset (EA) composingdifferent offset (EA) composing..

Components of EAComponents of EA

There are three different components which can There are three different components which can be combined to EA.be combined to EA.

DISP (Disparity, DISP (Disparity, 位移量位移量 ): EA components ): EA components provided by machine instructionprovided by machine instruction

Base Component (Base Component ( 基址分量基址分量 ): Provided by BX ): Provided by BX or BP registeror BP register

Index Component (Index Component ( 变址分量变址分量 ): Provided by SI or ): Provided by SI or DI registerDI register

Memory AddressingMemory Addressing

Different combination mode of these three Different combination mode of these three components forms different memory addressing.components forms different memory addressing.

1) Direct Addressing (1) Direct Addressing ( 直接寻址直接寻址 ))

2) Register Indirect Addressing (2) Register Indirect Addressing ( 寄存器间接寻寄存器间接寻址址 ))

3) Based Addressing (3) Based Addressing ( 基址寻址基址寻址 ))

4) Indexed Addressing (4) Indexed Addressing ( 变址寻址变址寻址 ))

5) Based Indexed Addressing (5) Based Indexed Addressing ( 基址变址寻址基址变址寻址 ))

1) Direct Addressing1) Direct Addressing

If EA is composed of DISP only, it is direct If EA is composed of DISP only, it is direct addressing.addressing.

EA = DISPEA = DISP

DISP may be data form or symbol form in DISP may be data form or symbol form in assembler language.assembler language.

1) Direct Addressing1) Direct Addressing

Example:Example:

MOV BX, [1000H]MOV BX, [1000H]

; implied DS for segment information; implied DS for segment information

MOV BX, DS:[1000H]MOV BX, DS:[1000H]

MOV BX, ES:[0100H]MOV BX, ES:[0100H]

1) Direct Addressing1) Direct Addressing

Example:Example:MOV BX, VAR1MOV BX, VAR1; VAR1 is a symbol disparity.; VAR1 is a symbol disparity.

MOV AL, DA1+3MOV AL, DA1+3; DA1 is a symbol disparity.; DA1 is a symbol disparity.

Symbol disparity will be replaced as data form Symbol disparity will be replaced as data form by assembler (by assembler ( 汇编程序汇编程序 ).).

1) Direct Addressing1) Direct Addressing

False usage:False usage:

MOV [0100H], 04HMOV [0100H], 04H

; 16-bit or 8-bit? It is a syntax error.; 16-bit or 8-bit? It is a syntax error.

Correct one:Correct one:

MOV BYTE PTR [0100H], 04HMOV BYTE PTR [0100H], 04H

2) Register Indirect Addressing2) Register Indirect Addressing

If EA is provided by one register entirely, it If EA is provided by one register entirely, it is register indirect addressing.is register indirect addressing.

EA = EA = （（ BXBX ））EA = EA = （（ BPBP ））EA = EA = （（ SISI ））EA = EA = （（ DIDI ））

2) Register Indirect Addressing2) Register Indirect Addressing

Examples:Examples:MOV AL, [BX]MOV AL, [BX]MOV BYTE PTR [SI], 03HMOV BYTE PTR [SI], 03HADD [DI], BLADD [DI], BL; BX, SI, and DI imply DS; BX, SI, and DI imply DS

MOV [BP], AX ;BP imply SSMOV [BP], AX ;BP imply SSADD DS:[BP], ALADD DS:[BP], AL

3) Based Addressing3) Based Addressing

If EA is composed of If EA is composed of base component base component and DISPand DISP, it is based addressing., it is based addressing.

EA = EA = （（ BXBX ）） + Disp+ Disp

EA = EA = （（ BPBP ）） + Disp+ Disp

4) Indexed Addressing4) Indexed Addressing

If EA is composed of If EA is composed of index component index component and DISPand DISP, it is indexed addressing., it is indexed addressing.

EA = EA = （（ SISI ）） + Disp+ Disp

EA = EA = （（ DIDI ）） + Disp+ Disp

Based Addressing and Indexed Based Addressing and Indexed AddressingAddressing

Example:Example:

MOV AXMOV AX ， ， 10H[SI]10H[SI]

DEST: Register AddressingDEST: Register Addressing

SRC: Indexed Addressing, EA = 10H+(SI), SRC: Indexed Addressing, EA = 10H+(SI), DS is implied.DS is implied.

Based Addressing and Indexed Based Addressing and Indexed AddressingAddressing

Example:Example:

MOV TAB1[BP]MOV TAB1[BP] ， ， CLCL

DEST: Based addressing, EA=TAB1+DEST: Based addressing, EA=TAB1+(BP), and SS is implied.(BP), and SS is implied.

SRC: Register addressingSRC: Register addressing

Based Addressing and Indexed Based Addressing and Indexed AddressingAddressing

Do you remember the 1D array in high-Do you remember the 1D array in high-level language?level language?

BX, BP, SI, DI can be the subscript BX, BP, SI, DI can be the subscript variable when the array is operated.variable when the array is operated.

5) Based Indexed Addressing5) Based Indexed Addressing

If EA is composed of three components, it is If EA is composed of three components, it is based indexed addressing.based indexed addressing.

EA = EA = （（ BXBX ）） ++ （（ SISI ）） + Disp+ DispEA = EA = （（ BXBX ）） ++ （（ DIDI ）） + Disp+ DispEA = EA = （（ BPBP ）） ++ （（ SISI ）） + Disp+ DispEA = EA = （（ BPBP ）） ++ （（ DIDI ）） + Disp+ Disp

BX imply DS, and BP imply SS.BX imply DS, and BP imply SS.

5) Based Indexed Addressing5) Based Indexed Addressing

Example:Example:

MOV AXMOV AX ， ， 200H[BX][SI]200H[BX][SI]

SRC: Based indexed addressing, EA = SRC: Based indexed addressing, EA = 200H+(BX)+(SI), DS is implied.200H+(BX)+(SI), DS is implied.

5) Based Indexed Addressing5) Based Indexed Addressing

Example:Example:

MOV TAB1[BP][DI]MOV TAB1[BP][DI] ， ， DLDL

DEST: Based indexed addressing, EA = TAB1+DEST: Based indexed addressing, EA = TAB1+(BP)+(DI), and SS is implied.(BP)+(DI), and SS is implied.

Do you remember 2D arrays in high-level Do you remember 2D arrays in high-level language?language?How about n-D arrays?How about n-D arrays?

Note in Memory AddressingNote in Memory Addressing

; Are they different?; Are they different?

MOV ALMOV AL ，， [BX] ; not use ALU[BX] ; not use ALU

MOV ALMOV AL ，， 10H[BX] ; ALU used10H[BX] ; ALU used

; Are they different?; Are they different?

MOV ALMOV AL ，， [BX][SI][BX][SI]

MOV ALMOV AL ，， 20H[BX][SI]20H[BX][SI]

(4) String Addressing(4) String Addressing

In string operation instructions, the In string operation instructions, the addressing mode are all string addressing.addressing mode are all string addressing.

No time for string operation now, sorry!No time for string operation now, sorry!

(5) I/O port Addressing(5) I/O port Addressing

When operation data is in I/O port, the When operation data is in I/O port, the addressing mode is I/O port addressing.addressing mode is I/O port addressing.

In 8086/8088, the I/O operation and In 8086/8088, the I/O operation and memory operation are distinguished by memory operation are distinguished by control signal on system bus.control signal on system bus.

So, different instructions used to I/O and So, different instructions used to I/O and memory operation.memory operation.

(5) I/O port Addressing(5) I/O port Addressing

In 8086/8088, only input and output In 8086/8088, only input and output instruction can operate I/O port.instruction can operate I/O port.

All instructions which can operate memory All instructions which can operate memory cell can not operate I/O port.cell can not operate I/O port.

(5) I/O port Addressing(5) I/O port Addressing

Unlike the 20-bit physic address of Unlike the 20-bit physic address of memory cell, the memory cell, the physic address of I/O physic address of I/O port is only 16-bitport is only 16-bit..

When I/O operation occurs, only lower 16 When I/O operation occurs, only lower 16 bits of address bus is valid.bits of address bus is valid.

There is There is no segment managementno segment management in I/O in I/O port space.port space.

(5) I/O port Addressing(5) I/O port Addressing

There are two addressing modes for I/O There are two addressing modes for I/O port addressing.port addressing.

Direct AddressingDirect Addressing: Port address is : Port address is provided by instruction.provided by instruction.

Indirect AddressingIndirect Addressing: Port address is : Port address is provided by DX register.provided by DX register.

(5) I/O port Addressing(5) I/O port Addressing

Example:Example:

IN AL, 60H ; 8-bit operationIN AL, 60H ; 8-bit operation

SRC: Direct I/O port addressing, can only SRC: Direct I/O port addressing, can only provide address as 0~255 (8 bit address)provide address as 0~255 (8 bit address)

OUT 40H, AX ;16-bit operationOUT 40H, AX ;16-bit operation

(5) I/O port Addressing(5) I/O port Addressing

Example:Example:MOV DX, 0FF55HMOV DX, 0FF55HIN AL, DXIN AL, DX

SRC: Indirect I/O port addressing, can SRC: Indirect I/O port addressing, can provide 16-bit port address (0~65535)provide 16-bit port address (0~65535)

64K is the I/O space size in 8086/8088.64K is the I/O space size in 8086/8088.