FPGA 上的人脸检测算法研究
description
Transcript of FPGA 上的人脸检测算法研究
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FPGA2007.06.19
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PCDSP
SOCASIC
FPGA
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SOCIP CoreASIC
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SOCFPGAnew architecture
ASICVideo Port(in &out)Face detection
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Target Board: Xilinx XUP Virtex-II Pro Development System Rev CProcessor: PPC 405 or MicroBlazeProcessor clock frequency: 300.000000 MHzBus clock frequency: 100.000000 MHzBRAM Memory : 16K+ 16K+ 16KDDR_SDRAM_32Mx64 Single Rank = 256 MB
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Performance
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StrategyPPC+
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Original Before Algo-opt After Algo-opt
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ApplicationCase1: Integrated in Digital CameraCase2: Integrated in Mobile PhoneCase3: Intelligent toysCase4: Other portable device based on arm9/PPC405/PPC440/xcale etc.
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New arch for ASICNew Architecture(very good)System C level modelingC Modeling and profilingVerilogHDL Coding
Video port(IP core) Video in (BT656)Video out (VGA)I2C (simplify)
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New ArchitectureHaarN x NN
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Encoder
Scan control
Image RAM
Decoder / Detect Logic
Passed window
Cascade RAM
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SOC(ASSP)Powerpc405+coreConnectNot arm926 + ambaIntegrate Video Port to PLB Bus
ASICA hardware version of the new architectureno processor
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PPC4xx Embedded core and PPC4xx ASSPPPC405/440 ASSP = PPC405/440 + SoCBus(CCB) + Peripherals
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IBM PowerPC Processor CoresHigh-performance hard cores for IBM, Chartered and SamsungFully synthesizable cores for flexibility in fab choice and/or design point
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Feasibilityppc405 core is more powerful than arm926ppc405 core is cheaper than arm926IBM provides design serviceFoundry: IBM/ TSMC/ Chartered/ Samsung
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DEMODEMOvideo 5fps6 students 5 monthsTHANKSTHE END
SUMSUNG S3C44B0X is like the ASSPWhile the ARM740 is like the PPC405/PPC440