スピントロニクス素子と集積回路応用

VDEC設立20周年記念行事東京大学武田先端知ビル、2017年1月20日

大野英男

東北大学電気通信研究所東北大学省エネルギー・スピントロニクス集積化システムセンター

東北大学スピントロニクス学術連携研究教育センター東北大学国際集積エレクトロニクス研究開発センター

東北大学原子分子材料科学高等研究機構

http://www.csis.tohoku.ac.jp/

Tetsuo Endoh, Takahiro Hanyu, Shunsuke Fukami, Shoji Ikeda, Hideo Sato, Shun Kanai, Fumihiro Matsukura and the CSIS team

Work supported in part by the FIRST Program from JSPS, ImPACT from JST,and by the R & D for Next-Generation Information Technology of MEXT

DRAM: dense, 6F2

SRAM: fast, 200F2

Current Working Memories

Volatile

Toward Nonvolatile CMOS VLSI

Logic-in-Memory Architecture by fusion between logic circuits and MTJs （Reduction of device number and interconnect wiring length）

Zero standby power of memory by non-volatile spintronics devices

Low Power Consumption

Low Power, High Performance, Low Cost

Spintronics Logic-in-Memory

VLSIs

Logic VLSIs with Spintronics Memory

Present Logic VLSIs

Logic

Logic

Logic

Volatile memory

Leakage current

Si sub.

Si sub.

Si sub.

Non-volatile memory

Non-volatile memory

Nonvolatile memory that is

scalable fast virtually infinite endurance back-end-of-line compatible low resistance

Two versus Three terminal: operation window

Three-terminal: Different READ and WRITE current pathHigh-speed operation, Simple and small-area peripheral circuits

Wide waveform tolerance owing to the large operation windowLong lifetime Much less stress on tunnel barrierLow error rate No read disturbance, overdrive possible

Three-terminalTwo-terminal

(Magnetic Tunnel Junction)

V

Readmargin

Writemargin

TDDBWriteRead

EM

Writemargin

V

V

Readmargin

TDDBRead

Write

WRITE

READ

WRITE

READ

• TDDB : Time-dependent dielectric breakdown• EM : Electromigration S. Fukami et al. IEEE Trans. Magn. 50, 3401006 (2014).

6‐8 F2 12 F2

2 terminal device

Magnetic Tunnel Junction(Spin‐transfer torque)

perpendicular

E

Parallel Antiparallel

Thermal fluctuationkBT

E

Parallel Antiparallel

Thermal fluctuationkBT E

Parallel Antiparallel

Thermal fluctuationkBT

E

Parallel Antiparallel

Thermal fluctuationkBT

Ic0 and =E/kBT

VKKE ecrystallinshape

02

eff

C effB

eff eff

E K V

eI K Vg

E

K K

Perpendicular MgO-CoFeB MTJ

interface perpendicularanisotropy

JC0 = 3.8 MA/cm2

(IC0 = 48 μA) E/kBT ~ 40TMR ratio = 110%Ta = 350oC

S. Ikeda et al., Nature Mat. 9, 721 (2010)

1.6 nm0.9 nm1.0 nm

Co20Fe60B20

E/kBT

0 10 20 30 40 50 60 70 800

102030405060708090

100

series1series2APL 2012 calculation

E/k

BT

Junction diameter (nm)H. Sato et al., Appl. Phys. Lett. 105, 062403 (2014)

STT-MRAM

H. Koike et al. IMW2016

Qualcomm, GlobalFoundries, TSMC, TDK Headway, Toshiba, Hynix, Avalanche, …TEL, AMAT, CANON-ANELVA, …Tohoku University, IMEC

Switching current versus switching speed

10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1

-400

-200

0

200

400

600

41416182

AP-P

I C (

A)

(s)

P-AP

82D (nm)

61

Thermally activated switching (long current pulse)

N. Ohshima et al., 76th JSAP fall meeting, 14p‐2J‐8.

0C11 IIA

Precessional switching(short current pulse)

Background Write

MTJ

BL /BL

WLPL

CMOSlatch

STT‐MRAM cell

Cell 1

Cell 2

timetcw

Write to CMOS latch

MTJswitch

Data from BLData from CMOS latch

tcw

T. Ohsawa et al., Symp. VLSI Circuits, pp. C110-C111, June 2013. @Endoh Gr. of Tohoku Univ.

Ternary CAM Cell

MTJ devices(Nonvolatile)

Comparisonlogic

one-bitstorage

(Volatile)Comparison

logic

one-bitstorage

(Volatile)

CMOS-based (12T)

Spintronics & CMOS (2T-2MTJ)

Area, Activity and Standby → Low Power

T. Hanyu Group

3 terminal device

Spin‐Orbit Switchingfor SOT‐MRAM

Spin-Orbit Torque (SOT) switching

1. In-plane current Spin accumulation (through SOI)2. Accumulated spin Torque (=Spin Orbit Torque; SOT)3. Torque Magnetization switching

Experiment

0

50

100

0

50

100

0

50

100

0 1 2 3 4 5

0

50

100

Type Y

Switc

hing

pro

babi

lity

PSW

(%)

(a)

p = 100 ns

Type X

N = 20

p = 10 ns

(b)

p = 1 ns

(c)

p = 0.5 ns

(d)

Current density (1011 A/m2)

Type X

Type Y(STT switching)

20 mT

S. Fukami et al., Symp. on VLSI Tech. T06-5 (2016).

SOT switching in Type X (and Type Z) is promising for GHz-class operation.

-40 -30 -20 -10 0 10 20 30 40

ICH (mA)

RH

0.2

(Co/Ni)/(Pt/Mn) SOT Device

Change in RH varies gradually with IMAX.= Magnetization state can be controlled in an analogue manner by the ICH.

-40 -30 -20 -10 0 10 20 30 40

ICH (mA)

RH

0.2

-40 -30 -20 -10 0 10 20 30 40

ICH (mA)

IMAX (mA) 8 12 16 20 24 28 32 36 40 44

START END

END START

tPtMn = 8 nm (biased)H = 0

… Function of synapse Neuromorphic computing (AI)S. Fukami et al., Nature Mater. 15, 535 (2016).

Recovery of direction cosine confirmed. Difference from ideal value is due to variation of

dynamic range

First Auto Design Tool for

Spintronics CMOS (2011）

Nonvolatile FPGAwith TSV

(First 3D Spintronics CMOS Processor)（VLSI 2012）

600MHzMTJ/CMOS Latch

(Fastest nonvolatile latch)(IEDM 2011）

Nonvolatile TCAM(Most compact TCAM

cell, 4T-2MTJ) （VLSI 2011）

1.5nsec / 1Mbit Embedded MRAM(Fastest nonvolatile

1Mbit memory)（VLSI 2013）

Nonvolatile GPU(Largest Scale

Spintronics Random Logic 500kgate/chip)（ISSCC 2013）

1Mb Array Three Terminal DW Cell(High endurance)

(VLSI 2012)

Nonvolatile microcomputer(First nonvolatile microcomputer)（ISSCC 2014）

Non-volatile CMOS VLSIs with spintronics

On 300 mm wafers

Development framework for spintronics devices

Center for Spintronics Integrated Systems (CSIS)

(Director : Hideo Ohno)

Center for Innovative Integrated Electronic Systems

(CIES)(Director : Tetsuo Endoh)

Development of spintronics materials, devices and integration technologies

using 300 mm-wafer process tools

Development of key technologies for spintronics materials and devices

using 3in process tools

Tohoku University

+

Paradigm Shift by Spintronics

Cache Memory

Storage capacity Low power

High Speed High power