1

Electronic System Level (ESL) Electronic System Level (ESL) DesignDesign을을 이용한이용한 SoCSoC 구조설계구조설계

2008. 10

이준환이준환 ((joonhwan.yi@kw.ac.krjoonhwan.yi@kw.ac.kr))

내용내용

ESL design ESL design 소개소개

ESL design ESL design 적용적용 예예

요약요약

2

내용내용

ESL design ESL design 소개소개

BackgroundBackground

Electronic system level (ESL) design Electronic system level (ESL) design 소개소개

ESL design tasksESL design tasks

ESL design ESL design 적용적용 예예

요약요약요약요약

Background

3

Design Productivity GapDesign Productivity Gap

1,000,000

10,000,000

10,000,000

100,000,000Logic Tr./ChipT /St ff M th

10,000

1,000Chi

p(M

)

10,000

100,000

.

1

10

100

1,000

10,000

100,000

10

100

1,000

10,000

100,000

1,000,000Tr./Staff Month.

xxxx

xx

x21%/Yr. compound

Productivity growth rate

x

58%/Yr. compoundedComplexity growth rate

100

10

1

0.1

0.01

0.001

Logi

c Tr

ansi

stor

per

C

0.01

0.1

1

10

100

1,000

Prod

uctiv

ity(K

) Tra

ns./S

taff

-Mo

Com

plex

ity

1

2003

1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2005

2007

2009

10

Source: Sematech, ITRS (international technology roadmap for semiconductor)

Complexity outpaces design productivity

Demands for Complex DesignsDemands for Complex Designs

고성능 설계 요구Example: Data transfer rate for communication standards

2G (GSM/GPRS/EDGE/CDMA2000 1x) 100 Kbps

다기능 설계 요구Example: Mobile convergence

( ) p3G (WCDMA/CDMA2000 1x EV-DO ~ 3 Mbps

Beyond 3G (HSPA/WiBro/LTE) 10 ~ 200 Mbps4G 100 Mbps ~ 1 Gbps

10,000 x

Example: Mobile convergenceVoice + broadcasting + entertainment + camera + security + etc.

저전력 설계 요구On-chip communications/computations consume less power than off-chip ones

4

Architecture MattersArchitecture Matters

Complex design means more functionality, more data Complex design means more functionality, more data movement, more computation on movement, more computation on SoCsSoCs

The performance of each IP as well as SoC architecture matters

Eff t t hEff t t h S CS C ffEfforts to enhance Efforts to enhance SoCSoC performanceperformance각 HW 및 SW IP성능 개선

현재까지 가장 널리 사용된 방법

복수의 IP이용 – 예: multi-processor SoC (MPSoC)복고???

다수의 IP간 또는 HW-SW간 interaction 최적화 = 구조문제사람의 머리로 해석하고 예측하기에 너무 복잡사람의 머리로 해석하 예측하기에 너무 복잡Architecture design based on scientific analysis is necessary

현재현재 design productivitydesign productivity는는 IP IP 수준이수준이 한계한계 SoCSoC 구조구조수준으로수준으로 확장확장 필요필요!!!!

Slow simulation time problem

Higher Level of Design AbstractionsHigher Level of Design Abstractions

역사적으로 higher level of design abstraction은 design productivity를 높이는 유용한 수단

Transistor level gate level register transfer level (RTL) electronic system level (ESL)electronic system level (ESL)

fHigher level of design abstractionHide unnecessary details

Higher simulation speed

Cope with more complex designs

Time Level of abstractions Design size LanguagesHigher levelof abstraction

2000s Electronic system level 10M+ C/C++/SystemC

1990s RTL 100K ~ 10M Verilog, VHDL

1980s Gate level 1K ~ 100K Schematic

1970s Transistor level ~ 1K SPICE netlist, layout

5

Design Cost for Mobile Design Cost for Mobile SoCsSoCs

nic

syst

em

ESL)

des

ign

nic

syst

em

ESL)

des

ign

Elec

tron

leve

l (E

Elec

tron

leve

l (E

출처: 2005 ITRS

Design cost increases exponentially

Electronic System Level (ESL) Design 소개

6

Electronic System Level (ESL)Electronic System Level (ESL)

An abstraction level of electronic circuit designs

Higher than register transfer level (RTL)

Lower than algorithm level

Design abstraction RTL ESL Algorithm level

Function accuracy Flip-flop level Register accurate levelBus-functional level

Behavior level

Cycle accuracy Cycle accurate Both (with or without cycle accuracy) are possible

No timing

Communication method

Signal (bit-level) SignalTransactionFunction calls

Function calls

Description languages

Hardware description language (Verilog, VHDL)

C/C++/SystemC C/C++/SystemC

목적에 따라 매우 다양한 abstraction layer가 존재한다예1: bus-functional transaction level model w/ cycle-accuracy (구조설계용)예2: bus-functional transaction level model w/o cycle-accuracy (SW 개발용)

Popular Levels in ESLPopular Levels in ESL

Programmer’s view (PV) – register accurate but no timingArchitectural view (AV) – register accurate & cycle approximateVerification view (VV) – register and cycle accurate

- Bus fabric- Arbiter, bus matrix- Bus bridges

- CPUs- DSPs- Interrupt controller, DMA controller, etc.- HW accelerators

SoC

Processors / Accelerators On-chip communication

CPUCPU

DSP

Memory controller

DSP

GPS

MPEG

Software Software

Memory

- OS, device driver- Middleware- Application software

- USIM, SDIO, USB, PCMCIA, UART, etc.- Corresponding host models- CDMA/Wibro modem & basestation models

SoCInterfaces & host models Software

PCMCIAUSB Modem

MPEG

Bus bridge

SDIOUSIM

Host Host Host Host Base-station

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ESL Design ESL Design 특장점특장점

Efficient hardware-software co-design in early design stage

고속/정확한 hardware-software co-simulation이 필요

특성ESL design

(Vi l l f )RTL FGPA특성

(Virtual platform)RTL FGPA

Availability Early Late Very late

구조 수정시간매우 빠름(수 분)

매우 느림(수 일 ~ 주)

매우 느림(수 일 ~ 주)

구조 변경범위 무제한 무제한 제한적

Simulation 정확도 높음 매우 높음 매우 높음Simulation 정확도 높음 매우 높음 매우 높음

Simulation 속도빠름

(RTL대비 3000배 이상)매우 느림 매우 빠름

Hardware-software co-design

매우 효과적 매우 제한적 제한적

Early Stage Performance Analysis Early Stage Performance Analysis 중요성중요성

Requirements / specification

Architecture exploration

현재 설계방식 ESL design을 이용한 설계방식

RTL

Gate-level

Behavioral synthesisBehavioral synthesis

Logic/physical synthesisLogic/physical synthesis

Architecture explorationESL

Logic/physical synthesisLogic/physical synthesis

경험과 지식 & 설계 marginInfeasible region의 solution이나

poor quality solution을 선택할 확률이 높다

Infeasibleregion

LayoutLayout LayoutLayout

Infeasible solutionOptimum solutionRefinement-needed solution

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Early Stage Performance Analysis Early Stage Performance Analysis

Infeasibleregion

Architecture exploration @ ESLSimulation speed

Abstraction

Requirements / specification

RTL model

Gate-levelmodel

Accuracy

Analysis time

FlexibilityBehavioral synthesisBehavioral synthesis

Logic/physical synthesisLogic/physical synthesis

Modeling efforts

Trade-offs between accuracy, analysis time, modeling efforts, and design flexibility between abstraction levels

LayoutLayout

ESL Design ESL Design 효과효과

Requirements

신규 IP 개발(algorithm / SW)

HW-SW partitioning

HW IPs

SW IPs

신규IPs

ESL 1

+성능분석및

최적화 Architecturepartitioning

Architecture exploration ESL 2

Initialarchitecture

최적화

성능분석및

최적화

Architecture design

Architecture design

ESL 3

HW-SW co-

verification

Implementation

Verification

Implementation

Verification

Yes

Architecture최적화

Early HW-SWco-verification

Late HW-SWco-verification

HW on silicon + SW(integration + verification)

Problem?

Success

No

Time to marketadvantage

Time to siliconadvantage

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ESL Design Tasks

ESL Design TasksESL Design Tasks

Architecture explorationArchitecture exploration

Parallel development of hardware and softwareParallel development of hardware and software

HardwareHardware--software partitioningsoftware partitioning

HardwareHardware--software cosoftware co--verificationverification

Performance analysisPerformance analysis

RTL generationRTL generation

Power analysisPower analysis

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Architecture ExplorationArchitecture Exploration

Exploration spaceat different

abstraction levels( i h d i ff )Pe

rform

ance

Initial architecture

Legend

gate-level

(with same design effort)

RTL

ESL

Specification

P

O ti

Infeasibleregion

Poor qualityregion

Cost“Intersection of the curve within a circle represents the set of optimum architecture solutions searchable at the abstraction level”

Optimumarchitecture curve

HardwareHardware--Software CoSoftware Co--DesignDesign

전통적인전통적인 설계방식설계방식

Sequential development: hardware 개발 後 software 개발

ESL designESL design을을 이용한이용한 설계방식설계방식

Parallel development: hardware와 software 개발 병행

Architecture 설계 Hardware 설계 Software 설계

A hit t 설계 H d 설계

Old flow

N fl납기단축

Architecture 설계 Hardware 설계

Software 설계

ESL design

New flow

ESL design

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HardwareHardware--Software PartitioningSoftware Partitioning

DefinitionDefinitionA process that makes decisions whether a required functionality of a system is more advantageously implemented in hardware or in softwareFundamental phase of hardware-software co-designp g

ESL design technique plays an crucial roleESL design technique plays an crucial roleFast iterative performance analysis is essential

Start with all HW (or SW) implementation

Is the performance Is the performance requirement met?

Change HW-SW partitionsReschedule jobsNoESL design

Optimum system architecture

Yes

Is it optimum?Is it optimum?

Yes

NoESL design

HardwareHardware--Software CoSoftware Co--VerificationVerification

전통적인전통적인 sequential developmentsequential development

Hardware-software co-verification이 과제 후반부에 수행

Big surprise (성능/기능 문제)로 인한 long iteration 발생

ESL designESL design을을 이용한이용한 parallel developmentparallel developmentESL designESL design을을 이용한이용한 parallel developmentparallel development

Hardware-software co-verification이 과제 초반부에 수행

지속적인 co-verification으로 big surprise가 작고 iteration이 짧다

Architecture 설계 Hardware 설계 Software 설계Old flow

Long iterations

Architecture 설계 Hardware 설계

Software 설계

New flow

ESL designESL design

Short iterations

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Performance AnalysisPerformance Analysis

ESL design tool에서 얻을 수있는 data

Information(Data 사용 예)

F i ll F i ll h d• Function call trace• Cache hit rate• Function execution time• Variable value

• Function call overhead• Cache size optimization• Software execution time 측정• Software bug 원인 파악

• Bus and signal waveform• Bus utilization• Register value waveform

• HW-SW co-verification• Bus & system architecture 분석• Hardware initialization의 정확성

SW

HW

• System performance 예측• HW-SW partitioning에 따른system 성능분석

System • 위에 제시한 HW & SW data

RTL GenerationRTL Generation

Behavioral synthesisBehavioral synthesis

Automatic ESL to RTL mapping

현재 설계방식 ESL design을 이용한 설계방식

ESL designInitial

software

Architecture explorationArchitecture design

Initial architecture document

Behavioral synthesis(RTL generation)

Behavioral synthesis(RTL generation)

Hardware design

Software design

Hardware design

Start from scratch

Software design

Start from scratch

•Short time for RTL generation•Short time for HW-SW co-verificationBroken links

(manual conversion)

(RTL generation)(RTL generation)

13

Power AnalysisPower Analysis

Why ESL power analysis?Why ESL power analysis?

Realistic scenario for power analysis

Short analysis time for power analysis

Base for system (HW & SW) power optimizationBase for system (HW & SW) power optimization

예예: ESL power analysis flow: ESL power analysis flow

Scenario @ESL & analysis @RTL

ESL

RTL

Realisticscenario

AnalysisAnalysisspeed PowerTheater

PrimePower

p (한국)

PowerTheater-ESLORINOCO

Mapae (한국)

Gate-level

Transistor-level

Unrealisticscenario AnalysisAnalysis

정확도

PowerTheaterPrimePower

PowerMillHSPICE

적용 예