ESL design 소개 (1시간)

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Electronic System Level (ESL)Electronic System Level (ESL)DesignDesign 2008. 9

(([email protected]@kw.ac.kr))

Copyrighted by Joonhwan Yi ([email protected])

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vvBackgroundBackground

vvElectronic system level (ESL) designElectronic system level (ESL) design

vvESL design tasksESL design tasks

vv

vv

Copyrighted by Joonhwan Yi ([email protected]) 2

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Back round

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Computer Based SystemComputer Based System

vv SystemSystem--onon--chips (chips (SoCsSoCs) are computer based systems) are computer based systems Processors and software control the system

Hardware accelerators perform dedicated tasks On-chip communication and interface IP handles data traffic

vv Many hardware and software components are coMany hardware and software components are co--working in aworking in acomplex mannercomplex manner System behavior cannot be predicted and optimized easily

Processors / Accelerators On-chip communicationMemory

- OS, device driver- Middleware- Application software

- Bus fabric- Arbiter, bus matrix- Bus bridges

- USIM, SDIO, USB, PCMCIA, UART, etc.- CDMA/Wibro modem

- CPUs- DSPs- Interrupt controller, DMA controller, etc.- HW accelerators

SoC

Interfaces

Software

CPU

CPU

PCMCIA

DSP

USB Modem

Memorycontroller

DSP

GPS

MPEG

Bus bridge

SDIOUSIM

Software Software

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Increasing Design ComplexityIncreasing Design Complexity

vvData transfer rate for communication standardsData transfer rate for communication standards

2G (GSM/GPRS/EDGE/CDMA2000 1x) 100 Kbps

3G (WCDMA/CDMA2000 1x EV-DO ~ 3 Mbps

Beyond 3G (HSPA/WiBro/LTE) 10 ~ 200 Mbps

4G 100 Mbps ~ 1 Gbps

10,000 x

Voice + broadcasting + entertainment + camera + security +etc.

vvMore functionality, more data movement, moreMore functionality, more data movement, morecomputationcomputation

The performance of each IP as well as SoC architecturematters

Architecture design based on scientific analysis is necessary

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Problems inProblems in SoCSoC Architecture DesignArchitecture Design

vv Slow simulation speed !!!Slow simulation speed !!!

More than 10M gates for modern mobile modem SoCs ormultimedia processors

At register transfer level (RTL), for SoC size, the simulation speedis about 3~30 cycles per second

For example, consider a CDMA modem SoC.

Takes about 4 hours to simulate 20 ms of real time scenario

,should be simulated many times

To simulate a real time scenario of 3 seconds, it takes more than 60years

At FPGA, its fast but has many limitations

Limited design space, long time for design changes, bad visibility forinternal signals, etc.

vv Late availability of executable designsLate availability of executable designs


HigherHigher level of abstractionlevel of abstraction addresses these problems nicely!

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Design AbstractionsDesign Abstractions

Time Level of abstractions Design size Languages

2000s Electronic system level 10M+ C/C++/SystemC

1990s RTL 100K ~ 1M Verilog, VHDL

Higher levelof abstraction

1980s Gate level 1K ~ 10K Schematic

1970s Transistor level ~ 100 SPICE netlist, layout


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Electronic System Level (ESL)

es gn

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Electronic System Level (ESL)Electronic System Level (ESL)

vv An abstraction level of electronic circuit designsAn abstraction level of electronic circuit designs

Higher than register transfer level (RTL) Lower than algorithm level

Design abstraction RTL ESL Algorithm level

Function accuracy Register (flip-flop) level Block levelBus-functional level

Behavior level


cycle accuracy) arepossible

Communicationmethod

Signal (bit-level) SignalTransactionFunction calls

Function calls

Descriptionlanguages

HDL (Verilog, VHDL) C/C++/SystemC C/C++/SystemC

abstraction layer 1: bus-functional transaction level model w/ cycle-accuracy ()2: bus-functional transaction level model w/o cycle-accuracy (SW )

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ESL DesignESL Design

v Efficient hardware-software co-design in early design stage

/ hardware-software co-simulation

ESL design

(Virtual platform)RTL FGPA

Availability Early Late Very late


( ) ( ~ ) ( ~ )

Simulation

Simulation

(RTL 3000 )

Hardware-softwareco-design

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ESL DesignESL Design

Requirements

IP(algorithm / SW)

HW-SWpartitioning

HWIPs

SWIPs

IPs

ESL 1

+

Architectureexploration

ESL 2

Initialarchitecture

Yes

ArchitectureLate HW-SW

co-verification


Architecture

design

Architecture

design

ESL 3

HW-SWco-

verification

Implementation

Verification

Implementation

Verification

HW on silicon + SW(integration + verification)

Problem?

Success

No

Time to marketadvantage

Early HW-SWco-verification

Time to siliconadvantage

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ESL Desi n Tasks

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ESL Design TasksESL Design Tasks

vv Architecture explorationArchitecture exploration

vv HardwareHardware--software cosoftware co--designdesignvv HardwareHardware--software partitioningsoftware partitioning

vv HardwareHardware--software cosoftware co--verificationverification

vv Performance analysisPerformance analysis


vv RTL generationRTL generation

vv Power analysisPower analysis

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Architecture ExplorationArchitecture Exploration

gate-level

Exploration spaceat differentabstraction levels

(with same design effort)Perform

ance

Initial architecture

Legend

Infeasibleregion


ESL

Specification

CostIntersection of the curve within a circle represents the set ofoptimum architecture solutions searchable at the abstraction level

Optimumarchitecture curve

oor qua yregion

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HardwareHardware--Software CoSoftware Co--DesignDesign

vv

Sequential development: hardware software vv ESL designESL design

Parallel development: hardware software


rc ec ure ar ware o ware

Architecture Hardware

Software

ESL design

ow

New flow

ESL design

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HardwareHardware--Software PartitioningSoftware Partitioning

vv DefinitionDefinition

A process that makes decisions whether a required functionality

of a system is more advantageously implemented in hardware orin software

Fundamental phase of hardware-software co-design

vv ESL design technique plays an crucial roleESL design technique plays an crucial role

Fast iterative performance analysis is essential

S i S i i


Is the performancerequirement met?

Optimum system architecture

Change HW-SW partitionsReschedule jobs

Yes

Is it optimum?

Yes

No

NoESL design

ESL design

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HardwareHardware--Software CoSoftware Co--VerificationVerification

vv sequential developmentsequential development

Hardware-software co-verification

Big surprise (/ ) long iteration

vv ESL designESL design parallel developmentparallel development

Hardware-software co-verification

co-verification big surprise iteration


Architecture Hardware Software

Architecture Hardware

Software

Old flow

New flow

ESL designESL design

Short iterations

Long iterations

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Performance AnalysisPerformance Analysis

ESL design tool

data

Information

(Data )

Function call trace Cache hit rate Function execution time Variable value

Function call overhead Cache size optimization Software execution time Software bug

SW


Bus and signal waveform Bus utilization Register value waveform

HW-SW co-verification Bus & system architecture Hardware initialization

HW

System performance HW-SW partitioning system

System HW & SW data

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RTL GenerationRTL Generation

vv Behavioral synthesisBehavioral synthesis

Automatic ESL to RTL mapping

Architecture explorationArchitecture design

ESL design


Hardwaredesign

Softwaredesign

ESL designInitial

software

Hardwaredesign

Start fromscratch

document

Softwaredesign

Start fromscratch

Short time for RTL generationShort time for HW-SW co-verificationBroken links

(manual conversion)

Behavioral synthesis(RTL generation)

Behavioral synthesis(RTL generation)

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Power AnalysisPower Analysis

vv Why ESL power analysis?Why ESL power analysis?

Realistic scenario for power analysis

Short analysis time for power analysis

Base for system (HW & SW) power optimization

vv : Samsung: Samsung--Sequence ESL power analysis flowSequence ESL power analysis flow

Scenario @ESL & analysis @RTLPowerTheater-ESL


ESL

RTL

Gate-level

Transistor-level

Unrealistic

scenario

ea s cscenario

Analysis

Analysisspeed PowerTheater

PrimePower

ORINOCOMapae ()

PowerTheaterPrimePower

PowerMillHSPICE

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vv ESL designESL design very fast hardware simulation modelvery fast hardware simulation model

FPGA chip RTL 3000

RTL available

-- --


ESL design hardware software

(early system verification)

(optimum system design)

vv Early stage system (HW+SW) performance analysisEarly stage system (HW+SW) performance analysis

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ESL design 소개 (1시간)

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