Bi Tp Ln Thit K Tng Hp H Thng S

Bi Tp Ln Thit K Tng Hp H Thng S2015

TRNG I HC BCH KHOA H NI

VIN IN T VIN THNG

====o0o====

BO CO BI TP LN TI: M PHNG BI TON THANG MY 6 TNGGVHD : TS Nguyn Hong DngSinh vin thc hinMSSVLp

Nguyn Vn Vinh20122809KT TTT 04-K57

Th Trang20124986KT TTT 03-K57

Dng Vn Trung20122610KT TTT 02-K57

Nguyn Vn Vit20122508KT TTT 06-K56

H Ni - 11/2015A. LI NI UB. NI DUNG

Chng I: Tng quan v FPGA v Verilog HDL1.1. Tng quan v FPGA.1.1.1 Mt vi nt v FPGANgy nay, khi nhcn cng ngh FPGA chng ta thng nghn cc con Chip c th ti lp trnhc. Cc bn khi tm hiu v FPGA qua internet thng b lc do c qu nhiu thng tin v khng bit btu tu. Bi vit ny mnh s gii thiu mt vi nt c bn v cng ngh FPGA, cc bn cha bit g c mt ci nhn tng quan v n. Nu bn l sinh vin nm 3 hoc trc gi ch lm vic vi lp trnh trn Viiu khin v by gi mun lm quen vi FPGA th nnc bi vit ny.u tin chng ta cn hiu r ci tn ca n.

Field Programmable Gate Array (FPGA)Field Programmable Gate Arrays l mt chip logic s c th lp trnh c, tc l bn c th s dng chng lp trnh cho hu ht cc chc nng ca bt k mt thit k s no. c nhiu ti liu trn website ni nhiu v FPGA nhng y mnh mun cc bn ch n ci tn ca n. Mnh thy trn cc website ngi ta dich ch FIELD l dng trng. Nhng y khng phi nh vy. FIELD ngha l ni s dng con chip. Field Programmable ngha l c th lp trnh c ti ni ca ngi s dng khc vi mt s chip l phi lp trnh ti ni sn xut. FPGA c to thnh t mt mng (matrix hay array) cc phn t kh trnh nn c gi l Programmable Gate Array.

B nh tnh u tin da trn FPGA (thng c gi l SRAM trn nn FPGA) c xut bi Wahlstrom vo nm 1967. Sau bn thng mi ca FPGA c Xilinx gii thiu vo nm 1984. Lc ny n gm c mt mng ca cc khi logic c th ti cu hnh Configurable Logic Blocks (CLBs) v cc u vo ra I/O (input/output). Chip FPGA u tin cha 64 CLBs v 58 I/Os. Ngy nay, FPGA c th cha khong 330,000 CLBs v khong 1100 I/Os. Phn ln cc sn phm FPGA trn th trng hin nay u da trn cng ngh SRAM vi 2 hng sn xut ln nht l Xilinx v Altera. Ngoi ra cn c cc hng khc sn xut FPGA nhng vi mc ch chuyn dng (Atmel, Actel, Lattice, SiliconBlue,..).

Kin trc c bn ca FPGA bao gm 3 thnh phn chnh: khi logic c th ti cu hnh, Configurable Logic Blocks (CLBs) thc hin cc chc nng logic; cc kt ni bn trong, Porgrammable Interconnect c th lp trnh kt ni cc u vo v u ra ca cc CLB v cc khi I/O bn trong; cc khi I/O cung cp giao tip gia cc ngoi vi v cc c tn hiu bn trong.

Di y l mt chip FPGA in hnh v tng khi ca n.

Hnh 1:Cu trc c bn ca FPGA

1. Khi logic c th ti cu hnh.Mc ch ca vic lp trnh khi logic trong FPGA l cung cp cc tnh ton v cc phn t nh c bn c s dng trong h thng s. Mt phn t logic c bn gm mt mch t hp c th lp trnh, mt Flip-Flop hoc mt cht (latch). Ngoi khi logic c bn , nhiu Chip FPGA hin nay gm mt hn hp cc khi khc nhau, mt s trong ch c dng cho cc chc nng c th, chng hn nh cc khi b nh chuyn dng, cc b nhn (multipliers) hoc cc b ghp knh (multiplexers). Tt nhin, cu hnh b nh c s dng trn tt c cc khi logic iu khin cc chc nng c th ca mi phn t bn trong khi .

2. Kt ni c th lp trnh.Cc lin kt trong mt FPGA dng lin kt cc khi logic v I/O li vi nhau to thnh mt thit k. Bao gm cc b ghp knh, cc transistor v cng m ba trng thi. Nhn chung, cc transistor v b ghp knh c dng trong mt cm logic kt ni cc phn t logic li vi nhau, trong khi c ba u c dng cho cc cu trc nh tuyn bn trong FPGA. Mt s FPGA cung cp nhiu kt ni n gin gia cc khi logic, mt s khc cung cp t kt ni hn nn nh tuyn phc tp hn.

3. Khi I/O kh trnh.I/O cung cp giao tip gia cc khi logic v kin trc nh tuyn n cc thnh phn bn ngoi. Mt trong nhng vn quan trng nht trong thit k kin trc I/O l vic la chn cc tiu chun in p cung cp v in p tham chiu s c h tr.

Theo thi gian, cc kin trc FPGA c bn c pht trin hn na thng qua vic b sung cc khi chc nng c bit c th lp trnh, nh b nh trong (Block RAMs), logic s hc (ALU), b nhn, DSP-48 v thm ch l b vi x l nhng c thm vo do nhu cu ca cc ngun ti nguyn cho mt ng dng. Kt qu l nhiu FPGA ngy nay c nhiu ngun ti nguyn hn so vi cc FPGA trc .

Hnh 2: Khi I/O kh trnh1.1.2 ng dng ca FPGAng dng ca FPGA bao gm: x l tn hiu s DSP, cc h thng hng khng, v tr, quc phng, tin thit k mu ASIC (ASIC prototyping), cc h thng iu khin trc quan, phn tch nhn dng nh, nhn dng ting ni, mt m hc, m hnh phn cng my tnh Do tnh linh ng cao trong qu trnh thit k cho php FPGA gii quyt lp nhng bi ton phc tp m trc kia ch thc hin nh phn mm my tnh, ngoi ra nh mt cng logic ln FPGA c ng dng cho nhng bi ton i hi khi lng tnh ton ln v dng trong cc h thng lm vic theo thi gian thc.1.1.3 ngha,vai tr ca FPGATrc y, khi mun ch to ra mt con chip vi x l, ngi ta phi thit k chip mc logic s dng cc ngn ng m t phn cng, kim tra cng on ny cn phi s dng nhng phn mm m phng. Sau thit k phi c tng hp da trn cc th vin cp thp ca hng sn xut con Chip sau ny, sau l qu trnh kim tra timing (nh thi) cho ton b thit k m bo thit k s hot ng tn s yu cu. Tt c cc cng on ny u ch c th kim tra bng cc phn mm m phng (iu ny dn ti nguy c xy ra sai st rt ln khi chuyn thit k sang mi trng Chip thc).

Quy trnh tip theo l gi thit k ca mnh ti cng ty sn xut Chip v ph mc cho s phn, mt chip mu gi vi triu la s c chuyn tr v, sau l bt u qu trnh test chip trong mi trng thc, nu tht bi, kh nng ln l chng ta s phi thc hin li hon ton qui trnh thit k nh ni trn, v c mi ln nh vy, phi thanh ton vi triu la cng vi khang thi gian nghin cu rt ln. Quy trnh ny lm cho cc t nc ngho nh Vit Nam khng th tham gia vo cc cuc chi ca cc t nc giu c trong th gii ca ASIC.

Nhng vi FPGA,chng ta khng nhng c th rt ngn thi gian thc hin ASIC m cn gim chi ph nghin cu ti a do qu trnh kim tra thit k khng cc Chip thc trong mi trng c th ni l gn vi mi trng ASIC thc nht. Kh nng ti cu hnh cho php sa bn thit k cho n khi t yu cu m khng phi tr khon chi ph no ngoi tin in tiu th1.2 Ngn ng m t phn cng Verilog HDL1.2.1 Qu trnh pht trinVerilog c ra i vo u nm 1984 bi Gateway Design Automation. Khi u, ngn ng u tin c dng nh l mt cng c m phng v kim tra. Sau thi gian u ngn ng ny c chp nhn bi ngnh cng nghip in t, mt cng c m phng, mt cng c phn tch thi gian, v sau ny vo nm 1987, cng c tng hp c xy dng v pht trin da vo ngn ng ny. Gateway Design Automation v nhng cng c da trn Verilog ca hng sau ny c mua bi Cadence Design System. T sau , Cadence ng vai tr ht sc quan trng trong vic pht trin cng nh ph bin ngn ng m t phn cng Verilog.Vo nm 1987, VHDL tr thnh mt chun ngn ng m t phn cng ca IEEE. Bi do s h tr ca B quc phng (DoD), VHDL c s dng nhiu trong nhng d n ln ca chnh ph M. Trong n lc ph bin Verilog, vo nm 1990, OVI ( Open Verilog International) c thnh lp v Verilog chim u th trong lnh vc cng nghip. iu ny to ra mt s quan tm kh ln t ngi dng v cc nh cung cp EDA ti Verilog.

Vo nm 1993, nhng n lc nhm chun ha ngn ng Verilog c bt u. Verilog tr thnh chun IEEE, IEEE Std 1364-1995, vo nm 1995. Vi nhng cng c m phng, cng c tng hp, cng c phn tch thi gian, v nhng cng c thit k da trn Verilog c sn, chun Verilog IEEE ny nhanh chng c chp nhn su rng trong cng ng thit k in t. Mt phin bn mi ca Verilog c chp nhn bi IEEE vo nm 2001. Phin bn mi ny c xem nh chun Verilog-2001 v c dng bi hu ht ngi s dng v ngi pht trin cng c. Nhng c im mi trong phin bn mi l n cho php bn ngoi c kh nng c v ghi d liu, qun l th vin, xy dng cu hnh thit k, h tr nhng cu trc c mc tru tng cao hn, nhng cu trc m t s lp li, cngnh thm mt s c tnh vo phin bn ny. Qu trnh ci tin chun ny vn ang c tip tc vi s ti tr ca IEEE.

1.2.2 Ngn ng verilog HDLNgn ng Verilog HDL p ng tt c nhng yu cu cho vic thit k v tng hp nhng h thng s. Ngn ng ny h tr vic m t cu trc phn cp ca phn cng t mc h thng n mc cng hoc n c mc cng tc chuyn mch. Verilog cng h tr mnh tt c cc mc m t vic nh thi v pht hin li. Vic nh thi v ng b m c i hi bi phn cng s c ch trng mt cch c bit.

Trong Verilog, mt linh kin phn cng c m t bi mt cu trc ngn ng khai bo module. S m t mt module s m t danh sch nhng ng vo v ng ra ca linh kin cng nh nhng thanh ghi v h thng bus bn trong linh kin. Bn trong mt module, nhng php gn ng thi, gi s dng linh kin v nhng khi quy trnh c th c dng m t mt linh kin phn cng.

Nhiu module c th c gi mt cch phn cp hnh thnh nhng cu trc phn cng khc nhau. Nhng phn t con ca vic m t thit k phn cp c th l nhng module, nhng linh kin c bn hoc nhng linh kin do ngi dng t nh ngha. m phng cho thit k, nhng phn t con trong cu trc phn cp ny nn c tng hp mt cch ring l.

Hin nay c rt nhiu cng c v mi trng da trn Verilog cung cp kh nng chy m phng, kim tra thit k v tng hp thit k. Mi trng m phng cung cp nhng chng trnh giao din ha cho bc thit k trc layout (front-end) v nhng cng c to dng sng v cng c hin th. Nhng cng c tng hp th da trn nn tng ca Verilog. Khi tng hp mt thit k th thit b phn cng ch nh FPGA hoc ASIC cn phi c xc nh trc..

Chng II: Gii thiu KIT FPGA DE2-70 v mi trng lp trnh Quartus II 9.12.1 Tng quan v kit DE2-702.1.1 Tng quan v Kit FPGA DE2.

Mc ch ca Kit DE2 l cung cp cho sinh vin mt phng tin ti u nghin cu v k thut s, cu trc my tnh v FPGA. Kit ny s dng nhng cngngh mi nht c v phn cng ln cng c CAD (Computer Aid Design) gipkhng ch sinh vin m cn c gio vin c th nghin cu c nhiu ng dngkhc nhau. Kit cung cp nhiu c im ph hp cho cng vic nghin cu cngnh pht trin nhng h thng s thng thng ln phc tp trong phng thnghim ca cc trng i hc.

2.1.2 c im c bn ca Kit FPGA DE2-70

Di y l hnh nh ca Kit DE2. N th hin b mt trn ca Kit cng nhv tr ca nhng linh kin trn Kit.

Hnh3: Mt trn ca Kit DE2-70 v v tr cc linh kin trn Kit

Kit DE2 mang nhng c im cho php ngi s dng c th thit k t nhng mch in n gin cho n nhng thit k phc tp nh Multimedia.

Kit DE2 gm nhng linh kin sau:

Chip FPGA Cyclone II 2C70 gm 896 chn. Tt c nhng linh kin trn kit u c kt ni sn vi nhng pin ca FPGA, iu ny cho php ngi s dng c th iu khin tt c nhng linh kin cng nh ng dng ca chng. Rom EPCS16: dng thit lp cu hnh ban u cho thit b, hot ng ni tip. USB Blaster: dng ci t chng trnh cho FPGA t my tnh, h tr 2 ch l JTAG v AS. 1 IC SSRAM 2Mbyte. 2 IC SDRAM 32Mbyte. B nh flash 8Mbyte. Khe cm th nh SD.

4 nt bm.

18 cng tc gt.

18 n led .

9 led xanh.

Ngun xung clock 50MHz v 28.63MHz.

B m ha/gii m m thanh CD 24bit vi cc u cm line-in, line-out, microphone-in.

B chuyn i tn hiu s sang tng t VGA 10bit vi u cm VGA-out.

2 b gii m tn hiu TV vi u cm TV-in.

Giao tip Enthernet 10/100.

Giao tip USB 2.0.

Giao tip chun RS-232 vi 9 chn.

Giao tip chun PS/2 cho chut v bn phm.

Giao tip hng ngoi (IrDA).

2 cng kt ni dng giao tip vi cc thit b ngoi vi khc m ngi s dng mun kt ni vo Kit.

i km vi nhng c tnh phn cng, Altera cng cung cp nhng giao tip I/O chun v bng iu khin vic truy xut nhng linh kin trn Kit da trn phn mm DE2 Control Panel.

Hnh4: S khi board mch Kit DE2-70

1.1.1. ng dng trong ging dy v hc tp.

Nhng kha hc v thit k mch logic v cu trc my tnh thng cp n nhng thit b v linh kin in t. Ngy nay khi m cng ngh ang pht trin vi tc chng mt th nhng gio trnh cng nh nhng thit b trong cc phng th nghim cng phi lun c cp nht nhng cng ngh v cng c thit k hin i nht, tuy nhin n vn phi m bo gip sinh vin nm vng nhng kin thc nn tng cho n nhng kin thc cao hn. Kit DE2 c thit k p ng c tt c nhng yu cu trn.1.1.2. ng dng trong nghin cu v thit k.Vi Chip Cyclone II FPGA tn tin, nhiu loi giao tip I/O v nhiu loi b nh khc nhau, Kit DE2 s gip ngi s dng rt linh ng trong vic thit k nhiu loi ng dng khc nhau. Cng vi nhng ng dng minh ha km theo Kit, ngi thit k c th to ra nhng th nghim th v v nhng ng dng nh l audio, video, USB, network v memory. Kit DE2 cng c th thc thi c nhng ng dng nhng s dng vi x l Nios II.Mt s ng dng minh ha:

ng dng trong x l nh v truyn hnh.

Hnh5: ng dng trong x l nh v truyn hnh ng dng trong x l m thanh.

Hnh6: ng dng trong x l m thanh

ng dng giao tip USB.

Hnh7: ng dng trong giao tip USB2.2 Mi trng lp trnh Quartus II 9.1.Quartus II l cng c phn mm pht trin ca hng Altera, cung cp mi trng thit k ton din cho cc thit k SOPC (h thng trn mt chip kh trnh - system on a programmable chip).

y l phn mm ng gi tch hp y phc v cho thit k logic vi cc linh kin logic kh trnh PLD ca Altera, gm cc dng APEX, Cyclone, FLEX, MAX, Stratix... Quartus cung cp cc kh nng thit k logic sau:

Mi trng thit k gm cc bn v, s khi, cng c son tho cc ngn ng: AHDL, VHDL, v Verilog HDL. Thit k LogicLock. L cng c mnh tng hp logic. Kh nng m phng chc nng v thi gian.

Phn tch thi gian. Phn tch logic nhng vi cng c phn tch SignalTap@ II. Cho php xut, to v kt ni cc file ngun to ra cc file chng trnh. T ng nh v li. Kh nng lp trnh v nhn din linh kin. Phn mm Quartus II s dng b tch hp NativeLink@ vi cc cng c thit k cung cp vic truyn thng tin lin mch gia Quartus vi cc cng c thit k phn cng EDA khc. Quartus II cng c th c cc file mch (netlist) EDIF chun, VHDL v Verilog HDL cng nh to ra cc file netlist ny. Quartus II c mi trng thit k ha gip nh thit k d dng vit m, bin dch, sot li, m phng...

2.3 S lc cch s dng phn mm Quartus II 9.1. to mi mt project trong Quartus II 9.1 ta lm nh sau:

Chy phn mm Quartus II 9.1

File ( New project Wizard.

Next.

Chn v tr th mc lu project v tn project ( Next.

Next.

Chn dng chp l Cyclone II v tn chip l EP2C70F896C6 ( Next.

Next.

Finish.

Hnh8: Vo File ( New Project Wizard

Hnh9: Chn Next tip tc

Hnh10: Chn th mc cha project v t tn cho project ri Next

Hnh11: Chn Next tip tc

Hnh12: Chn Cyclone II trong Family v EP2C70F896C6 cho Kit DE2-70 ri Next

Hnh13: Chn Next tip tc

Hnh: Hnh14:Chn Finish kt thcChng III: Thit K chng trnh iu khin thang my 6 tng v m phng trn modelsim,Kit DE2-70. 3.1 S khi.Hnh 15: S khiS khi c chia lm 3 modul nh l khi chia tn DIV,khi iu khin chnh Control v khi hin th Display.

iu khin thang my 6 tng,bi ton cn u vo(input) l tn hiu xung clock 50Mhz ca KitDE2-70,tn hiu reset,nt bm ln(up),nt bm xung(down),gi tng(call_floor),chn tng(select_floor),gi ca m(hold door) v ng ca(close door) th cho u ra l s tng thang my ang hin ti,hng di chuyn ca thang my hay trng thi hin ti ca thang my.

3.2 M t chi tit.

3.2.1 Khi chia tn

Khi chia tn DIV c u vo (input) l xung clock ca Kit DE2-70 l 50MHz v tn hiu reset.u ra(output) l CLK_1,khi chia tn s chia tn t 50MHz xung 1Hz thi gian xung CLK_1 c chu k T= 1s.

3.2.2 Khi iu khin.

Khi Control l khi iu khin chnh,iu khin hot ng c bn ca thang my nh gi tng(call_floor),chn tng(select_floor),m ca(OpenDoor),ng ca(CloseDoor) v gi ca(HoldDoor).Thang my c 5 ch trng thi l trng thi ch,trng thi m ca,trng thi ng ca,trng thi ln v trng thi xung. Khi bnh thng hoc c reset,trng thi v trng thi ch(Swait) khi c tn hiu ca u vo l up hoc down th ng thi vi vic gi tng ang hin ti ti tng c gi. sau thang my chuyn sang trng thi m ca(OpenDoor),lc ny nu trong thi gian 5s hoc bm nt close th ca s ng li v sang trng thi CloseDoor.Khi ca c ng nu gi ca(hold) th ca li m v trng thi quay v trng thi OpenDoor.cn nu ko th lc ny s bt u vic chn tng.tng chn l i ln th thang my s i ln v ngc li.khi n tng chn th thang my s m ca tc l trng thi lc ny l trng thi OpenDoor.Khi ny cho u ra l tng m thang my ang hoc ang n, vi mi trng thi s c tn hiu u ra bo hiu hng m thang my ang di chuyn.

3.2.3 Khi hin th.

Khi hin th,hin th trng thi hin ti ca thang my ra LED 7 thanh v s tng hin ti thang my ang ra LED 7 thanh,LEDG.

S khi c to ra khi xy dng bng codeS trng thi FSM.

3.3 Kt Lun

Vi kt qu ny, em bc u xy dng mt b iu khin hot ng ca thang my 6 tng n gin.

. c bit qua qu trnh nghin cu v thc hin ti em tch lu c nhiu kin thc b ch:

Bc u nm c kin thc c bn v FPGA v ngn ng m t phn cng Verilog HDL

Hiu c nguyn tc hot ng ,thut ton ca thng my.Nm c cch s dng v lp trnh bng phn mm QUATUS II, v hiu

cch np v chy mt chng trnh trn kit pht trin DE2.Nhng iu cn hn ch v hng pht trin ca ti.

Do thi gian thc hin ti c hn nn em mi ch lm c b iu khin thang my 6 tng theo nguyn l n gin.Chng trnh mi ch c m phng trn phn mm ModelSim vn cha c thc s ng nh yu cu.