EE141 VLSI Test Principles and Architectures Test Generation 1 1 中科院研究生院课程： VLSI...

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VLSI Test Principles and Architectures Test Generation1

中科院研究生院课程： VLSI 测试与可测试性设计

第 5讲测试生成 (1)

李晓维中科院计算技术研究所

Email: [email protected]://test.ict.ac.cn

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Chapter 4Chapter 4

Test GenerationTest Generation

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What is this chapter about?What is this chapter about? Introduce the basic concepts of ATPG

Focus on a number of combinational and sequential ATPG techniques Deterministic ATPG and simulation-based

ATPG Fast untestable fault identification

ATPG for various fault models

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Test GenerationTest Generation Introduction Random Test Generation Theoretical Foundations Deterministic Combinational ATPG Deterministic Sequential ATPG Untestable Fault Identification Simulation-based ATPG ATPG for Delay and Bridge Faults Other Topics in Test Generation Concluding Remarks

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IntroductionIntroduction Test generation is the bread-and-butter in VLSI

Testing Efficient and powerful ATPG can alleviate high costs of DFT Goal: generation of a small set of effective vectors at a low

computational cost ATPG is a very challenging task

Exponential complexity Circuit sizes continue to increase (Moore’s Law)

– Aggravate the complexity problem further Higher clock frequencies

– Need to test for both structural and delay defects

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Conceptual View of ATPGConceptual View of ATPG Generate an input vector that can distinguish

the defect-free circuit from the hypothetically defective one

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Fault ModelsFault Models Instead of targeting specific defects,

fault models are used to capture the logical effect of the underlying defect

Fault models considered in this chapter: Stuck-at fault Bridging fault Transition fault Path-delay fault

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Simple illustration of ATPGSimple illustration of ATPG Consider the fault d/1 in the defective circuit Need to distinguish the output of the defective circuit

from the defect-free circuit Need: set d=0 in the defect-free circuit Need: propagate effect of fault to output Vector: abc=001 (output = 0/1)

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Example 1Example 1

a

b

c

d

e

f

10

g h i 1

s-a-0j

k

z

0(1)1(0)

1Test vector for h s-a-0 fault

Good circuit valueFaulty circuit value

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A Typical ATPG SystemA Typical ATPG System Given a circuit and a fault model

Repeat Generate a test for each undetected fault Drop all other faults detected by the test using a

fault simulator Until all faults have been considered

Note 1: a fault may be untestable, in which no test would be generated

Note 2: an ATPG may abort on a fault if the resources needed exceed a preset limit

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Category of ATPGCategory of ATPG Simulation-based

Exhaustive Random-pattern generation Pseudo-random-pattern generation

Path sensitization D-algorithm, 9-V algorithm PODEM, FAN TOPS, SOCRATES

Boolean satisfiability & Neural network Boolean difference Boolean satisfiability (2-SAT, 3-SAT) Neural network

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Random Test GenerationRandom Test Generation Simplest form of test generation

N tests are randomly generated Level of confidence on random test set T

The probability that T can detect all stuck-at faults in the given circuit

Quality of a random test set highly depends on the underlying circuit

Some circuits have many random-resistant faults

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Weighted Random Test GenerationWeighted Random Test Generation Bias input probabilities to target random resistant

faults Consider an 8-input AND gate

Without biasing input probabilities, the prob of generating a logic 1 at the gate output = (0.5)8 = 0.004

If we bias the inputs to 0.75, then the prob of generating a logic 1 at the gate output = (0.75)8 = 0.100

Obtaining an optimal set of input probabilities a difficult task

Goal: increase the signal probabilities of hard-to-test regions

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Exhaustive Test GenerationExhaustive Test Generation Exhaustive Testing

Apply 2n patterns to an n-input combinational circuit under test (CUT)

Guarantees all detectable faults in the combinational circuits are detected

Test time maybe be prohibitively long if the number of inputs is large

Feasible only for small circuits Pseudo-exhaustive Testing

Partition circuit into respective cones Apply exhaustive testing only to each cone Still guarantees to detect every detectable fault based on

Lemma 1

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Path Sensitization Method Circuit ExamplePath Sensitization Method Circuit Example

1 Fault Sensitization2 Fault Propagation3 Line Justification

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Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i

1 0DD1

11D

DD

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Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier

(chain of D or D) disappears

1DD

D

DD

11


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Final try: path g – i – j – k – L – test found!

0DD D

1 DD

1

0

1


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History of Algorithm SpeedupsHistory of Algorithm Speedups

Algorithm

D-ALGPODEMFANTOPSSOCRATESWaicukauski et al.ESTTRANRecursive learningTafertshofer et al.

Est. speedup over D-ALG(normalized to D-ALG time)17232921574 ATPG System2189 ATPG System8765 ATPG System3005 ATPG System48525057

Y ear

1966198119831987198819901991199319951997

†††

†

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Roth’s 5-Valued and Muth’s 9-ValuedRoth’s 5-Valued and Muth’s 9-Valued

SymbolDD01X

G0G1F0F1

Meaning1/00/10/01/1X/X0/X1/XX/0X/1

FailingMachine

1001XXX01

GoodMachine

0101X01XX

Roth’sAlgebra

Muth’sAdditions

1 100

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Forward ImplicationForward Implication

Results in logic gate inputs that are significantly labeled so that output is uniquely determined

AND gate forward implication table:

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Backward ImplicationBackward Implication

Unique determination of all gate inputs when the gate output and some of the inputs are given

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Example 2 Fault A sa0Example 2 Fault A sa0

Step 1 – D-Drive – Set A = 1

D1 D

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Step 2 -- Example 2Step 2 -- Example 2

Step 2 – D-Drive – Set f = 0

D1

0

DD

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Step 3 – D-Drive – Set k = 1

D1

0

DD

1D

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Step 4 – Consistency – Set g = 1

D1

0

DD

1D1

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Step 5 – Consistency – Set f = 0

D1

0

DD

1D1

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Step 6 – Consistency – Set c = 0, Set e = 0

D1

0

DD

1D1

00

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Test found -- Example 2Test found -- Example 2

Step 7 – Consistency – Set B = 0

Test cube: A, B, C, D, e, f, g, h, k, L

D1

0

X

DD

1D1

000

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Example 3 – Fault s sa1Example 3 – Fault s sa1 Primitive D-cube of Failure

1Dsa1

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Example 3 – Step 3 s sa1Example 3 – Step 3 s sa1 Propagation D-cube for v

1

D

0sa1 D1 D

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Example 3 – Step 4 s sa1Example 3 – Step 4 s sa1 Propagation D-cube for Z

1Dsa1

0 D

D

1 1

1D

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Example 3 – Step 5 s sa1Example 3 – Step 5 s sa1 Singular cover of m

1Dsa1

0 D

D

11

1D

1

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Test Found – Step 6 s sa1Test Found – Step 6 s sa1 Singular cover of d

1Dsa1

0 D

D

1 1

1 D

11

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Example 3 – Fault u sa1Example 3 – Fault u sa1 Primitive D-cube of Failure

1

D0

sa1

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Example 3 – Step 2 u sa1Example 3 – Step 2 u sa1 Propagation D-cube for v and implications

1

D

0sa1

D

00 1

0

1

0

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Example 3 – Step 3 u sa1Example 3 – Step 3 u sa1 Propagation D-cube for Z

1

sa1D

0

D

0

1D

0 10

1

0

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Example 3 – Step 4 Example 3 – Step 4 uu sa1 sa1 Singular cover for r – f = 0 and n = 1 cannot justify r = 1

1

sa1D

0

D

0

1D

0 10

1

0

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Example 3 – BacktrackExample 3 – Backtrack Remove C = 1 and B = 0 assignments

1

sa1 D

0

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Example 3 – BacktrackExample 3 – Backtrack Need alternate propagation D-cube for v

1

sa1 D0

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Example 3 – Step 5 u sa1Example 3 – Step 5 u sa1 Propagation D-cube for v

1

sa1 D01

D

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Example 3 – Step 6 u sa1Example 3 – Step 6 u sa1 Propagation D-cube for Z and implications

D

1

sa1D

01

D

1

1

00

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Example 3 – Step 7 u sa1Example 3 – Step 7 u sa1 Singular cover for r

sa1D

1

D

01

D

1

1

100

0

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Test Found – Step 8 u sa1Test Found – Step 8 u sa1 Singular cover for d – set A = 1

sa1D

1

D

01

D

1

1

100

10

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D-Algorithm – Top LevelD-Algorithm – Top Level

1. Number all circuit lines in increasing level order from PIs to POs;

2. Select a primitive D-cube of the fault to be the test cube; Put logic outputs with inputs labeled as D (D) onto

the D-frontier;3. D-drive ();4. Consistency ();5. return ();

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D-frontierD-frontier Fault Cone -- Set of hardware affected by fault D-frontier – Set of gates closest to POs with fault effect(s)

at input(s)

Fault Cone

D-frontier

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Singular Cover ExampleSingular Cover Example Minimal set of logic signal assignments to show essential

prime implicants of Karnaugh map

GateAND

123

InputsA0X1

BX01

Outputd001

GateNOR

123

Inputsd1X0

eX10

OutputF001

GateAND

123

InputsA0X1

BX01

Outputd001

GateNOR

123

Inputsd1X0

eX10

OutputF001

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D-Cube Operation of D-IntersectionD-Cube Operation of D-Intersection

– undefined (same as ) or – requires inversion of D and D D-intersection: 0 0 = 0 X = X 0 = 0

1 1 = 1 X = X 1 = 1X X = X

D-containment –Cube a containsCube b if b is a subset of a

01XDD

000

111

X01XDD

DD

DD

01XDD

000

111

X01XDD

DD

DD

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Concluding RemarksConcluding Remarks Covered a number of topics

Theoretical Foundations Combinational & sequential ATPG Untestable fault identification Simulation-based & hybrid ATPG Delay testing Bridging fault testing Compaction, N-Detect, FSM testing

Challenges Ahead Fast untestable fault identification essential to

remove large numbers of stuck-at, bridge, delay faults

Sequential ATPG remains an open research area

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中科院研究生院课程： VLSI测试与可测试性设计

下次课预告时间： 2007 年 10 月 29 日（周一 7:00pm ）

地点： S106 室内容：测试生成 (2)

教材： VLSI TEST PRINCIPLES AND ARCHITECTURES

Chapter 4 Test Generation

EE141 VLSI Test Principles and Architectures Test Generation 1 1 中科院研究生院课程： VLSI...

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