江门电子学系统与ASIC需求II 第四届核电子学ASIC研讨会

2014-10-31

江晓山 高能所

1

CONTENTS

Simple introduction of the existing schemes

Some possibility

the requirement for ASIC of JUNO electronics

2

SIMPLE INTRODUCTION OF THE SCHEMES

Three schemes

Scheme 1 : “all dry” electronics

Scheme 2 : Self-triggered under water electronics

Scheme 3 : Global-triggered under water electronics

3

Amplifier ADCData

processing

Data Storage & collection

Trigger & clock

DAQ

PMT Dry part

Packaged with PMTLocal box

Dry part

PMT Local box Dry part

scheme1

scheme2

scheme3

Long analog cable

Short digital cable Long digital cable

Short analog cable Long digital cable

SCHEME 1

Sample ADC

FPGADisc.

Int. ADC

Disc.32channels

xTCA crates x52

Cablesx16500

FEE Crate Sum(for level 2 trigger)

andControlModule(FCS&C)

FEE Crate Sum(for level 1 trigger)

andWhite Rabbit(for clock)

Module(FCS&WR)

Front End Electonics Module (FEE) x10

Preamplifierx16500

Trigger Crate Sum Module

(TCS)

L1 Trigger Module(L1T)

L2 Trigger Module(L2T)

White RabbitSystem(WRS)

L1 x52L2 x52

(Fiber link)

Calibration trigger

Veto trigger

WR networkclockL1

signal

dataL2

clock

signal

L1

Fiber network

xTCA crate

Backplane connection

Gigabit Ethernet switch

x52

DAQ slow control

(Fiber link)

PMT electronics

spliter

4

FROM LIANGJIAN WEN’S SLIDE

5

THE POSSIBLE VIEW OF SCHEME 1

Traditional structure, it should be ok but…, can

be the base scheme

6

SCHEME 2 : SELF-TRIGGERED UNDER

WATER ELECTRONICS(FROM ACHIM’S CDR)

Base on the SOC

Mainly work will be done in front, in JUNO then

in the water

No global trigger, self-trigger + soft-trigger, real

TDAQ

With the ASIC transfer 5V to 3000V in front

Intelligent PMT

7

Achim Stahl, RWTH Aachen 20. Oct 1́4

8

Power Supplies

Flash ADCs

Computer Farm

Power Supplies

Computer Farm

Voltage

Divider

HV

+

SoC

Pow

er

Clo

ck

Data

Hig

h V

olt

age

An

alo

g

Sig

nal

Intelligent PMT Conventional

+ Cascadability

+ Noise

9

From achim’s slide

10

From achim’s slide

Per MCP

• Amplification / shaping of

input

• Baseline to zero

• Detection of single p.e

(discrim.)

• Time-stamp of readout

window

• fADC.

• TDC for start of pulse ?

• Feature extraction

• Self-calibration

• Adjustment of HV and

amplification

• Creation of test pulses

Per PMT

• Optical test pulse (LED)

• Clock (locked to ext. clock)

• Data buffer

• System tests

• Data exchange

11

From achim’s slide

12

From achim’s slide

13

From achim’s slide

14

From achim’s slide

SCHEME 3 : GLOBAL-TRIGGERED UNDER

WATER ELECTRONICS

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AD Amp+Discriminator+ADC+FPGA+DDR

Amp+Discriminator+ADC+FPGA+DDRData collection

& Control& Power

Data collection & Control& Power

Global Trigger& Clock

Replugable analog cable(<10m)

PMT

Under water electronics(32ch or 96ch, redundancy)

Digital cable & power cable(80m, redundancy)

Collection & control

Trigger optical linkwater

OpticalEthernet

switch

OpticalEthernetSwitch

Ethernet link

Optical ethernet

Global trigger

Local bypass cable(redundancy)

SOME DETAILS ABOUT SCHEME 3

All parts

Front cables and connector

Splitter

Front electronics and waveform digitizer

Data progressing and temporary storage

Data transfer

Under water electronics box-local box

Backend cables and connector

Trigger system

High voltage system

Low voltage system

16

FRONT END CABLES AND CONNECTOR

The connection between PMT and electronics is

one cable, transfer both signal and HV

Length : 5meters

The requirement for the cable：

Can work on the detector, nether pollute water or

liquid scintillator nor be polluted

Can work at least ten years

Should be the high voltage cable and the attenuation

for the signal with 200MHz bandwidth below 5%

The connector should be watertight, and better with

the ability of under water pluggable

17

SPLITTER

Location is in the local box, used for separate the

HV and signal

The requirement for splitter：

Can work with 3000 V HV

Good matching for the signal

Appropriate discharge time constant to get a good

balance point between the ballistic deficit and

overshoot

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FRONT END ELECTRONICS AND WAVEFORM

DIGITIZING

Key part of the electronics, just behind the splitter

The requirement

Large dynamic range for the front end from 0.5mV to 20V

and good protection for the large signal

Two range

Low range for the single electron-photon detection, the

magnification of front electronics is 1

High range for the large signal (4000p.e.) detection, the

magnification of front electronics is 1/4

The tow range are combined into one after digitizing

One discriminating channel for the analog trigging and

reference time measurement

ADC should be 10bits ENOB

Calibration of electronics from the point after splitter 19

DATA PROCESSING AND TEMPORARY

STORAGE

Just after the waveform digitizing part, traditional structure

Main function

Get the information for trigger system

Combine the two range into one

Do the temporary storage for trigger latency and supernova

Using FPGA for the flexibility of the future change

Two stage

part one, low price FPGA with the enough memory, for 2 ~4 channels

part two, good reliability FPGA for the fiber transfer, for 32 channels

Redundancy design 20

THE ELECTRONICS IN LOCAL BOX OF

SCHEME 3

21

DATA TRANSFER

Using fiber network to transfer data outside

water, and can monitor the situation of the fiber

transfer

Using TCP/IP protocol to connect directly to the

switch and then transfer to DAQ

High reliability design

22

UNDERWATER LOCAL BOX

Each local box connect with 32 PMTs

High reliability required, because no redundancy

design

Can work on the detector, nether pollute water or liquid

scintillator nor be polluted

Watertight design and fill with epoxy for the situation in

case watertight is not work

23

BACKEND CABLE AND CONNECTOR

Using the photoelectric composite cable, about 6

fiber and 6 cables(redundancy)

One connector for each cable and local box, with

is re-pluggable outside water

The length is from 20 meters to 80 meters

Cable definition：

Cable: HV 1x2, LV 1x2, GROUND 1x2

Fiber: Data 1x2, Trigger out 1x2, Control 1x2

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TRIGGER AND CLOCK SYSTEM

Outside water

Can do flexible trigger

Some kinds of trigger

Normal trigger

Supernova trigger

Test trigger or force trigger

25

HIGH VOLTAGE AND LOW VOLTAGE

Tow choice

Using one voltage to front and get HV and LV

separately

Below 48V? Safety voltage

Using two separate HV and LV transfer

Depend on the Ripple of the HV and reliability

The HV is connect to the splitter, between HV and

front end electronics only with one HV capacitor, so

the ripple is easy to couple to the signal, what value

we can tolerate when using the low threshold scheme?

And it also can make the front amplifier saturation

26

SOME POSSIBILITIES

Scheme from Anatael

All fiber system idea and scheme

27

FROM ANATAEL’S SLIDE

28

29

FROM ANATAEL’S SLIDE

30

FROM ANATAEL’S SLIDE

31

FROM ANATAEL’S SLIDE

32

FROM ANATAEL’S SLIDE

33

FROM ANATAEL’S SLIDE

34

FROM ANATAEL’S SLIDE

ALL FIBER SYSTEM IDEA AND SCHEME

Some “new” idea

DWDM(Dense Wavelength Division Multiplexing)

Optical PCB technology

Power transfer by laser?

Basic support

The reliability of the optical system is 25 years

ASIC+FPGA

35

POWER TRANSFER BY LASER

Power transfer by laser

Mature in industry

But too expensive over 2000EURO/ch

36

TRANSFER IN ONE FIBER

DWDM(Dense Wavelength Division Multiplexing)

37

TRANSFER IN ONE FIBER

Product of the DWDM

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OPTICAL PCB

Put the photoconduction inside PCB

Connect the fiber directly to the PCB

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WHAT WE CAN GET FROM THESE?

One local box for 7 PMT

Connect with 2m HV cable

Total 236 local box

Each local box have 2 fiber and 4 power cable connected

Longest 80m, shortest 20m

Total 572 fibers and 1144 power cables

Fiber and power cable not expensive

Each fiber transfer 3 optical channels with DWDM

Redundancy from FE part, good reliability

PMTs of one local box not close to each other 40

LOCAL BOX

41

THE CLUSTER OF PMT FOR ONE LOCAL

BOX

42

SYSTEM

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THE REQUIREMENT FOR ASIC OF JUNO

ELECTRONICS

Schime1 Pre amplifer(DengZhi)

ADC(LiFule,WeiWei)

Schime2 SOC(Achim, Germany)

power ASIC(Dmity, Russia)

Schime3 FE(DengZhi, YanXiongbo)

ADC(LiFule,WeiWei)

power ASIC(Dmitry, Russia)

Schime4 Paris-ROC(Anatel)

power ASIC(Dmity, Russia)

Almost all schemes need the ASIC

The Soc maybe not so far 44

WHAT IS THE FUTURE REQUIREMENT OF

PHYSICAL EXPERIMENT

Maybe

Soc + power ASIC, assembled just close to the output

of detector

Part Soc + FPGA + power ASIC, if we can get more

flexibility

ASIC can driver the laser illuminator directly

Current handling used for the large dynamic range

Front fast sampling instead the analog signal out

So, COME ON, you guys have great future!

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Thanks!