Dk Dong Co Mot Chieu

MC LC Trang

Li m u ....................................................................................................... 4 Chng 1. t vn ..................................................................................... 6

1.1. Bi ton iu khin ng c mt chiu ........................................................... 6 1.1.1. ng c in mt chiu kch t bng nam chm vnh cu ................................ 6 1.1.2. M hnh ha ng c mt chiu ......................................................................... 7 1.1.3. Cu trc iu khin phn hi dng in ............................................................. 8 1.1.4. Gii php thit k b iu khin s ................................................................... 10

1.2. K thut iu ch rng xung PWM v mch cu H .................................. 11 1.2.1. K thut iu ch rng xung PWM .............................................................. 11 1.2.2. Mch cu H ....................................................................................................... 12

1.3. xut cc thnh phn ca h thng iu khin ng c mt chiu ........... 13 Chng 2. Gii thiu chung v cc thnh phn ca h thng .................. 15

2.1. Ngun adapter ............................................................................................... 15 2.2. ng c c gn encoder ................................................................................ 15

2.2.1. ng c thc nghim ........................................................................................ 15 2.2.2. Encoder ............................................................................................................. 16

2.3. Driver L298 ................................................................................................... 17 2.4. in tr shunt ................................................................................................ 19 2.5. Opamp LM324 ............................................................................................... 20 2.6. Cc thit b nhp/xut d liu ....................................................................... 21

2.6.1. Mn hnh LCD 16x2 ......................................................................................... 21 2.6.2. Bn phm nt nhn ............................................................................................ 23 2.6.3. Cng truyn thng RS232 ................................................................................. 25 2.6.4. Chun giao tip SPI v mch np ISP .............................................................. 28

2.7. Vi iu khin ATmega16 ................................................................................ 30 2.7.1. Gii thiu h vi iu khin AVR ...................................................................... 30 2.7.2. Kin trc ca AVR ........................................................................................... 31 2.7.3. ATmega16 ........................................................................................................ 35

Chng 3. Thit k mch phn cng .......................................................... 39 3.1. Cc cng vo/ra ca mch phn cng .......................................................... 39 3.2. Mch driver L298 .......................................................................................... 39 3.3. o tc ng c ......................................................................................... 40

3.4. Mch o dng phn hi ................................................................................. 41 3.5. Mch bo v qu dng .................................................................................. 42 3.6. Khi nt nhn v hin th .............................................................................. 43 3.7. Mch to dao ng bng thch anh .............................................................. 44 3.8. S nguyn l tng hp .............................................................................. 44

Chng 4. Thit k phn mm..................................................................... 45 4.1. Tm hiu cc module ca ATmega16 c s dng ...................................... 45

4.1.1. Cc ngt trong ATmega16 ................................................................................ 45 4.1.2. iu ch rng xung (PWM) vi Timer/Counter1 (T/C1) ............................ 47 4.1.3. To chu k trch mu vi Timer 2 v m xung vi Counter0 ........................ 53 4.1.4. B chuyn i tng t - s (ADC) ................................................................. 56 4.1.5. o tn s tn hiu dng xung vi Input Capture ............................................... 61 4.1.6. Giao tip truyn thng SPI v UART ............................................................... 63

4.2. Xy dng giao din ha ngi dng trn MATLAB ................................. 68 4.3. Ci t phn mm cho vi iu khin ............................................................. 72

4.3.1. Thut ton iu ch in p .............................................................................. 72 4.3.2. Lu thut ton iu khin ............................................................................ 72 4.3.3. Lp trnh C cho AVR vi phn mm CodeVision AVR .................................. 73

Chng 5. Kt qu t c ........................................................................ 75 5.1. Thc nghim .................................................................................................. 75

5.1.1. Phng n thc nghim .................................................................................... 75 5.1.2. Th nghim 1 - Kim tra php o dng ............................................................. 76 5.1.3. Th nghim 2 - Nhn dng hm truyn i tng vng trong .......................... 76 5.1.4. Th nghim 3 - Nhn dng hm truyn i tng vng ngoi .......................... 77 5.1.5. Kt qu thc nghim ......................................................................................... 78

5.2. nh gi v bn lun .................................................................................... 79 5.2.1. Cc kt qu t c ......................................................................................... 79 5.2.2. Hn ch ............................................................................................................. 79

5.3. Tng kt n ............................................................................................... 80 Ti liu tham kho ........................................................................................ 81 PH LC. ...................................................................................................... 82

Sn phm mch phn cng ................................................................................... 82

Li m u

Ngy nay, dng in xoay chiu c s dng rng ri, cng vi l s xut hin ngy cng ph bin ca cc loi my in xoay chiu 3 pha trong nn sn xut hin i. Mc d vy, ng c in mt chiu (CMC) vn ng vai tr quan trng nh nhng u im ni bt v c tnh lm vic, kh nng iu chnh tc bng phng trong phm vi rng, kh nng m my ln v c bit l kh nng qu ti. Trn gc nghin cu, phng php iu khin truyn ng cc loi my in xoay chiu c s dng ch yu vn l iu khin vector theo nguyn l ta t thng rotor, da trn c s nguyn l iu khin CMC. Chnh v vy, iu khin CMC vn l bi ton c bn v quan trng nht, l bc m cc nh nghin cu cng nh ng dng tip cn vi nhng bi ton iu khin cc h thng truyn ng phc tp.

Nguyn tc iu chnh ng c c bn vn l iu chnh in p t ln 2 u mch phn ng (to dng in sinh mmen). Vi s pht trin nhanh chng ca cng ngh bn dn, phng php iu chnh in p trn 2 u ti c s dng ph bin nht l k thut iu ch rng xung (PWM) nhm tn dng cc kh nng u vit ca h thng iu khin s hin i so vi nhng c cu iu p c in. Nhim v c bn ca ngi k s ch cn l thit k gii thut b iu khin tnh ton ra gi tr in p cn iu ch. Vi bi ton iu khin CMC, nhiu lut iu khin c nghin cu p dng, d vy PID vn l phng php c a chung v tnh n gin v hiu qu ca n.

Chnh v nhng l do trn, l nhng sinh vin ngnh iu khin t ng xc nh c hng nghin cu trong nm hc cui l tp trung vo lnh vc iu khin cc loi my in, chng em quyt nh thc hin n 3 vi ti Thit k h thng iu khin ng c mt chiu theo k thut PWM c phn hi dng in trn nn vi iu khin ATmega16 vi mong mun c c nhng kin thc v k nng thc t phc v cho qu trnh hc tp v nghin cu ng dng, c th vn dng tng hp cc l thuyt hc to ra mt sn phm hon chnh, p ng c cc yu cu k thut vi chi ph thp. Quyn n ny l s tng hp cc ni dung cn thit ng vai tr quan trng trong vic nh hng thit k, tng hp qu trnh tm hiu, trao i, phn tch v gii quyt vn ca 3 thnh vin trong nhm, l s ghi nhn ng gp ca tng c nhn vo cng vic chung.

Quyn bo co n c chia thnh 5 chng: - Chng 1. t vn

Chng ny cp n cc trng tm trong bi ton iu khin ng c, tr li cu hi v sao phi phn hi dng in, v v sao phi iu ch rng xung, cc l thuyt no s c p dng vi bi ton iu khin mmen v tc quay, t xut cu hnh c bn ca h thng cn thit k.

- Chng 2. Gii thiu chung v cc thnh phn ca h thng Trn c s cu hnh c xut, tm hiu v cc c tnh k thut v gii php s dng chng trong bn thit k.

- Chng 3. Thit k mch phn cng

Vi nhng tm hiu c trnh by trong Chng 2, cc thit b s c kt ni vi nhau vo trong mt mch phn cng tng hp m kt qu cui cng c th hin trong s nguyn l trc khi chuyn sang thit k mch in.

- Chng 4. Thit k phn mm Nhim v c bn ca chng ny l lp trnh, ci t c thut ton iu khin ng c vo trong vi iu khin ATmega16, vi cc tnh nng h tr nh giao din ha ngi dng, np qua ISP v truyn tin qua cng UART.

- Chng 5. Kt qu t c Ni dung chng trnh by v tin trnh thc nghim v cc kt qu, t a ra nhng nh gi v bn lun, cng nh ch ra mt s hn ch ca n.

c thc hin thnh cng n, chng em xin gi li cm n chn thnh n TS. V Vn H, ngi c nhng hng dn, gip tn tnh cho chng em c v nhng hiu bit thc t cng nh nhng h tr trong qu trnh lm mch phn cng. Mc d c nhm n lc thc hin n vi thi nghim tc c th to ra nhng kt qu tt nht, nhng chc rng mch thnh phm cng nh quyn bo co n kh trnh khi nhng thit st, hn ch. Chng em rt mong nhn c thm nhng gp , ch bo qu bu t cc thy c c th lm tt hn vi nhng sn phm sau ny. Chng em xin chn thnh cm n!

Nhm sinh vin thc hin, ng c Cng, inh Vn Ha, Trn V Trung,

KSTN KT K55

Chng 1. t vn

1.1. Bi ton iu khin ng c mt chiu

1.1.1. ng c in mt chiu kch t bng nam chm vnh cu

ng c in mt chiu (CMC) kch t bng nam chm vnh cu l loi ng c mt chiu kch t c lp m phn cm stator l nam chm vnh cu. Phn ng rotor c cc cun dy qun xung quanh mt li thp v c ni vi ngun in mt chiu. Mt phn quan trng khc ca CMC l b phn chnh lu, n c nhim v i chiu dng in gip cho chuyn ng quay ca rotor l lin tc, thng thng b phn ny gm c mt b c gp v mt b chi than tip xc vi c gp. Cu to v nguyn tc hot ng ca CMC c minh ha bi Hnh 1.

Pha 1: Dng in chy trong mch phn ng sinh ra t trng ca rotor, t trng ny tng tc vi t trng ca nam chm sinh ra mt mmen lm rotor quay.

Pha 2: Khi mt ca cun dy song song vi cc ng sc t, mmen bng 0, rotor tip tc quay theo qun tnh.

Pha 3: Sau mi v tr m ti mmen bng 0, b phn chnh lu s o chiu dng in trong dy qun mmen quay lin tc v ng chiu.

Hnh 1. Cu to v chu trnh cc pha lm vic ca CMC

Tc quay l mc tiu iu khin c bn ca bi ton iu khin ng c. Cc k thut iu khin tc quay ca CMC thng tp trung vo vic tc ng n in p t trn 2 u hoc in tr ca mch phn ng. Trong , k thut iu ch rng xung in p s dng cc b bin i in t cng sut l ph bin hn c nh kh nng tc ng nhanh v c bit l iu khin mm bng vi x l (iu khin s).

1.1.2. M hnh ha ng c mt chiu

Theo [1] cc phng trnh ton hc m t CMC c cho bi cng thc:

- in p phn ng: AA A A A Adi

u e R i Ldt

= + + (1)

- Mmen quay: M M Am k i= (2) - Phng trnh chuyn ng: ( )1

2 M Tdn

m mdt Jpi

= (3)

- Sc in ng cm ng: A ee k n= (4) - Hng s ng c: 2e Mk kpi= (5)

- Hng s thi gian phn ng: AAA

LTR

= (6)

Bin i Laplace cc phng trnh trn, ta thu c m hnh dng s khi m t CMC nh sau:

Hnh 2. M hnh ton hc ca ng c mt chiu

Hm truyn i tng tc ng c:

( )( ) 2

2 22

2 2

1 1 11 2( ) 1 1 11

1 21

2 22 2 1

MA A

CA

e MA A

eM

A A AA A A e M

e M e M

kn s R sT JsG s

u s k kR sT Js

kkR J R T JR T Js R Js k k

s sk k k k

pi

pi

pi pipi pi

+= =

++

= =

+ + + +

Do m hnh i tng tc CMC c hm truyn dng khu bc hai. Da trn s hiu bit y v cc thng s m hnh, ta d dng thit k c mt b iu khin PID cho cht lng iu khin tt. Trong thc t, cc ng c mt chiu c bn trn th trng hin nay rt t khi km theo mt bng thng s chi tit, nu c cng rt s si. Do vy vic xc nh y tt c cc tham s m hnh l mt vic lm kh. Ta thng ch d dng o c cc gi tr in tr, in cm phn ng, vic nhn dng m hnh y phc v cho cng vic tng hp b

iu khin s c tin hnh bng phng php kho st p ng xung thc nghim, vi s h tr ca cng c System Identification Toolbox trong Matlab. Khi , cn thit phi c thm mt cng truyn thng h thng giao tip vi my tnh.

1.1.3. Cu trc iu khin phn hi dng in

Phng trnh chuyn ng (3) cho thy quan h trc tip gia mmen quay v tc . Phng trnh (2) cho thy mi quan h t l gia mmen quay Mm v dng in phn ng

Ai CMC kch thch bng nam cham vnh cu vi t thng kch t l hng s. Nh vy bng vic iu khin Ai cho php ta p t ngay tc thi mmen quay Mm qua p ng tc n l rt nhanh. y cng chnh l tng trong cu trc iu khin tng (cascade control) kinh in ca cc h truyn ng: gm hai vng phn cp vi khu iu chnh tc quay vng ngoi v khu iu chnh dng phn trong (Hnh 3).

Hnh 3. S cu trc iu khin ng c mt chiu C 2 khu iu chnh trong Hnh 3 u c thit k theo cu trc PI m bo p ng nhanh v trit tiu sai lch tnh. Cc thit k b iu khin cho CMC thng da vo 2 phng php (tiu chun ti u) c bn l ti u module v ti u i xng. Trong khi mc tiu ca phng php ti u module l gi tr thc (o c) bm theo gi tr t chnh xc nht (trong mt di tn rng nht) c th, th phng php ti u i xng mong mun a gi tr thc tr li vi gi tr t nhanh nht c th sau khi n b nh bt ra khi v tr cn bng (nng cao tr n nh cho h kn). Vng iu chnh bn trong, i tng phn in c ng hc bin i nhanh, b iu khin ca vng ny thng c thit k theo phng php ti u module. Vng iu chnh bn ngoi, i tng phn c c ng hc bin i chm hn, li thng chu nh hng bi s thay i t ngt ca nhiu ti, do vy ta s dng phng php ti u i xng cho b iu khin tc quay. Lu rng, cc tham s ca cc b iu khin c tnh ton theo hai phng php ny da trn m hnh thu c t cc d liu o c v php c lng, bn cnh cc c tnh c-in ca h thng khng hon ho nh trong l thuyt v c nhng sai khc ty vo ng dng c th. Do , cc thng s b iu khin thu c cng ch l mt gi tr ng tin cy trong ci t ban u, nhng gi tr ny c th s cn c chnh nh thm trong qu trnh thc nghim.

thit k b iu khin dng, sc in ng cm ng Ae thng c b qua, v khi , t (1) v Hnh 3, hm truyn mch in phn ng l mt khu qun tnh bc hai:

( ) ( )*( ) 1/1 1 1( ) ( ) 1 1 1 1

A Ai

A t A A t A

i s RG su s sT R sT sT sT

= = =

+ + + + (7)

Trong , 11 tsT+

l hm truyn ca b bin i. i vi b bin i s dng cc van tn

s ng ct cao, ng hc ca khu ny l rt nhanh v c th b qua, tc l coi 0tT , *

A Au u= . Khi , hm truyn mch phn ng xp x mt khu qun tnh bc nht:

*

( ) ( ) 1/( ) ( ) ( ) 1A A A

iA A A

i s i s RG su s u s sT

= = =

+ (8)

B iu khin dng c thit k theo phng php ti u module l mt khu tch phn I:

( )1 1 ;12 22c PiA

Pi iA

AA

KRK G sKT T sT

R

= = = = (9)

Vi b iu khin dng ( )ciG s thit k nh trn, vng iu chnh dng (vng kn) c hm truyn nh sau:

( )( )* 2 2

1 11 2 2 1 2

Ascli

A A A A

i sG

i s T s T s T s= =

+ + + (10)

Cng vi hm truyn t phn c, i tng iu khin tng qut lc ny l mt khu qun tnh-tch phn bc nht:

( )( )

1 12 1 2 1

Mn

A M

kG sJs T s T s T s

= =

+ + (11)

Trong , 2MM

JTk

=

l hng s thi gian phn c, v 2 AT T = l hng s thi gian thay

th ca vng trong. p dng phng php ti u i xng, ta thu c tham s ca b iu khin tc :

( )

4

2

11

In

MPn

c

n PnIn

T TTKT

G s KT s

=

=

= +

(12)

1.1.4. Gii php thit k b iu khin s

1.1.4.1. Thut ton PID s PID vn lun c coi l b iu khin chun cng nghip v tnh n gin v hiu

qu lm vic ca n. Lut PID trn min thi gian (lin tc) c m t bi cng thc dng chun tc:

( ) ( ) ( )( )

0

1 tp d

i

de tu t K e t e d T

T dt

= + + (13)

Hoc dng song song:

( ) ( ) ( )( )

0

t

p i dde t

u t K e t K e d Kdt

= + + (14)

Do cc b iu khin s lm vic vi cc tn hiu gin on (discrete-time) theo thi gian trch mu, nn c th ci t c lut PID vo vi iu khin, ta phi chuyn cng thc (13) v dng cng thc sai phn bng cc php xp x khu tch phn (I) v khu vi phn (D). Cc thut ton PID s dng trong iu khin s ch khc nhau bi n lc thc hin php xp x 2 thnh phn ny, tc l khc nhau chnh xc.

Thut ton PID s n gin nht s dng cng thc sai phn sau [2]: 1 0 1 1 2 2k k k k ku u r e re r e = + + + (15)

Trong , 0 1 dpT

r KT

= + , 1

21 dpi

T Tr K

T T

= + , 2

dp

Tr K

T= , vi T l chu k trch

mu tn hiu. Cng thc cho mt s trng hp ring: - B iu khin I:

1 1 1

1

k k k

i

u u re

r TK = +

= (16)

- B iu khin PI:

1 0 1 1

0 1, 1

k k k k

p pi

u u r e re

Tr K r K

T

= + +

= =

(17)

1.1.4.2. Gii php iu khin khi hng s thi gian mch in phn ng qu nh B iu khin trong thc t lun mt mt khong thi gian x l tn hiu v tnh

ton trc khi a ra tn hiu iu khin, tc l tc ng iu khin chm hn so vi thi im bt u trch mu. Nu khong thi gian tr iu khin ny nh hn 1/10 hng s thi gian b nht ca i tng iu khin, ta c th b qua n v thut ton iu khin s m bo cho cht lng mong mun. Nhng nu i tng c thnh phn ng hc bin i

qu nhanh so vi kh nng tnh ton ca vi iu khin, cc hng s thi gian qu nh tng ng s c b qua khi thit k b iu khin, v ta khng c kh nng tng hp c mt vng iu chnh kn m ng hc ca n li c th nhanh hn c c mt chu k ly mu.

Trong nhiu ng dng iu khin ng c, mch phn ng c in cm rt nh so vi in tr, dn n hng s thi gian in nh ch c vi trm s, trong khi thi gian thc thi cc lnh tnh ton trc khi a c ra tn hiu iu khin (c th l duty cycle trong PWM) ln hn ng k (c vi ms). Khi , cu trc b iu khin dng c la chn vn l mt khu tch phn (I), nhng cng thc (9) khng cn c s dng tnh h s iK na, m thay vo , hm truyn t vng iu chnh dng s tr thnh mt khu qun tnh bc nht vi hng s thi gian t l nghch vi iK , ngha l iK cng ln th dng in bm tn hiu t cng nhanh. Tuy nhin, iK ln s dn n nguy c a in p iu khin nhanh chng vo vng bo ha (gi tr gii hn in p), tc l vng m i tng iu khin khng cn tuyn tnh na, tnh n nh ca h kn v th khng cn c m bo. Do , iK nn c chn va phi nu khng yu cu p ng iu khin mmen qu nhanh. Hm truyn t tng hp ca i tng vng ngoi vn l mt khu qun tnh tch phn bc nht, b iu khin tc vn c la chn theo cu trc PI v thit k theo nguyn l ti u i xng nh cng thc (12).

1.2. K thut iu ch rng xung PWM v mch cu H

1.2.1. K thut iu ch rng xung PWM

Mt trong nhng phng php n gin m hiu qu thay i in p t ln phn ng ng c l s dng k thut iu ch rng xung (PWM Pulse Width Modulation).

Hnh 4. Nguyn l iu ch rng xung PWM

Nhn thy Hnh 4, gi tr trung bnh in p trn ti:

max *on

ton off

T Duty cycleU U AmplitudeT T period

= =

+ (18)

Ta thy gi tr in p trn ti ph thuc vo t s /Duty cycle period = . Do , ng vi mi tn s xung period , ta c th iu chnh Duty cycle iu chnh in p t ln phn ng ng c. Ch : Khi la chn tn s ca xung PWM, ta cn la chn sao cho p ng c hc ca ng c mn khng c cm gic b vp do in p thay i. ng thi chu k xung iu ch phi nh hn hng s thi gian mch in phn ng in cm trong mch thc s c tc dng lm cho dng in khng b gin on.

1.2.2. Mch cu H

Tn hiu PWM xut t vi x l khng dng cp trc tip cho ng c c, v vy ta cn s dng mt mch trung gian c th cung cp p v dng cho ng c. Mt khc chiu quay ca CMC ph thuc vo cc m v dng ca ngun c ni vo pha no trn phn ng ca ng c, do mun i chiu quay ca ng c ta cn i cc ni vo phn ng. Mch cu H c xy dng nh l mt gii php hiu qu cho c 2 vn ny.

Hnh 5. S nguyn l ca mch cu H Mch cu H l t hp 4 kha in t cng sut, c mc nh s Hnh 5, nguyn l hot ng ca mch ny nh sau: - Cng vi mc in p V th khi cng tc L1 v R2 ng s cho i tng ng c

chy ngc chiu so vi khi cng tc L2 v R1 cng ng. Tuy nhin, vic ng ct ny tuyt i khng L1 v L2, hoc R1 v R2 cng ng v s xy ra ngn mch nguy him cho ngun. Chnh v vy, i km vi mch cu H s c nhng b iu khin sao cho nhng cp cng tc ny khng th cng ng.

- Gi thit rng, ng c chy vi vn tc nh mc khi c cung cp ngun nh mc vi L1, R2 ng v L2, R1 m. R rng, khi R2 c c nh ng nguyn v L1 c cho ng ct vi vi thi gian Duty cycle trong chu k period , nh vy

in p trung bnh c t ln u ng c s l: *tDuty cycleU V

period= .

Cc kha L1, L2, R1, R2 phi chu tn s ng ct PWM ln ti hng KHz nn chng thng l cc van bn dn c iu khin loi FET, MOSFET, IGBT, BJT cng sut.

1.3. xut cc thnh phn ca h thng iu khin ng c mt chiu

- C cu chp hnh: Mch cu H thc cht l t hp ca cc van cng sut, 2 tiu ch la chn mch van ch yu l dng ti a v tn s ng ct ti a m loi van c th chu. Da vo tnh ton v datasheet ca cc sn phm trn th trng, nhm s dng Chip driver L298 c tch hp sn mch cu BJT bn trong li ng c. - Thit b o: + Tc quay c o bng encoder c sn gn vi v ng c. + Dng in mt chiu c o bng in tr shunt, khuch i tn hiu t shunt bng LM324, l loi OPAMP gi r v ch i hi ngun n. - B iu khin: Thut ton iu khin phi c ci t trn mt vi iu khin p ng c cc yu cu:

+ C module PWM chuyn dng iu khin ng c; + C thm 2 Timer/Counter v 1 chn ngt ngoi x l tn hiu xung encoder v

to chu k trch mu. + C Module ADC chuyn i tn hiu tng t thu c t in tr shunt sang

tn hiu s, phc v cho vic ly gi tr dng phn hi; + Bn cnh cc chc nng c bn cn c k trn, cc yu t v tc tnh ton, mc

thng dng, gi thnh cng c xt n. AVR Atmega 16 l vi iu khin c nhm la chn, p ng y cc tiu ch trn. - Thit b nhp/xut d liu:

+ Khi nt nhn: gm 4 nt Start/Stop, Up, Down, Reverse + Mn hnh hin th LCD 16x2 + Cng truyn thng RS232

Bng 1. Cc thit b nhp/xut d liu v chc nng

Thit b Chc nng

Nt Start/Stop Khi ng v dng ng c

Nt Up Tng gi tr Setpoint

Nt Down Gim gi tr Setpoint

Nt Reverse o chiu ng c

LCD 16x2 Hin th tc , dng, tn hiu iu khin, cng nh sai lch

Cng RS232 Truyn tn hiu ln my tnh nhn dng v nh gi cht lng

Hnh 6. S cu trc xut ca h thng iu khin CMC

Chng 2. Gii thiu chung v cc thnh phn ca h thng 2.1. Ngun adapter

Mc tiu ca n hng n l gii quyt bi ton iu khin ng c, v vy s khng thit k mch ngun adapter m s dng mch ngun c sn. Thng s ca ngun c s dng:

- in p u vo: 220VAC - in p u ra: 12VDC, 5VDC, 3.3VDC - Dng u ra: 1A

2.2. ng c c gn encoder

2.2.1. ng c thc nghim

ng c mt chiu c s dng trong n l Servo Motor C6680 60025 c trong my in HP Scanjet 8250 do hng HP ch to, vi cc thng s c bn nh sau:

- in p lm vic: 3 24V DC. nh mc 12V DC. - Dng in khng ti nh mc: 80mA. - Tc khng ti nh mc: 4000 vng/pht. - Incremental Encoder: 888 xung/vng.

ng c c cp in v iu khin thng qua 6 dy ni vi header 2.0mm 6P ca board mch ng c, bao gm 4 dy tn hiu mch iu khin v 2 dy mch ng lc c phn bit bi cc mu sc khc nhau theo th t sau:

Dy mch iu khin: - Mu en : GND - Mu Da cam: Knh Encoder B - Mu : +5V - Mu Vng: Knh Encoder A

Dy mch lc: - Mu Xanh L: DC- - Mu Nu : DC+

Hnh 7. Hnh nh thc t ca ng c Servo s dng trong n

2.2.2. Encoder

Encoder l thit b xc nh tc quay ca ng c s dng phng php s (digital). Ngoi ra, cn c phng php tng t (analog) nh s dng tachometer. y, vic s dng encoder tin dng hn c vi l do h thng iu khin l s, ng thi ta c th va xc nh tc quay, gc quay v c chiu quay. V vy, hu ht cc loi ng c bn sn trn th trng u c tch hp mt encoder 3 u ra.

Hnh 8. Cu to ca encoder Hnh 9. Encoder vi 2 knh A, B

Cu to ca encoder c ch ra Hnh 8 bao gm mt ngun pht quang (thng s dng ngun hng ngoi), mt cm bin quang nhn tn hiu v mt a c chia rnh ngn cch. a chia rnh cng nhiu ng ngha tn hiu xung pht v cng nhiu trong 1 vng quay, tc l phn gii ca gc quay v chnh xc ca tc quay cng cao. Tuy nhin, iu ny ng ngha vi vic tc x l ca trung tm iu khin phi nhanh mt cch tng ng no , v ngoi cng vic ny, trung tm x l phi iu khin nhng tc ng khc.

Ngoi ra, encoder thng c to ra vi 3 knh tn hiu gm: knh A, B v I, vi cc c th ring. Knh I l tn hiu c to ra bi 1 vng quay ca trc ng c, c mi vng s c 1 xung ra knh I (Hnh 8). Trong khi , knh A v B tng t knh I nhng s xung xut hin trn 2 knh sau mi vng quay ca ng c l N xung (ph thuc vo nh sn xut) cng l s rnh - c gi l phn gii ca encoder. Knh A c t lch so vi knh B mt s nguyn ln rnh cng vi na rnh. iu ny khin cho tn hiu t knh B c cng tn s ca knh A nhng lch pha 90o (Hnh 9). y chnh l c s xt xem ng c ang chy thun hay chy ngc. Hnh 9 th hin v tr hai cm bin knh A v B lch pha nhau v cho tn hiu xung nh hnh v. Nhn thy:

- Khi ng c quay theo chiu kim ng h, ti tn hiu sn xung ca knh A cho ta gi tr bng 0 ca knh B.

- Ngc li, khi ng c quay ngc chiu kim ng h, tn hiu sn xung ca knh A cho gi tr 1 ca knh B.

Nh vy, khi kt hp vic m s xung to ra bi knh A trong khong thi gian c nh ng thi xc nh tn hiu ca knh B s cho ta bit ng thi tc , cng nh chiu quay ca ng c.

2.3. Driver L298

L298 l vi mch tch hp 2 mch cu H trong cng mt v, thch hp vi mc logic TTL tiu chun, dng li cc ti cm nh cun r-le, ng c mt chiu, ng c bc...

Hnh 10. S kt ni chn ca L298 L298 s cn 2 ngun cp: 1 ngun Vss cp cho cc mch logic a ra tn hiu ng/m van, 1 ngun Vs cp cho mch lc c kt ni vi cc chn Ouputs u ra. Cu trc ca mt IC L298N c th hin trong Hnh 11. Mi mch cu trong L298 c 1 u vo Enable cho php kch hot mch cu hot ng, khi van no dn van no kha s ty thuc vo 2 tn hiu u vo Inputs. Cc E ca cc van nhnh di c ni vi nhau v u cc tng ng vi im ni chung ny c th c ni vi mt in tr

shunt ngoi o dng, in tr ny (cng vi 2 t 100nF chng nhiu ngun) c khuyn ngh t gn vi chn GND ca IC. Trong nhng ng dng khng cn n phn hi dng, cc chn cc emitter ni chung s c ni trc tip vi GND. Trong ng dng cho iu khin CMC (Hnh 12), vi mc tiu bo v ng c qu p v iu khin ng c chy theo c 2 chiu thun nghch v c hm, ta s dng thm mt mch cu diode bo v, yu cu l loi diode phc hi nhanh (trr 200ns) v chu c dng 1A. Khi cn dng ti ln ti trn 2A, c th s dng cu hnh song song (Hnh 13) tng dng cho ng c.

Hnh 11. S cu trc ca L298

Hnh 12. ng dng L298 trong iu khin CMC

Hnh 13. Cu hnh kt ni song song tng dng ca L298

2.4. in tr shunt

in tr shunt l loi in tr c bit c dng rng ri trong cc ng dng o dng in mt chiu, thng c ch to bng manganin l vt liu t thay i gi tr in tr theo nhit hn ch sai s trong qu trnh o. Shunt c mc ni tip vi ti dng cn o chy qua n, s st p trn shunt t l vi dng in v do tr s in tr bit, php o in p ri trn shunt s cho bit gi tr dng ti.

Hnh 14. Hnh dng ca cc loi in tr miliohm lm shunt thng dng

khng nh hng ng k n mch in, in tr shunt thng c tr s rt nh, vo c vi m (miliohm resistors). Khi chn in tr shunt, bn cnh v tr s Ohm ca in tr, ngi ta cn quan tm n dng nh mc qua in tr (dng ti a o c) v chnh xc ca in tr . Hnh dng v c im ca cc loi in tr miliohm thng dng trn th trng c th hin trong Hnh 14 v Bng 2.

Bng 2. Thng s ca cc in tr miliohm lm shunt thng dng

d (mm) Max Current Rating (A) Resistance Range (m) 0.4 2.0 70 ~ 150

0.5 2.5 50 ~ 150

0.6 3.0 50 ~ 100

0.7 4.0 20 ~ 70

0.8 4.5 10 ~ 50

0.9 5.0 10 ~ 40

1.0 5.5 6 ~ 30

1.2 7.0 5 ~ 20

1.4 8.0 5 ~ 20

1.6 9.5 3 ~ 15

1.8 10 3 ~ 10

2.0 12 3 ~ 10

2.5. Opamp LM324

LM324 l mt IC khuch i thut ton, cng sut thp bao gm 4 b khuch i thut ton (Op-Amp) trong n (Hnh 15).

(a) (b) Hnh 15. Hnh nh thc t v s chn ca LM324N

Thng thng mt b khuch i thut ton (Op-Amp) th cn phi c ngun i, tc l phi c ngun dng (+Vcc), t (GND) v ngun m (-Vcc), chng hn nh Opamp 741. Tuy nhin cc Opamp trong LM324 c thit k c bit s dng vi ngun n, tc ch cn Vcc v GND l .

LM324 c th c dng rng ri trong hu ht cc ng dng mch khuch i thut ton c bn, bao gm c mch so snh. Tuy nhin cn lu rng khi c cp ngun n, cc opamp s khng th hot ng ch khuch i o, v ch so snh, in p u ra s thp hn Vcc do s st p trn cc bng transistor (Hnh 16).

Hnh 16. S cu trc ca LM324

2.6. Cc thit b nhp/xut d liu

2.6.1. Mn hnh LCD 16x2

LCD (Liquid Crystal Display) - mn hnh tinh th lng - l loi thit b hin th cu to bi cc t bo (cc im nh) cha tinh th lng c kh nng thay i tnh phn cc ca nh sng v do thay i cng nh sng truyn qua khi kt hp vi cc knh lc phn cc. Chng c u im l phng, cho hnh nh sng, chn tht v tit kim in. Ngy nay, thit b hin th LCD c s dng trong rt nhiu cc ng dng ca VK. LCD c rt nhiu u im so vi cc dng hin th khc: kh nng hin th k t a dng, trc quan (ch, s v k t ha), d dng a vo mch ng dng theo nhiu giao thc giao tip khc nhau, tn rt t ti nguyn h thng v gi thnh r...

C nhiu loi LCD vi nhiu hnh dng v kch thc khc nhau, nhng kh thng dng l LCD 16x2. Vi 2 hng, mi hng 16 k t. Khi sn xut LCD, nh sn xut tch

hp chp iu khin bn trong lp v v ch a ra cc chn giao tip cn thit. Cc chn ny c nh s th t v t tn nh Hnh 18.

Hnh 17. Hnh nh thc t ca LCD 16x2

Hnh 18. S chn LCD

Bng 3. ngha cc chn ca LCD Pin K hiu Ngha 1 Vss Chn ni t cho LCD, khi thit k mch ta ni chn ny vi

GND ca mch iu khin

2 VDD Chn cp ngun cho LCD, khi thit k mch ta ni chn ny vi VCC = 5V ca mch iu khin

3 VEE iu chnh tng phn ca LCD.

4 RS Chn chn thanh ghi (Register select). Ni chn RS vi logic 0 (GND) hoc logic 1 (VCC) chn thanh ghi. + Logic 0: Bus DB0-DB7 s ni vi thanh ghi lnh IR ca LCD ( ch ghi - write) hoc ni vi b m a ch ca LCD ( ch c - read) + Logic 1: Bus DB0-DB7 s ni vi thanh ghi d liu DR bn trong LCD.

5 R/W Chn chn ch c/ghi (Read/Write). Ni chn R/W vi logic 0 LCD hot ng ch ghi, hoc ni vi logic 1 LCD ch c.

6 E Chn cho php (Enable). Sau khi cc tn hiu c t ln bus DB0-DB7, cc lnh ch c chp nhn khi c 1 xung cho php ca chn E. + ch ghi: D liu bus s c LCD chuyn vo(chp nhn) thanh ghi bn trong n khi pht hin mt xung (high-to-low transition) ca tn hiu chn E. + ch c: D liu s c LCD xut ra DB0-DB7 khi pht hin cnh ln (low-to-high transition) chn E v c LCD gi bus n khi no chn E xung mc thp.

7 - 14 DB0 - DB7

Tm ng ca bus d liu dng trao i thng tin vi MPU. C 2 ch s dng 8 ng bus ny : + Ch 8-bit : D liu c truyn trn c 8 ng, vi bit MSB l bit DB7. + Ch 4 bit : D liu c truyn trn 4 ng t DB4 ti DB7, bit MSB l DB7.

15 Ngun dng cho n nn.

16 GND cho n nn.

2.6.2. Bn phm nt nhn

Nt nhn (Push Button) l linh kin c kh, s dng kim loi c tnh n hi cao lm tip im, c gi trong mt v cng bng nha hoc kim loi, to ra tn hiu logic nhm iu khin mt hoc mt vi qu trnh hay my mc. Cc b mt thng l phng hoc to hnh ph hp vi ngn tay hoc bn tay con ngi, d dng n hoc th ra. Nt nhn l hnh thc ra lnh ph bin nht trn th gii, xut hin trong hu ht mi thit b, vt dng nh thang my, my tnh cm tay, in thoi, bn phm, chung, v trong rt nhiu thit b gia nh hay cng nghip.

Hnh 19. Mt s loi nt nhn, cng tc thng c s dng

C nhiu loi nt nhn vi nhiu chng loi, kch thc (Hnh 19) v nguyn l hot ng khc nhau ty thuc vo mc ch s dng. Hnh 20 a ra mt cch kt ni nt nhn vi cc module khc, c bit l kt ni vi u vo tch cc thp ca cc vi iu khin, s dng mt in tr treo R. Theo l thuyt, u ra OUT s mang gi tr in p 0V khi nt c nhn, v 5V khi nh ra.

Hnh 20. S nguyn l kt ni phm bm thng thng

Do bn cht l s tip xc c kh do n hi nn khi cc tip im tip xc vi nhau, xy ra hin tng cc tip im dao ng trc khi n nh. Tn khoa hc ca hin tng ny l Switch bounce (Rung phm). Hin tng ny lm cho nt nhn b on off lin tc thm vi ln na mc d ngi s dng ch nhn th c ng mt ln, v vn ny s gy ra sai lch gi tr logic nh trn Hnh 21.

Hnh 21. p ng u ra hin tng rung phm (Switch bounce)

Debounce l tn gi ca cch gii quyt hin tng rung phm ny. C hai cch Debounce:

- Cch th nht (Debouncing in Software): lp trnh xc nhn s kin nhn nt, tr mt khong thi gian thch hp m bo tn hiu logic thu c l chnh xc.

- Cch th hai (Debouncing in Hardware): s dng phn cng l cc linh kin analog hoc IC s loi b hin tng dao ng ca tn hiu ra.

2.6.3. Cng truyn thng RS232

Vi mc ch phc v cho vic nhn dng m hnh tng hp b iu khin, h thng nht thit phi c thm mt cng truyn thng c th truyn s liu ln my tnh. Chun giao tip c coi l n gin v d dng l RS232. Hu ht cc h thng, thit b u c giao tip vi my tnh thng qua chun ny. Qu trnh d liu ca chun RS232:

Hnh 22. Qu trnh truyn k t A Qu trnh truyn v nhn d liu qua cng ni tip RS232 c thc hin khng

ng b, ch cn mt ng truyn cho mt qu trnh v d liu c truyn theo khung d liu c chun ha bi cc thit b nn khng cn ng xung nhp bo trc d liu n. B truyn gi mt bit bt u (Start bit) thng bo cho b nhn bit mt k t s c gi n trong ln truyn bit tip theo. Start bit lun bt u bng mc 0. Tip theo l cc bit d liu (data bits) c gi di dng m ASCII (7 hay 8-bit d liu). Sau c th l mt Parity bit (bit kim tra chn, l). V cui cng l bit dng (Stop bit c th l 1, 1.5 hay 2 bit dng). Qu trnh truyn k t A c minh ha Hnh 22.

Tc bit c nh ngha l s bit truyn c trong thi gian 1 giy. Tham s ny phi c thit lp bn pht v bn nhn l nh nhau (gia vi iu khin v my tnh phi chung nhau 1 tc truyn bit). Ngoi tc bit cn mt tham s m t tc truyn l tc Baud. Tc Baud lin quan n tc m phn t m ha d liu c s dng din t bit c truyn cn tc bit th phn nh tc thc t m cc bit c truyn. V mt phn t bo hiu s m ha mt bit nn khi hai tc bit v tc baud l phi ng nht. Mt s tc Baud thng dng: 50, 75, 110, 150, 300, 600, 1200, 2400, 4800, 9600, 19200, 28800, 38400, 56000, 115200bps. Khi s dng chun ni tip RS232 th yu cu thi gian chuyn mc logic khng vt qu 4% thi gian truyn 1 bit. Do vy, nu tc bit cng cao th thi gian truyn 1 bit cng nh, thi gian chuyn mc logic cng phi nh. iu ny lm gii hn tc Baud v khong cch truyn.

Parity bit dng kim tra li trn ng truyn. Mt bit c b sung vo d liu c truyn cho thy s lng cc bit "1" c gi trong mt khung truyn l chn hay l. Nu s bit 1 l l, Parity bit l 1. Ngc li, s bit 1 l chn, Parity bit l 0. Bng phng thc ny ch c th tm ra mt s l bit b li, nu nh s bit chn c mc li th

Parity bit s trng gi tr vi trng hp khng mc li v th khng pht hin ra li. Do , trong k thut m ha li ny khng c s dng trong trng hp c kh nng mt vi bit b mc li. Cc c tnh vt l v k thut ca chun RS232:

RS 232 s dng phng thc truyn thng khng i xng, s dng tn hiu in p chnh lch gia mt dy dn v t. Do , ngay t u tin ra i n mang v li thi ca chun TTL. Mc in p logic ca chun RS232:

Mc logic 0 : +3V -> +12V Mc logic 1 : -12V -> -3V

Cc mc in p trong phm vi t -3V n 3V l trng thi chuyn tuyn, khng c nh ngha. Trong trng hp thay i gi tr logic t thp ln cao hoc t cao xung thp, mt tn hiu phi vt qua qung qu trong mt thi gian ngn hp l. iu ny dn n vic phi hn ch v in dung ca cc thit b tham gia v ca c ng truyn. Tc truyn dn ti a ph thuc vo chiu di ca dy dn. a s cc h thng hin nay ch h tr vi tc 19.2 kbps. Cc c tnh in hc khc:

Chiu di cc i: 15m (khng dng Model) Tc d liu cc i: 100kbps Cc gi tr tc truyn d liu chun: 50, 75, 110, 750, 300, 600, 1200, 2400,

4800, 9600, 19200, 28800, 38400, 56600,115200bps Tr khng ti: 3k-7k in dung li vo:

Chn 3: TXD (Transmit Data): ng gi d liu. Chn 4: DTR (Data Terminal Ready): Bo DTE sn sng. Chn DTR thng

trng thi ON khi thit b u cui sn sng thit lp knh truyn thng (t ng quay s hay t ng tr li). DTR trng thi OFF ch khi thit b u cui khng mun DCE ca n chp nhn li gi t xa.

Chn 5: GND (Ground): t ca tn hiu. Chn 6: DSR (Data Set Ready): Bo DCE sn sng, ch tr li, 1 tone tr li

v DSR ON sau 2 giy khi Modem nhc my. Chn 7: RTS (Request To Send): ng RTS kim sot chiu truyn d liu. Khi

mt trm cn gi d liu, n ng mch RTS sang ON bo hiu vi Modem ca n.

Chn 8: CTS (Clear To Send): Khi CTS chuyn sang ON, Modem xc nhn l DTE c th truyn s liu. Qu trnh ngc li nu i chiu truyn s liu.

Chn 9: RI (Ring Indicator): Khi Modem nhn c tn hiu chung, RI chuyn ON/OFF mt cch tun t vi chung in thoi bo hiu cho trm u cui. Tn hiu ny ch th rng mt Modem xa yu cu thit lp lin kt dial-up.

S ghp ni RS232 dng IC max232 Khi thc hin giao tip vi vi iu khin, ta phi dng thm mch chuyn mc logic t TTL sang RS232 v ngc li. Vi mch thng s dng l MAX232 ca Maxim, y l IC chy n nh v c s dng ph bin trong cc mch giao tip chun RS232. Tch hp trong hai knh truyn cho chun RS232 nhng gi thnh ca Max232 tng i ph hp. Mi u truyn ra v cng nhn tn hiu u c bo v chng li s phng tnh in. Ngoi ra Max232 cn c thit k vi ngun cung cp l +5VDC nn c th thit k trn cng 1 mch vi cc linh kin CMOS khc. Mch giao tip nh sau:

Hnh 24. S ghp ni RS232 dng IC max232

2.6.4. Chun giao tip SPI v mch np ISP

Serial Peripheral Interface (hay SPI bus) l mt chun truyn thng ni tip tc cao do hng Motorola xut. y l kiu truyn thng Master Slave, trong c mt chip Master iu phi qu trnh truyn thng v cc chip Slaves c iu khin bi Master, v th truyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn song cng (full duplex) ngha l ti cng mt thi im qu trnh truyn v nhn c th xy ra ng thi. SPI i khi c gi l chun truyn thng 4 dy v c 4 ng giao tip trong chun ny l SCK (Serial Clock), MISO (Master Input Slave Output), MOSI (Master Ouput Slave Input) v SS (Slave Select). Hnh 1 th hin mt kt SPI gia mt chip Master v 3 chip Slave thng qua 4 ng. SCK: Xung gi nhp cho giao tip SPI, v SPI l chun truyn ng b nn cn 1 ng gi nhp, mi nhp trn chn SCK bo 1 bit d liu n hoc i. y l im khc bit vi truyn thng khng ng b m chng ta bit trong chun UART. S tn ti ca chn SCK gip qu trnh tuyn t b li v v th tc truyn ca SPI c th t rt cao. Xung nhp ch c to ra bi chip Master. MISO Master Input / Slave Output: nu l chip Master th y l ng Input cn nu l chip Slave th MISO li l Output. MISO ca Master v cc Slaves c ni trc tip vi nhau. MOSI Master Output / Slave Input: nu l chip Master th y l ng Output cn nu l chip Slave th MOSI l Input. MOSI ca Master v cc Slaves c ni trc tip vi nhau. SS Slave Select: SS l ng chn Slave cn giap tip, trn cc chip Slave ng SS s mc cao khi khng lm vic. Nu chip Master ko ng SS ca mt Slave no xung mc thp th vic giao tip s xy ra gia Master v Slave . Ch c 1 ng SS trn mi Slave nhng c th c nhiu ng iu khin SS trn Master, ty thuc vo thit k ca ngi dng.

Hnh 25. Giao din SPI

In System Programming (ISP) l kh nng ca mt s thit b logic kh trnh, vi iu khin hay mt s thit b nhng c th c lp trnh khi ci t trong mt h thng hon chnh thay v phi lp trnh trc khi ci t n vo h thng. ISP cho php lp trnh (np) hoc lp trnh li cho hu ht cc loi vi iu khin AVR, s dng giao tip chun 3 dy SPI, gip tit kim thi gian, tin bc trong c thit k ln lp trnh.

Hnh 26. S chn np ISP s dng Header 2x5

Mch np ISP h tr hu ht cc vi iu khin thuc h AVR v mt s chip thuc h 89S. Khi np th vi iu khin trong mch np lun ng vai tr nh Master, v vi iu khin cn np ng vai tr nh Slave. Chip Master s dng clock cho kt ni t chn SCK. Ti mi xung clock, 1 bit c truyn t mch np (Master) ti vi iu khin ch (Slave) thng qua chn Master Out Slave In (MOSI). ng thi, cng ti mi xung clock, 1 bit c truyn t Slave sang Master thng qua chn Master In Slave Out (MISO). Chn Reset (RST) c s dng tin hnh xa b nh chip Slave (Chip Erase).

2.7. Vi iu khin ATmega16

2.7.1. Gii thiu h vi iu khin AVR

AVR l h vi iu khin c dng kh ph bin hin nay, vi nhng c im chnh ni bt nh sau:

+ Phng php thit k RISC (Reduced Instruction Set Computer) vi hu ht cc lnh c chiu di c nh, truy nhp b nh np-lu tr, v 32 thanh ghi a nng.

+ Kin trc ng ng lnh kiu 2 tng (two-stage instruction pipeline) cho php lm tng tc thc thi lnh.

+ C cha nhiu b phn ngoi vi ngay trn chip, bao gm cng I/O s, b bin i ADC, b nh EEPROM, b nh thi UART, b nh thi RTC, b iu ch rng xung (PMW)

+ Hu ht cc lnh, tr lnh nhy v np/lu tr u c thc thi trong 1 chu k xung nhp.

+ Hot ng vi tc ng h n 12MHz. Xung nhp do b dao ng to ra cng chnh l xung nhp ca h thng, khng h phi cho qua b chia tn. Kt hp vi kh nng thc hin lnh trong 1 chu k xung nhp, vi iu khin AVR c th t ti tc x l 12MPIS.

+ B nh chng trnh v d liu c tch hp ngay trn chip. Trn chip AVR c ti 3 cng ngh b nh chip khc nhau: EPROM, EEPROM hay PROM, RAM tnh (SRAM).

+ Kh nng lp trnh c. Ngoi tp lnh ca AVR ln n 133 lnh th AVR cn c h tr ngn ng lp trnh bc cao, chng hn ngn ng C.

+ c ng v vi t 8 n 64 chn thch hp vi nhiu ng dng khc nhau. + Tc x l ln hn n 12 ln so vi cc h vi iu khin CISC (Complex

Instruction Set Computer) thng thng. + Lm vic vi di rng in p ngun cp, t 2,7V n 6V.

Vi iu khin AVR do hng Atmel (Hoa K) sn xut, c gii thiu ln u nm 1966 Mt s chip AVR thng dng:

AT90S1200 Attiny10 Atmega8






AT90C8534 Attiny28 Atmega64

Atmega86RF410

Hnh 27. Hnh nh mt s vi iu khin AVR thng dng

2.7.2. Kin trc ca AVR

AVR s dng kin trc Harvard, tch ring b nh v cc bus cho chng trnh v d liu.

Hnh 28. S kin trc tng quan ca AVR a) ALU (khi s hc logic) Lm vic trc tip vi cc thanh ghi chc nng chung. Cc php ton c thc hin ch trong mt chu k xung clock. Hot ng ca ALU c chia lm 3 loi: S hc (arithmetic), L-gc (logical) v cc hm Bit (bit-functions).

b) Thanh ghi lnh: Thanh ghi lnh ni vi tp thanh ghi bng cch la chn xem thanh ghi no s c ALU s dng thc thi lnh. Li ra ca thanh ghi lnh c gii m bng b gii m lnh quyt nh chn tn hiu iu khin no s c kch hot hon thnh lnh hin ti.

c) B nh chng trnh: B nh chng trnh l loi b nh flash. Dung lng chnh xc ca b nh ny thay i khc nhau gia cc b x l trong cng h. B nh chng trnh bn cnh cc lnh lu tr, cng cha cc vector ngt bt u a ch $0000. B nh chng trnh c chia thnh 5 phn khc nhau:

Tp thanh ghi: Mt tp thanh ghi vi 32 thanh ghi c rng 8-bit. Tt c cc b iu khin h AVR u c tp thanh ghi ny. Cc thanh ghi c t tn t R0 n R31. Tp thanh ghi c chia thnh 2 phn mi phn c 16 thanh ghi nh s t R0 ti R15 v t R16 n R31. Tt c cc lnh thao tc trn cc thanh ghi u c th truy nhp trc tip v truy nhp trong chu trnh n n tt c cc thanh ghi. Nhng c ngoi l l cc lnh BSCI, SUBI, CPI, ORI cng nh lnh WI, cc lnh ny ch tc ng n cc thanh ghi t R16 n R31. Thanh ghi R0 n R31 c cc chc nng b sung. Thanh ghi R0 c dng trong cc lnh np b nh chng trnh LPM (Load Program Memory), trong khi cc thanh ghi t R26 n R31 c s dng lm cc thanh ghi con tr. Cc thanh ghi con tr ny c s dng trong nhiu lnh gin tip dng cho thanh ghi.

Hnh 29. Tp thanh ghi ca AVR

64 thanh ghi vo/ra (I/O), mi thanh 8-bit: Tt c cc b x l khng phi u c ng 64 thanh ghi. Mt s trong c nhiu hn s cn li ty thuc vo s cc b phn ngoi vi c trn chip . Cc thanh ghi vo/ra ny thc cht l mt phn ca b nh SRAM trn chp v c th c truy nhp hoc c th nh b nh SRAM vi cc a ch gia $20 v $5F hoc nh cc thanh ghi I/O vi c a ch gia $00 v $3F. Tuy nhin hu ht cc thanh ghi ny thng c trao i nh cc thanh ghi I/O ch khng phi nh b nh SRAM.

B nh SRAM bn trong: B nh ny c trn hu ht cc b x l AVR, ch tr cc b x l loi c s (baseline). Dung lng b nh ny thay i t 128 byte n 4 kbyte. B nh SRAM c s dng cho ngn xp cng nh lu tr cc bin. Trong thi gian c ngt v gi on chng trnh, gi tr hin ti ca b m chng trnh c lu trong ngn xp. Kch thc ca ngn xp b gii hn bi b nh SRAM c trn mt chip. V tr ca ngn xp c ch th bi con tr ngn xp.

B nh SRAM bn ngoi: c tnh ny ch c cc b x l c ln trong h vi iu khin AVR. Cc b x l ny c cc cng truy nhp b nh v d liu bn ngoi c th s dng bt k b h SRAM ngoi no m ngi dng c th ty quyt nh khi thit k.

Hnh 30. Bn b nh ca vi iu khin AVR

EEPROM. B nh EEPROM c sn trn hu ht cc b iu khin AVR v c truy nhp theo mt bn b nh tch bit. a ch bt u ca b nh EEPROM lun l $0000. Cc b x l khc nhau c t 64 byte n 4kbyte b nh EEPROM. B nh EEPROM c th c c v ghi bi bt k chng trnh no. Vic c b nh EEPROM din ra nhanh hn vic ghi vo b nh EEPROM. B nh EEPROM c th ghi c khong 100000 ln.

d) Thanh ghi trng thi (SREG): Thanh ghi trng thi cha 8-bit c, ng vai tr bo hiu trng thi ca b x l. Tt c cc bit c xa khi reset v c th c c hoc ghi vo b nh chng trnh.

+ Bit 0 C (Carry Flag): l bit nh trong cc php i s hoc logic, + Bit 1 Z (Zero Flag): c ny c set nu kt qu php ton i s hay php Logic

bng 0. + Bit 2 N (Negative Flag): c ny c set nu kt qu php ton i s hay php

Logic l s m. + Bit 3 V (Twos complement Overflow Flag): hot ng ca c ny lin quan n

kin thc s nh phn (phn b). + Bit 4 S (Sign Bit): Bit S l kt qu php XOR gia 1 c N v V, S=N xor V. + Bit 5 H (Half Carry Flag): c H l c nh trong 1 vi php ton i s v php

Logic, c ny hiu qu i vi cc php ton vi s BCD. + Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit LoaD) v

BST (Bit STorage). + Bit 7 I (Global Interrupt Enable): bit ny phi c set ln 1 nu trong chng

trnh c s dng ngt. Thanh ghi trng thi khng c lu tr vo my trong thi gian din ra mt thao tc ngt. Lnh trong mt on chng trnh ngt c th sa i bt trng thi v v th chng trnh ca ngi dng phi lu tr v khi phc thanh ghi trng thi trong thi gian c mt ngt.

e) Con tr ngn xp (SP) L mt thanh ghi 8-bit c a ch trong cc thanh ghi chc nng c bit l $3E (trong b nh RAM l $5E), c nhim v tr ti vng nh RAM cha ngn xp.

Trc khi thc hin chng trnh phc v ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngn xp gim hai v tr. V con tr ngn xp s gim i 1 khi thc hin lnh PUSH. Ngc li khi thc hin lnh POP th con tr ngn xp s tng thm 1 v khi thc hin lnh SET hay RETI th con tr ngn xp s tng thm 2. Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt

chng trnh con c gi hoc cc ngt c cho php phc v. V gi tr ngn xp cng phi ln hn hoc bng $60H (0x60) v $5FH tr li l vng cc thanh ghi.

f) Qun l ngt: Ngt l mt c ch cho php cc thit b ngoi vi bo cho CPU bit v tnh trng sn sng cho trao i d liu ca mnh. Khi c tn hiu bo ngt CPU s tm dng cng vic hin ti v lu li v tr ang thc hin chg trnh (con tr PC) vo ngn xp, sau tr n vector phc v ngt v thc hin chng trnh phc v ngt cho ti khi gp lnh RETI th CPU li ly PC t ngn xp ra v tip tc thc hin tip chng trnh m trc khi phc v ngt n ang lm. Trong trng hp m c nhiu ngt yu cu cng mt lc th CPU s lu cc c bo li v ln lt thc hin cc ngt theo mc u tin. Trong trng hp ang phc v ngt m c ngt mi xut hin th n s kim tra, nu ngt mi c u tin hn th n s phc v ngt , cn nu khng th n s b qua.

g) Cc cng vo ra Tt c cc b iu khin AVR u c mt lng ln cc cng vo/ra, rng nm trong khong t 3 bit cho ti 48-bit. Cc cng ra ca AVR c th chu dng in ln ti 20mA, rt thch hp cho vic iu khin trc tip cc LED m khng cn n mch m b sung. Cc cng c nh s l DDRx, PORTx, PINx cho mt cng x cho trc. cng DDRx l thanh ghi hng d liu. Khi ghi mt mc 1 vo mt bit DDR lm cho bit tng ng thnh bit li ra trong PORT. Sau , xut ra mt gi tr 1 trn bit cng. bit tng ng c th c t hoc reset bng cch s dng lnh CBI hoc SBI hoc mt lnh OUT. Tng t c d liu vo mt cng ta s dng thanh thi PINx.

h) B nh thi watchdog: B nh thi watchdog l mt b nh thi iu khin c v c s dng lm thit b nh thc trong trng hp phn mm b ri vo mt hoc mt s vng lp v tn, hoc trong trng hp vic thc thi chng trnh b mc li. b nh thi watchdog c mt li ra, c khar nng t li b iu khin. Mch nh thi watchdog timer c gi nhp t mt b dao ng RC ring bit trn chip. Khong thi gian reset mch watchdog c iu chnh thng qua iu khin mch chia tn s watchdog timer.

2.7.3. ATmega16

ATmega16 l vi iu khin 8-bit c thit k theo phng php RISC. Vi kh nng thc hin mi lnh trong vng mt chu k xung clock, ATmega16 c th t c tc 1MIPS trn mi MHz (1 triu lnh/s/MHz). Atmega16 c cc c im sau:

16KB b nh Flash vi kh nng c trong khi ghi, lp trnh ngay c trn h thng. - 512 byte b nh EEPROM. Cho php 10,000 ln ghi/xa. - 1KB b nh SRAM. - 32 thanh ghi chc nng. - 32 ng vo ra chung. - 2 b Timer/Couter 8-bit v 1 b Timer/Couter 16-bit vi cc ch lm vic: so snh,

chia tn tch bit v bt mu. - 8 knh ADC 10 bit. - 4 knh iu ch rng xung PWM - Atmega 16 h tr y cc chng trnh v cng c pht trin h thng nh: trnh

dch C, macro assemblers, chng trnh m phng/sa li, kit th nghim,. - AVR s dng kin trc Harvard, tch ring b nh v cc bus cho chng trnh v d

liu. Cc lnh c thc hin ch trong mt chu k xung clock. B nh chng trnh c lu trong b nh Flash.

- H tr b truyn nhn UART lp trnh c. - H tr giao din truyn thng SPI ch/t (master/slave). - H tr b so snh tng t - H tr b nh thi Watchdog vi b to dao ng ring, cho php lp trnh c v t

ng reset khi treo my - 6 ch ng: ch ri (Idle), ch tit kim in (Power-Save), ch gim nhiu

ADC (ADC Noise Reduction), ch ch (Standby), ch ch m rng (Extended Standby) v ch gim bt in nng (Power-Down)

AVR Atmega16 c 32 thanh ghi lm vic a nng. Ton b 32 thanh ghi ny u c ni trc tip vi b x l s hc logic ALU. Cho php truy nhp vo 2 thanh ghi c lp trong 1 chu k xung nhp. Kin trc t c c tc x l nhanh gp 10 ln vi iu khin dng CISC thng thng.

Cc chn tn hiu ca b vi x l dng a tn hiu vo hay xut tn hiu ra. N bao gm 3 BUS chnh: Bus a ch, Bus d liu, Bus iu khin nhng thng thng c phn thnh cc nhm c th sau: - Nhm cc chn cp ngun nui cho b vi x l. - Nhm chn d liu, a ch (trng thi): cc tn hiu ny thng l 3 trng thi, trong

a ch l tn hiu ra, cn d lin th c 2 chiu. Mt s b vi x l dng mt s chn truyn c tn hiu a ch v d kin. AVR Atmega16 c 28 ng tn hiu 3 trng thi, c chia lm 4 port: + Port A (PA7 PA0): gm cc chn t 33 n 40. + Port B (PB7 PB0): gm cc chn t 1 n 8. + Port C (PC7 PC0): gm cc chn t 22 n 29. + Port D (PD7 PD0): gm cc chn t 14 n 21.

Tt c cc port ny u l cng vo/ra 8-bit vi cc in tr treo bn trong (dnh ring cho mi bit), cc b m ra c c im hng i xng vi c ch sink v ch

source. Khi cc chn tn hiu ca cc port ny c s dng lm u vo v mc tch cc t vo chn l thp th chng s cp dng khi in tr treo bn trong hot ng. Khi c mt trng thi reset c kch hot, cc chn tn hiu ny s l 3 trng thi ngay c khi b pht xung clock khng chy. c bit, port A c th c dng lm cc u vo tng t cho b bin i ADC, hoc vn lm mt cng vo/ra 2 chiu 8-bit khi b bin i ADC khng c s dng.

- Chn reset (chn 9): reset u vo. Mt mc tch cc thp t ln chn reset di hn chiu di xung nh nht s kch hot mt trng thi reset, ngay c khi b pht xung clock khng chy. Nhng xung ngn hn khng m bo cho vic kch hot mt trng thi reset.

- Chn XTAL1 (chn 13): l u vo ca b khuch i pht xung ngc v l u vo ca mch iu khin b pht xung bn trong.

- Chn XTAL2 (chn 12): l u ra ca b khuch i pht xung ngc. - Chn AREF (chn 32): l chn cp in p tham chiu tng t (t bn ngoi) cho b

bin i ADC.

Hnh 31. Cu hnh chn ca ATmega16

Hnh 32. S khi ca Atmega16

Chng 3. Thit k mch phn cng

3.1. Cc cng vo/ra ca mch phn cng

Da trn s cc khi chc nng c xut mc 1.3 v cc tm hiu v thit b Chng 2, trc khi bt tay vo thit k phn cng, ta cn xc nh c cc cng vo/ra ca mch v c s la chn linh kin thc t ph hp.

Bng 4. Cc cng vo/ra mch phn cng v chc nng

STT Cng vo/ra Chc nng

1 Connector 4P Kt ni vi cc ngun DC +5V, +12V cp cho mch

2 Connector 6P Kt ni vi cc ng c thc nghim

3 IDE Connector 10P (2x5) Giao tip SPI vi my tnh thng qua mch np ISP 4 COM DB9 Giao tip RS232 vi my tnh

C th thy c 2 ngun +5V ta c th ly: t mch adapter v t mch np ISP (my tnh), do ta s dng thm 1 cng tc chuyn i linh hot gia 2 ngun ny. Bn cnh , cc n LED ch th c s dng bo c in vo mch v mt s t c s dng lc ngun.

Hnh 33. Cc cng vo/ra mch phn cng

3.2. Mch driver L298

V c bn, mch driver L298 c trnh by kh chi tit trong datasheet ca thit b cng nh ni dung c cp trong mc 2.3.

Hnh 34. Mach driver L298 Trong bi ton iu khin ng c, in p phn ng mong mun s c to ra

da trn c s ca 3 ng iu khin l PWM dng iu khin ln in p, DIR dng iu hng (du ca in p) v En cho php mch hot ng. Chip L298 c sn ng En nhng 2 ng iu khin In1 v In2 khng thc s ng nht vi cc ng PWM v DIR theo chc nng nh chng ta mong mun. Trong mt s thit k mch driver cho ng c, ngi ta s s dng thm mt mch logic ph vi 2 ng vo l PWM v DIR trong khi 2 ng ra l 2 ng iu khin In1 v In2, cch lm ny n gin v mt t duy nhng i hi thm phn cng h tr. Trong n ny, nhm s s dng cch kt ni phn cng trc tip cc ng En, In1, In2 ca L298 vi 3 chn OCR ca VK, mi lin h gia In1, In2 vi PWM, DIR s c gii quyt bng phn mm (mc 4.3.1).

3.3. o tc ng c

xc nh c gi tr tc (hoc v tr) thc t cng nh chiu quay hin ti ca ng c, ta cn x l cc tn hiu dng xung t 2 knh Encoder. Ty theo i lng iu khin (v tr hay vn tc) v c im encoder ( phn gii) ngi ta thng s dng cc gii php sau c encoder bng AVR. - Dng chc nng counter: t cc knh ca encoder vo cc chn Counter (T0, T1) ca cc b Timer m s lng xung trn cc knh ny. y l phng php s dng t ti nguyn nht (t tn thi gian CPU c encoder). Nhc im ln nht ca phng php ny l khng xc nh c chiu quay, mc khc phng php ny khng n nh khi vn tc ng c c s thay i ln. - Dng input capture: Mt s b timer-counter trn AVR c chc nng Input capture. C mi ln c mt tn hiu (cnh ln hoc cnh xung) trn chn ICP (Input Capture Pin), gi tr thi gian ca timer c t ng gn cho thanh ghi ICR (Input capture Register). So snh gi tr thanh ghi ICR trong 2 ln lin tip s c c chu k ca tn hiu kch chn ICP. T suy ra tn s tn hiu. Nu mt knh ca encoder c ni vi chn ICP th ta

c th o c tn s tn hiu ca knh ny, t tnh c vn tc ca ng c. Chng ta c th dng ngt Input Capture v khi ngt xy ra, c th m s xung tng thm bit c gc quay motor, cng c th xc nh c chiu quay thng qua mc knh B trong trnh phc v ngt Input Capture. y l mt phng php hay, nhng c nhc im l kh phc tp khi s dng chc nng input capture ca AVR. Mc khc trn cc chip AVR t ATmega32 tr xung, Input Capture ch c Timer 1, trong khi Timer ny thng c dng to PWM iu khin ng c. - S dng ngt ngoi: Knh A ca encoder c ni vi 1 ngt ngoi (nn chn INT2 l ngt c mc u tin thp nht) v knh B c ni vi mt chn no bt k (khng phi chn ngt). C mi ln ngt ngoi xy ra, tc c 1 xung xut hin knh A th trnh phc v ngt ngoi t ng c gi. Trong trnh phc v ngt ny, ta kim tra mc logic ca knh B, ty theo knh B ang mc thp hay cao m bin m xung s c tng thm hay gim i. Phng php ny n gin, hiu qu v c s dng kh ph bin trong bi ton c encoder o tc . Tuy nhin, cn phi lu n khong thi gian gia 2 ln ngt ny xy ra. Trong n ny, ng c c chn c phn gii ca encoder l 888 xung trn mi vng quay, c vn tc khng ti ti a vo khong 3000 vng/pht = 50 vng/s nn tn s xung ln nht t encoder l 888 x 50 = 44.4 KHz, tc l c khong 20us li xy ra mt ngt. Tn s ngt nh th l tng i cao so vi tn s 8MHz ca CPU.

Vi mong mun kim nghim c 3 phng php o tc trn, v mt phn cng, nhm ni Knh A ca encoder c ni vi chn 3 (dng ngt INT2) v chn 20 (dng ngt ICP1) ca vi iu khin Atmega16, Knh B ni vi chn 1 (dng Counter 0), khng s dng knh I.

3.4. Mch o dng phn hi

o dng mt chiu, ta s dng in tr shunt 10m, gi tr in p ri trn in tr ny

l -1(V) () (A) (A/ )100

ss s s

IU R I= = , do thu c tn hiu in p tng t c tr

s Volt gn vi tr s Ampere ca dng in chy qua ng c, ta s dng 2 tng khuch i khng o, mi tng 11 ln, nng tn hiu thu c t shunt ln 121 ln. Do nh hng ca vic iu ch rng xung vi tn s cao, tn hiu thu c t shunt c nguy c cha cc thnh phn cao tn nh hng n tnh chnh xc ca php o v gy ra hin tng trng ph khi trch mu tn hiu. V vy, ta lp thm mt mch lc thng thp RC u vo mch o.

Hnh 35. Mch o dng ng c mt chiu bng in tr shunt

3.5. Mch bo v qu dng

Mc tiu ca mch ny l to ra mt ngt (thng l ngt ngoi c mc u tin cao ch sau ngt reset, c th vi ATmega16 l ngt INT0) bo cho vi iu khin thc hin lnh dng ng c khn cp khi xy ra s c qu dng nhm m bo an ton cho ti v cc thit b trong mch. u vo ca mch ny l tn hiu tng t (gi tr dng in o c)

measI cn u ra ca mch l xung s mc logic cao khi maxmeasI I< v mc logic thp khi maxmeasI I> , maxI l gi tr dng in ln nht cho php, v ngt c gi n VK l mt ngt theo mc theo thp.

Mt mch so snh o c di tr nh Hnh 36 c s dng, trong in tr FR c

chn rt ln so vi cc in tr 2 3,R R .

Hnh 36. Mch so snh o c di tr (a) v s Thevenin tng ng (b)

Hnh 37. Lu di tr vo-ra cho mch so snh o

Ta thy rng 2 32 3 232 3

,FR RR R R R

R R> =

+

nn 2323 23

0, 1Ff F

R RR R R R

+ +

.

Khi , mc in p tham c chn ng vi gi tr maxI l 3232 3

ref DDRV V V

R R= =

+.

y, ta s chn RF = 1M, R2 = 10k, R3 c iu chnh trong di 0 10k bng mt

bin tr cho php Vref nm trong di t 0 n 1 2.5(V)2 DD

V = , ng vi dng in ln nht

cho php maxI c t trc (bng phn cng) nm trong di 0 2A.

Hnh 38. Mch so snh bo v qu dng

3.6. Khi nt nhn v hin th

chn ch v gi tr t cho b iu khin, ta s dng 4 nt nhn vi cc chc nng khc nhau. Do cc chn 4 port ca vi iu khin ATmega16 u l cc u vo/ra ba trng thi v c th ci t lm u vo hoc u ra mt cch linh hot bng phn mm, nn ta kt ni phn cng bn nt nhn trc tip vo cc chn PC0 PC3 ca vi iu khin m khng cn s dng in tr treo bn ngoi.

hin th thng tin v gi tr t, ch hot ng v cc gi tr o tc thi, ta s dng mt mn hnh LCD 16x2. Cc chn d liu t D4 D7 c kt ni vi Port PC4 7 ca vi iu khin s dng vi ch truyn 4-bit. Cc tn hiu iu khin LCD c ni vi PA5 7 ca vi iu khin. Ta s dng thm mt bin tr vi chnh 10K iu chnh tng phn ca mn hnh LCD.

Hnh 39. Khi nt nhn v LCD

Hnh 40. Kt ni cc nt nhn v LCD vi port C ca VK

3.7. Mch to dao ng bng thch anh

Bn thn AVR cng c ni dao ng, tuy nhin b to dao ng s dng cng hng thch anh bn ngoi vn c s dng rng ri v n n gin, hot ng n nh v c nhiu la chn v tn s hot ng. B cng hng thch anh c h s phm cht Q cao (khong 10000 hoc hn na), v ch cn mt khong thi gian ngn n nh trng thi dao ng (ch khong 5ms 20ms)

Trong mch to dao ng bng thch anh (Hnh 41), thch anh c mc vo 2 chn XTAL1 v XTAL2 ca VK, l cc u vo v ra ca mt b khuch i o trong chip. i vi ATmega16, tn s dao ng ln nht l 8MHz, cng l tn s thch anh c s dng trong n. Mch ny cn c thm 2 t in tr s bng nhau (trong khong 12pF 22pF) h tr cho vic bt u dao ng.

Hnh 41. Mch to dao ng bng thch anh

3.8. S nguyn l tng hp Xem phn Ph lc, trang 84.

Chng 4. Thit k phn mm

4.1. Tm hiu cc module ca ATmega16 c s dng

4.1.1. Cc ngt trong ATmega16

Ngt (Interrupt) l mt tn hiu khn cp gi n b x l, yu cu tm ngng tc thi cc hot ng hin ti nhy n mt ni khc thc hin mt nhim v khn cp no . Nhim v ny c gi l chng trnh phc v ngt ISR (interrupt service routine). Sau khi kt thc nhim v trong ISR, b m chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc nhim v cn dang d. Ngt c mc u tin x l, thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi gian. Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt thc) hay do cc tc nhn bn ngoi.

Tt c cc ngt u c ring mt bit cho php tng ng, cng vi bit cho php ngt ton cc (Global Interrupt Enable) trong thanh ghi trng thi, s cn phi set ln 1 c th kch hot c ngt . Atmega16 cung cp mt vi ngun ngt khc nhau, cc ngt ny tng ng vi mi vc-t ngt khc nhau trong khng gian b nh chng trnh v c cho bi Bng 5.

Bng 5. a ch cc vc t ngt ca Atmega16

Bng trn cng xc nh mc u tin x l ca cc ngt, a ch cng thp th mc u tin ngt cng cao. Reset l ngt c mc u tin cao nht, tip n l ngt ngoi INT0.

Lin quan n ngt bao gm cc thanh ghi nh sau: SREG, MCUCR, MCUCSR, GICR, GIFR - Thanh ghi Status Register (SREG):

Bit 7 I: Global Interrupt Enable: Bit ngt ton cc. Bit ny cn c set khi cho php cc ngt. - Thanh ghi MCU Control Register (MCUCR):

Thanh ghi MCUCR c cc bit lin quan n ngt nh sau: Bit 3, 2 ISC11, ISC10: Cc Bit iu khin chiu ngt 1. Ngt ngoi 1 c kch hot bi chn INT1 nu bit ngt ton cc SREG I v bit cho php ngt tng ng trong thanh GICR c set. Mc v sn ca ngt ngoi INT1 c xc nh theo Bng 6.

Bng 6. iu khin chiu ngt INT1 theo bit

Bit 1, 0 ISC01, ISC00: Cc Bit iu khin chiu ngt 0. Tng t nh cc bit 3 v 2 trn.

- Thanh ghi MCU Control and Status Register (MCUCSR):

Bit 6 ISC2: Bit iu khin chiu ngt 2. Ngt ngoi 2, ngt khng ng b, c kch hot bi chn ngoi INT2 nu bit ngt ton cc v bit cho php ngt tng ng trong thanh GICR c set. Nu ISC2 c vit xung 0, mt sn xung chn INT2 s kch hot ngt. Nu ISC2 t vit ln 1, mt sn ln chn INT2 kch hot ngt.

- Thanh ghi General Interrupt Register Control (GICR):

Bit 7-6-5: Cc bit cho php ngt ca ngt ngoi INT1, INT0 v INT2 tng ng.

Khi bit INT1 c set (1) v bit ngt ton cc SREG I cng c set, chn ngt ngoi IN1 c enabled. Tc ng ln chn ny s gy ra 1 yu cu ngt ngay khi INT1 c cu hnh nh 1 chn ouput. Tng t vi cc bit 6, 5. Bit 1: IVSEL (Interrupt Vector Select)

Khi bit IVSEL c xa (0), cc vec t ngt c t ti vng bt u ca b nh Flash. Khi bit ny c set (1), cc vec t ngt c chuyn n vng bt u ca on Boot Loader trong b nh Flash. Bit 0: IVCE: (Interrupt Vector Change Enable)

Bit IVCE nn c vit ln mc logic 1 c th thay i c bit IVSEL. IVCE c xa bi phn cng trong 4 chu k my sau khi n c vit hoc khi IVSEL c vit. Set bit IVCE s lm disable cc ngt. Ch : Trong n ny, cc bit 1 v 0 thanh ghi ny s u c clear mc 0. - Thanh ghi General Interrupt Flag Register (GIRF)

Bit 7 INTF1: (External Interrupt Flag 1) C ngt ngoi 1.

Khi c mt sn hoc mt s thay i mc logic ln chn INT1 n s gy ra 1 yu cu ngt, bit INTF1 c set ln 1. Nu bit ngt ton cc SREG I v bit INT1 thanh GICR u c set (1). MCU s nhy n vc t ngt tng ng. C ngt c xa khi th tc ngt c thi hnh. Mt s la chn khc, c bo ngt c th b xa bi vit logic 1 vo n. C ny lun lun c xa khi INT1 c cu hnh nh l 1 mc ngt. Bit 6, 5 INTF0, INTF2: tng t nh bit 7.

4.1.2. iu ch rng xung (PWM) vi Timer/Counter1 (T/C1) Chip AVR ATmega16 cung cp 3 Timer/Counter (T/C) phc v cho nhiu mc

ch khc nhau. Trong , T/C0 v T/C2 l cc T/C 8-bit cn T/C1 l T/C 16-bit vi cc chc nng c bn nh Counter, Input Capture, Output Compare, Waveform Generation. Ngoi ra mi Timer c thm mt s chc nng m rng khc nh Phase Correct PWM, Asynchronous Operation T/C1 v T/C0 s dng chung mt module b m t trc (prescaler) nhng c kh nng s dng ring bit do c cc ci t khc nhau. Ngun xung

Clock cung cp cho cc module c th s dng bao gm ngun xung Clock ni ly trc tip t xung Clock ca h thng vi mt h s t l; hoc s dng ngun xung Clock ngoi a vo chn T0/T1 tng ng, c la chn thng qua cc bit Clock Select (CS12:0) trn thanh ghi iu khin TCCR1B (Timer/Counter Control Register). Tng t, T/C2 cng c th s dng ngun xung Clock ni ng b hoc ngun ngoi khng ng b thng qua hai chn TOSC1/2. S khi ca T/C0 v T/C1 c th hin trn Hnh 42 vi k hiu n thay th cho s ch ca T/C tng ng.

Hnh 42. S khi cu trc Timer/Counter0,1

i vi ring T/C1, c 5 ch hot ng chnh, tuy nhin y ta ch cp n ch fast PWM (PWM tn s cao) c s dng trong ng dng ny.

4.1.2.1. Cc thanh ghi s dng vi ch xut xung fast PWM C kh nhiu thanh ghi lin quan n T/C1, y ta xt nhng thanh ghi v cc bit

lin quan n ch xut xung fast PWM. V l T/C 16-bit trong khi rng b nh d liu ca AVR l 8-bit nn i khi cn dng nhng cp thanh ghi 8-bit to thnh 1 thanh ghi

16-bit, 2 thanh ghi 8-bit s c tn kt thc bng cc k t L v H trong L l thanh ghi cha 8-bit thp (LOW) v H l thanh ghi cha 8-bit cao (High) ca gi tr 16-bit m chng to thnh. - TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8-bit to thnh thanh ghi 16-bit (TCNT1) cha gi tr m hin ti ca T/C1. C 2 thanh ghi ny cho php c v ghi gi tr mt cch trc tip, tuy nhin cn ch vn bo ton d liu nu nh xy ra ngt trong qu trnh truy cp thanh ghi 16-bit vi bus d liu 8-bit. S kt hp ca hai thanh ghi ny to thnh thanh ghi 16-bit nh sau:

- TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh ghi iu khin hot ng ca T/C1. Tt c cc Mode hot ng ca T/C1 u c xc nh thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, y khng phi l 2 byte cao v thp ca mt thanh ghi m l 2 thanh ghi hon ton c lp. Cc bit trong 2 thanh ghi ny bao gm cc bit chn Mode hay chn dng xung (Waveform Generating Mode WGM), cc bit quy nh dng xung xut ra (Compare Output Match COM), cc bit chn gi tr chia prescaler cho xung nhp Clock (Clock Select CS)Cu trc ca 2 thanh ghi c trnh by c th nh sau: Thanh ghi TCCR1A:

Trong : Bit 7:6 COM1A1:0: Ci t ch Compare Output cho knh A Bit 5:4 COM1B1:0: Ci t ch Compare Output cho knh B Cc bit COM1x1:0 ny iu khin vic cho php hoc la chn kiu xung xut ra (khng o hay o) ti cc chn Output Compare OC1x nh trn Bng 7.

Bng 7. Cc bit ph COM1x1:0 iu khin la chn kiu xung xut ra ti chn OC1x

Bit 3:2 FOC1x: Ci t ch Force Output Compare cho knh A/B. Ta khng s dng n cc bit ny y.

Bit 1:0 WGM11:0: Kt hp vi cc bit WGM13:2 thanh ghi TCCR1B iu khin vic la chn ch xut xung, dng xung xut ra, v la chn ngun lm gi tr TOP nh trn Bng 8.

Bng 8. M t cc ch xut xung ca Waveform Generation Module

Thanh ghi TCCR1B:

Bit 4:3 WGM13:2: Kt hp vi cc bit WGM11:0 thanh ghi TCCR1A iu khin vic la chn ch xut xung, dng xung xut ra, v la chn ngun lm gi tr TOP nh trn Bng 8. Bit 2:0 CS12:0: Cc bit la chn xung nhp Clock s dng bi Timer/Counter nh trn Bng 9.

Bng 9. La chn xung nhp cho Timer/Counter thng qua cc bit Clock Select

OCR1A v OCR1B (Ouput Compare Register A v B): l hai thanh ghi cha gi tr 16-bit c lin tc so snh vi gi tr b m TCNT1. Khi hai gi tr ny khp nhau, s xy ra mt ngt hoc thay i mc logic ca xung PWM xut ra trn chn OC1x.

- TIMSK (Timer/Counter Interrupt Mask Register): cc b T/C trn AVR dng chung thanh ghi mt n ngt, v th TIMSK cng c dng quy nh ngt cho T/C1. C iu lc ny chng ta ch quan tm n cc bit t 2 n 5 ca TIMSK. C tt c 4 loi ngt trn T/C1

Bit 5 - TICIE1: l bit cho php ngt trong trng hp Input Capture c dng. Bit 4:3 - OCIE1A/B: l bit cho php ngt khi gi tr b m TCNT1 khp vi OCR1A/B. Bit 2 - TOIE1: l bit cho php ngt trn cho T/C1.

- TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c cc b T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.

Bit 5 - ICF1: l bit c Input Capture, c set khi capture s kin trn chn ICP1. Khi ta la chn ch trn thanh ghi WGM13:0 gi tr ICR1 c dng lm gi tr TOP, th c ICF1 c set khi gi tr TCNT1 khp vi gi tr TOP. C ICF1 t xa khi chng trnh phc v ngt c thc hin hoc c th xa bng phn mm. Bit 4:3 - OCF1A/B: l bit c c set xung nhp tip theo sau khi gi tr TCNT1 khp vi gi tr OCR1A/B. C t xa khi chng trnh phc v ngt c thc hin hoc c th xa bng phn mm. Bit 2 - TOV1: l bit c bo trn ca T/C1, c set ph thuc vo ch c chn qua cc bit WGM13:0. C cng t xa khi chng trnh phc v ngt c thc hin hoc c th xa bng phn mm.

4.1.2.2. Hot ng ca Timer1 ch xut xung fast PWM Trong ch xut xung fast PWM (WGM13:0 = 5,6,7,14 hoc 15), b m s m

t gi tr BOTTOM (lun bng 0) n gi tr TOP v sau bt u li t BOTTOM (1 sn, khc vi cc ch Phase, Frequency Correct). Mc logic ca chn OC1x (Output Compare1A/B) ph thuc vo ch xut xung o hay khng o c la chn bit COM1x1:0, v d nh trong ch xut xung khng o (COM1x1:0 = 2), chn OC1x c mc logic 0 (b xa) khi c gi tr thanh ghi TCNT1 bng vi gi tr thanh ghi OCR1x, v c mc logic 1 (c set) khi gi tr TCNT1 c reset v BOTTOM.

Tn s xung PWM xut ra c tnh bi cng thc:

( )_ /

* 1clk I O

OCnxPWM

ffN TOP

=

+ (19)

Trong , N biu th cho gi tr chia tn s prescaler (1, 8, 64, 256 hoc 1024). phn gii xung PWM cho ch fast PWM c th c t c nh 8-bit, 9-bit,

10-bit hoc nh ngha thng qua thanh ghi ICR1 hoc OCR1A vi phn gii ti thiu l 2-bit (ICR1 hoc OCR1A c t gi tr 0x0003) v ti a l 16-bit (ICR1 hoc OCR1A c t gi tr MAX). phn gii xung PWM c th tnh theo cng thc:

( )( )

log 1log 2FPWMTOP

R+

= (20)

Nh vy, trong ch fast PWM, b m s m tin cho n khi gi tr b m trng vi hoc l mt trong cc gi tr c nh 0x00FF, 0x01FF, 0x03FF (WGM13:0 = 5, 6, hoc 7), hoc trng vi gi tr thanh ghi ICR1 (WGM13:0 = 14) hoc gi tr thanh ghi OCR1A (WGM13:0 = 15). Gi tr b m c xa chu k Clock tip theo.

Hnh 43. Biu thi gian ch fast PWM

Biu thi gian ca ch fast PWM nh trn Hnh 43. Trong , thanh ghi OCR1x hoc ICR1 c s dng nh ngha v cp nht gi tr TOP. Du gch ngang nh trn sn ca TCNT1 th hin thi im gi tr thanh ghi TCNT1 bng vi gi tr OCR1x. Cng ti thi im ny, c bo ngt OCF1x s c set v trng thi logic s c s thay i trn chn xut xung OC1x.

V d c th vi hot ng ca fast PWM knh A, s dng Mode 14 (WGM13:0 = 1110b). Trong Mode 14, gi tr TOP c cha trong thanh ghi ICR1. B m TCNT1 s tng t 0 (BOTTOM) ln n TOP. Gi s cc bit ph COM1A1 = 1, COM1A0 = 0, lc ny ban u trng thi trn chn OC1A (chn 15) l High (5V), khi TCNT1 tng n bng gi tr ca thanh ghi OCR1A th chn OC1A c xa v mc LOW (0V), thanh ghi m TCNT1 vn tip tc tng n khi no n bng gi tr TOP cha trong thanh ghi ICR1 th TCNT1 t ng reset v 0 v chn OC1A tr v trng thi HIGH.

Hnh 44. Minh ha fast PWM Mode 14 knh A

Nh vy ta c th iu khin c tn s xung (chu k) v duty cycle thng qua hai thanh ghi ICR1 v OCR1A. Thng thng, ta gi c nh gi tr thanh ghi ICR1 v thay i gi tr OCR1A phc v mc ch iu khin. Hot ng ca fast PWM knh B cng hon ton tng t knh A. Cc Mode 5,6,7 cng tng t Mode 14, nhng gi tr TOP l c nh. Ring ch c Mode 15, gi tr TOP cng nm lun trong thanh ghi OCR1x. Do vy, ta thu c xung PWM vi duty cycle khng i l 50% v c th thay i tn s xung ra bng cch thay i gi tr thanh ghi OCR1x.

4.1.3. To chu k trch mu vi Timer 2 v m xung vi Counter0

Timer/Counter (T/C) l cc module c lp vi CPU. Chc nng chnh ca cc b T/C l nh thi (to ra mt khong thi gian, m thi gian) v m s kin. mc ny chng ta s tm hiu chc nng nh thi gian chu k trch mu cho b iu khin ca T/C2, v ng thi chc nng m s kin ca T/C0 m xung t Encoder trong khu o tc ng c.

Timer/Counter2: L mt b nh thi/m module 8 bit, T/C2 c n 4 ch hot ng nh T/C1, ngoi ra n n cn c s dng nh mt module canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous) do c thit k c bit vi chn OSC ring khng dng chung ngun dao ng ca chip nh Timer0 v Timer1. S khi ca n c m t Hnh 45.

Hnh 45. S khi cu trc ca T/C2

Lin quan n chc nng nh thi ca T/C2, c 5 thanh ghi lin quan l: - TCNT2 (Timer/Counter Register): L thanh ghi 8 bit cha gi tr hin ti ca T/C2. Thanh ghi ny cho php c v ghi gi tr mt cch trc tip.

- TCCR2 (Timer/Counter Control Register): l thanh ghi iu khin hot ng ca T/C2.

Cc bit CS20, CS21 v CS22 gi l cc bit chn ngun xung nhp cho T/C2 (Clock Select). Chc nng cc bit ny c m t trong Bng 10.

Bng 10. Chn xung nhp cho T/C2

Trong : clkT2S l xung nhp a vo 2 chn OSC ca b T/C2 - OCR2 (Ouput Compare Register): Thanh ghi cha gi tr so snh vi TCNT2 tng t nh T/C1. - TIMSK (Timer/Counter Interrupt Mask Register): L thanh ghi mt n cho ngt ca tt c cc T/C, trong ch c bit TOIE2 v OCIE2 l lin quan n T/C2.

Bit 6 - TOIE2: l bit quy nh ngt trn Timer2. Bit 7 - OCIE2: l bit cho php ngt khi xy ra trong vic so snh TCNT2 vi OCR2. - TIFR (Timer/Counter Interrupt Flag Register): L thanh ghi c nh cho tt c T/C.

Bit 6 TOV2: Bit c bo trn ca T/C2, c set khi trn xy n. C t xa bi phn cng khi chng trnh phc v ngt c thc hin hoc c th xa bng phn mm. Bit 7 OCF2: Bit c c set xung nhp tip theo sau khi gi tr TCNT2 khp vi gi tr OCR2. C t xa khi chng trnh phc v ngt c thc hin hoc c th xa bng phn mm.

Timer/Counter0: l mt b module n gin vi 8 bit nh Timer/Counter 2. S khi ca n c cho Hnh 42, c 4 thanh ghi lin quan n hot ng v iu khin T/C0, l: - TCNT0 (Timer/Counter Register): Tng t nh thanh ghi TCNT2 T/C2 - TCCR0 (Timer/Counter Control Register): Thanh ghi iu khin hot ng ca T/C0.

Cc bit CS00, CS01 v CS02 dng chn ngun xung nhp (Clock Select). Chc nng cc bit ny c m t tng t nh trong Bng 9 ca T/C1. cu hnh T/C0 nh mt b m xung trn chn T0, t TCCR0 = 6 (CS02 = 1, CS01 = 1, CS00 = 0) m cnh xung trn chn T0, t TCCR0 = 7 (CS02 = 1, CS01 = 1, CS00 = 1) m cnh ln. - TIMSK (Timer/Counter Interrupt Mask Register): tng t T/C2. - TIFR (Timer/Counter Interrupt Flag Register): tng t T/C2.

4.1.4. B chuyn i tng t - s (ADC) Chip AVR ATmega16 ca Atmel c tch hp sn cc b chuyn i ADC loi xp

x lin tip vi phn gii 10 bit. ADC c kt ni vi mt b trn tn hiu tng t 8 knh cho php chuyn i 8 knh n (t cc chn ADC0 n ADC7 ca port A). Bn cnh , ADC ca ATmega16 h tr 16 t hp chuyn i in p hiu (gia 2 u vo), trong c 2 in p hiu (ADC1-ADC0 v ADC3-ADC2) c th khuych i kh trnh.

ADC trn AVR cn c nui bng ngun in p ring chn AVCC, gi tr in p cp cho AVCC khng c khc ngun nui chip (VCC) qu +/-0.3V. Nhiu (noise) l vn rt quan trng khi s dng cc b ADC, gim thiu sai s chuyn i do nhiu, nh sn xun khuyn ngh kt ni chn AVCC vi ngun s VCC thng qua mt mch LC, v cc chn port A c s dng lm u ra s khng nn chuyn trng thi khi qu trnh chuyn i ADC ang din ra.

in p tham chiu cho ADC trn AVR c th c to bi 3 ngun: dng in p tham chiu ni 2.56V (c nh), in p AVCC hoc dng in p ngoi t trn chn VREF. Nu kt ni chn AREF vi in p c nh bn ngoi th ngi dng ch c th la chn in p ngoi t trn chn AREF lm in p tham chiu m khng s dng c cc 2 la chn cn li, v in p ny phi c lc tht tt. Nu khng c in p ngoi no c kt ni vi chn AREF, ngi dng c th chuyn gia 2 la chn s dng in p tham chiu ni 2.56V hoc AVCC lm tham chiu, khi chn VREF cn c ni vi mt t in lc nhiu, v lu rng kt qu ln chuyn i ADC u tin sau khi chuyn ch tham chiu c th khng chnh xc v nn c b qua.

4.1.4.1. Hot ng ca ADC ADC chuyn i mt u vo in p tng t thnh mt gi tr s 10 bit thng qua

php xp x lin tip. Gi tr nh nht ng vi GND v gi tr ln nht ng vi in p tham chiu tr 1 bit (LSB). Vic la chn in p tham chiu c quy nh bi cc bit REFS trong thanh ghi ADMUX. Knh u vo tng t v h s khuch i in p hiu GAIN c quy nh bi cc bit MUX trong ADMUX. Bt c chn u vo port A no cng c th c s dng ch n knh ADC.

ADC c cho php hot ng bng vic set bit ADEN trong thanh ghi ADCSRA, khi vic la chn in p tham chiu v cc knh u vo mi c hiu lc, v ch nn xa bit ADEN trc khi bc vo cc ch ng. Mt qu trnh chuyn i c bt u bng vic set bit ADSC trong ADCSRA, bit ny s c gi mc cao trong sut qu

trnh chuyn i, v c xa bng phn cng khi qu trnh chuyn i kt thc. Ngoi ra, mt qu trnh chuyn i cng c th c kch hot t ng bi cc ngun khc nhau ch ADC Auto Trigger, s dng ch ny cn set mt bit cho php l ADATE trong ADCSRA v chn ngun kch quy nh bi cc bit ADTS trong thanh ghi SFIOR.

Thi gian thc hin mt qu trnh chuyn i thng thng l 13 chu k ADC clock, trong khu trch mu v gi tr chim 1.5 chu k, cc thi gian ny vi ln chuyn i u tin (sau khi set bit ADEN) tng ng l l 25 v 13.5 chu k ADC clock. Tn s ADC clock c t t tn s CPU thng qua mt thang t l c quy nh bi cc bit ADPS trong thanh ghi ADCSRA.

Sau khi chuyn i hon tt, kt qu c ADC ghi vo cc thanh ghi d liu ADC

l ADCH v ADCL. i vi chuyn i knh n, kt qu l 1024INREF

VADCV

= , i vi

chuyn i knh hiu, kt qu l ( )512POS NEG

REF

V V GAINADC

V

= . Mc nh, kt qu 10

bit ny c hiu chnh phi, nhng c th ty chn hiu chnh tri sang bng vic set bit ADLAR trong ADMUX. Nu kt qu c hiu chnh tri v yu cu chnh xc khng qu 8-bit, ch cn c ADCH l ; ngc li, ADCL phi c c trc, sau mi c ADCH m bo rng ni dng ca cc thanh ghi d liu ny l trong cng mt ln chuyn i. Mi khi ADCL c c, truy nhp ca ADC n cc thanh ghi d liu s b kha, ngha l nu ADCL c c v mt chuyn i hon thnh trc khi ADCH c c th kt qu chuyn i s b mt v khng thanh ghi no d liu no c cp nht. Khi ADCH c c, truy nhp ca ADC n cc thanh ghi ADCH v ADCL li c kch hot tr li.

ADC c nhng ngt ring c kch khi mt ln chuyn i hon thnh. Khi ADC truy nhp n cc thanh ghi d liu b cm gia qu trnh c ADCH v ADCL, ngt vn xy ra mc d kt qu chuyn i b mt.

Lu thi gian m t hot ng ca ADC trong mt qu trnh chuyn i thng thng c th hin trong Hnh 46.

Hnh 46. Lu thi gian ADC trong mt chuyn i n

4.1.4.2. Cc thanh ghi trong ADC C 4 thanh trong b ADC trn AVR trong c 2 thanh ghi data cha d liu sau khi chuyn i, 2 thanh ghi iu khin v cha trng thi ca ADC. - ADMUX (ADC Multiplexer Selection Register): l 1 thanh ghi 8-bit iu khin vic chn in p tham chiu, knh v ch hot ng ca ADC. Chc nng ca tng bit trn thanh ghi ny s c trnh by c th nh sau:

Bit 7:6 REFS1:0 (Reference Selection Bits): l cc bit chn in p tham chiu cho ADC Bng 11. Chn in p tham chiu quy nh bi cc bit REFS

Bit 5 ADLAR (ADC Left Adjust Result): l bit cho php hiu chnh tri kt qu chuyn i. S d c bit ny l v ADC trn AVR c phn gii 10 bit, ngha l kt qu thu c sau chuyn i l 1 s c di 10 bit (ti a 1023), AVR b tr 2 thanh ghi d liu 8-bit cha gi tr sau chuyn i. Nh th gi tr chuyn i s khng lp y 2 thanh ghi d liu, trong mt s trng hp ngi dng mun 10 bit kt qu nm lch v pha tri trong khi cng c trng hp ngi dng mun kt qu nm v pha phi. Bit ADLAR s quyt nh v tr ca 10 bit kt qu trong 8-bit ca 2 thanh ghi data. Nu ADLAR=0 kt qu s c hiu chnh v pha phi (thanh ghi ADCL cha trn 8-bit thp v thanh ghi ADCH cha 2 bit cao trong 10 bit kt qu), v nu ADLAR=1 th kt qu c hiu chnh tri (thanh ghi ADCH cha trn 8-bit cao nht, cc bit t 9 n 2, v thanh ADCL cha 2 bit thp nht trong 10 bit kt qu). Bits 4:0 MUX4:0 (Analog Channel and Gain Selection Bits): l 5 bit cho php chn knh, ch v c h s khuych i cho ADC. Do b ADC trn AVR c nhiu knh v cho php thc hin chuyn i ADC kiu so snh (so snh in p gia 2 chn analog) nn trc khi thc hin chuyn i, chng ta cn set cc bit MUX chn knh v ch cn s dng.

Bng 12. Chn ch chuyn i ADC quy nh bi cc bit MUX

ADCSRA (ADC Control and Status RegisterA): l thanh ghi chnh iu khin hot ng v cha trng thi ca module ADC.

Bit 7 ADEN (ADC Enable): set bit ny ln 1 cho php module ADC c s dng. Tuy nhin khi ADEN = 1 khng c ngha l ADC hot ng ngay, cn set mt bit khc ln 1 bt u qu trnh chuyn i, l bit ADSC. Bit 6 ADSC (ADC Start Conversion): set bit ny ln 1 l bt u khi ng qu trnh chuyn i. Bit ADSC s c c l 1 trong sut qu trnh chuyn i, khi qu trnh kt thc, n s c t ng tr v 0. thc hin mt chuyn i, thng thng chng ta s set bit ADEN = 1 trc v sau set ADSC = 1. Bit 5 ADATE (ADC Auto Trigger Enable): Khi bit ny c set ln 1, ch Auto Trigger ADC s c bt. ADC s bt u mt ln chuyn i khi c sn ln ca tn hiu kch trigger. Ngun kch trigger c chn bng cc bit ADTS trong thanh ghi SFIOR. Bit 4 ADIF (ADC Interrupt Flag): c bo ngt. Khi mt chuyn i kt thc, bit ny t ng c set ln 1, v th ngi dng cn kim tra gi tr bit ny trc khi thc hin c gi tr chuyn i m bo qu trnh chuyn i thc s hon tt. Bit 3 ADIE (ADC Interrupt Enable): bit cho php ngt ADC, nu bit ny c set bng 1 v bit cho php ngt ton cc (bit I trong thanh ghi trng thi ca chip) c set, mt ngt s xy ra khi mt qu trnh chuyn i ADC kt thc v cc gi tr chuyn i c cp nht (cc gi tr chuyn i cha trong 2 thanh ghi ADCL v ADCH). Bit 2:0 ADPS2:0 (ADC Prescaler Select Bits): cc bit chn h s chia xung nhp cho ADC. Cng nh tt c cc module khc trn AVR, ADC cn c gi nhp bng mt ngun xung clock. Xung nhp ny c ly t ngun xung chnh ca chip thng qua mt h s chia. Cc bit ADPS cho php ngi dng chn h s chia t ngun clock chnh n ADC. Tham kho bng 4 bit cch chn h s chia.

Bng 13. Chn h s chia xung nhp cho ADC

- ADCL v ADCH (ADC Data Register): 2 thanh ghi cha kt qu chuyn i. Bit ADLAR trong thanh ghi ADMUX quy nh cch m kt qu c ghi vo.

+) ADLAR = 0:

+) ADLAR=1:

Thng thng, 2 thanh ghi data c sp xp theo nh dng ADLAR = 0, ADCL cha 8-bit thp v 2 bit thp ca ADCH cha 2 bit cao nht ca gi tr thu c. Ch th t c gi tr t 2 thanh ghi ny, trnh c sai kt qu, cn c thanh ghi ADCL trc v ADCH sau.

- SFIOR (Special Function IO Register C): thanh ghi chc nng c bit, 3 bit cao trong thanh ghi ny quy nh ngun kch ADC nu ch Auto Trigger c s dng. l cc bit ADTS 2:0 (Auto Trigger Source 2:0). Cc loi ngun kch c trnh by trong bng 5.

Bng 14. Chn ngun kch ADC trong ch Auto Trigger

4.1.5. o tn s tn hiu dng xung vi Input Capture

Input Capture l mt module c tch hp theo cc timer-counter 16 bit trong AVR. Mc ch chnh ca module ny l dng o tn s tn hiu hoc rng xung (duty). VK Atmega16 c 1 chn ICP1 hot ng vi chc nng input capture ca

Timer/Counter 1. Sau y l s khi ca module Input capture lin quan n Timer/Counter 1.

Hnh 47. S khi chc nng ca module Input Capture Tn hiu ngoi c ni qua chn ICP1. Bit ICES (Input Capture Edge Select) trong thanh ghi TCCRB1 s quyt nh loi "cnh" ca tn hiu vo kch Input Capture. Khi ICES=0, cnh xung ca tn hiu vo s kch Input Capture, nu ICES=1 th cnh ln s kch. Thanh ghi ICR1 cha gi tr chnh ca Input Capture. Gi s bit ICES=0, v Input Capture c th hot ng bt k mode no ca Timer1 m trong thanh ghi ICR1 khng c s dng. Khi c 1 tn hiu cnh xung chn ICP1, s thay i ny xc nhn ln b pht hin sn (edge detector), v mt capture s c kch. Khi Input Capture c kch, trong cng 1 chu k my, gi tr ca thanh ghi TCNT1 (thanh ghi Timer) s c t ng chp vo thanh ghi ICR1 v ng thi c ICF1 c set. Nu enable TICIE1=1, C Input Capture s sinh ra mt ngt Input Capture. C ICF1 s c t ng xa khi ngt c thi hnh. C ICF1 cng c th c xa bng phn mm. Nh vy, bng cch li dng kh nng thanh ghi TCNT1 c t ng chp vo ICR1, chng ta c th tnh c khong thi gian gia 2 ln Input Caprture xy ra, t suy ra chu k hay tn s tn hiu cn o. Vic c gi tr 16-bit trong ICR1 c thc hin bng cch c byte thp trc (ICR1L) ri sau n byte cao (ICR1H). Khi byte thp c c, byte cao c copy vo thanh ghi tm thi (TEMP). Khi CPU c a ch ca ICR1H, n s truy cp vo thanh ghi TEMP. Mt b loi b nhiu (noise canceler) s lc bt nhiu b dng mt b lc s n gin. B loi b nhiu ny s c enable bi vic set bit Input Capture Noise Canceler (ICNC1) trong thanh ghi Timer/Counter Control Register B (TCCR1B). Ch : Khi ngt Input Capture xy ra th thanh ghi m TCNT1 t ng c copy vo thanh ghi ICR1. Chng ta s tnh khong thi gian chu k bng cch ly gi tr thanh ghi

ICR1 tr i gi tr ICR1 trc . V gi tr ca thanh ghi m TCNT1 c gii hn l 16 bit nn trng hp chu k xung cn o qu ln (v d T= 1s = 1,000,000us) th cng thc trn sai. Trng hp ny cn cng thm mt s ln 0xffff ng vi mi ln trn b m. V khng khuyn ngh dng module Input Capture khi tn s o ca tn hiu thay i lin tc trong qu trnh hot ng. o duty cycle ca mt tn hiu bn ngoi, cn yu cu sn kch (ln hoc xung) phi c thay i sau mi capture. Thay i chiu sn kch nn c hon thnh sm nht c th sau khi thanh khi ICR1 c c. Sau s thay i ca 1 sn, c ICF1 nn c xa bi phn mm. Nu ch o tn s th khng cn xa c ICF1.

4.1.6. Giao tip truyn thng SPI v UART

4.1.6.1. Truyn thng SPI trn AVR Chun giao tip SPI c gii thiu mc 2.4.4, mc ny s lm r module SPI ca Atmega16. Trn Atmega16, cc chn SPI nh sau: SCK PB7 (chn 8), MISO PB6 (chn 7), MOSIPB5 (chn 6), SSPB4 (chn 5). Khi chip AVR c s dng lm Slave, cn set cc chn SCK input, MOSI input, MISO output v SS input. Nu l Master th SCK output, MISO output, MOSI input v khi ny chn SS khng quan trng, chng ta c th dng chn ny iu khin SS ca Slaves hoc bt k chn PORT thng thng no. Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghi iu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR. - SPCR (SPI Control Register): Thanh ghi 8 bit iu khin tt c hot ng ca SPI.

Bit 7 SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c set bng 1 v bit ngt ton cc SREG I c set bng 1, 1 ngt s xy ra sau khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l i vi chip Slave) khi truyn nhn d liu vi SPI. Bit 6 SPE (SPI Enable): Set bit ny ln 1 cho php b SPI hot ng. Nu SPIE=0 th module SPI dng hot ng. Bit 5 DORD (Data Order): Bit ny ch nh th t d liu cc bit c truyn v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln nht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c truyn trc. Bit 4 MSTR (Master/Slave Select): Nu MSTR =1 th chip c nhn din l Master, ngc li MSTR=0 th chip l Slave. Bit 3 v 2 CPOL v CPHA: y chnh l 2 bit xc lp cc ca xung gi nhp v cnh sample d liu. S kt hp 2 bit ny to thnh 4 ch hot ng ca SPI. Mt ln na,

chn ch no khng quan trng nhng phi m bo Master v Slave cng ch hot ng. V th c th 2 bit ny bng 0 trong tt c cc chip. Bit 1:0 CPR1:0: Hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR cho php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun xung clock chia cho mt h s chia. Bng di tm tt cc tc m SPI trong AVR c th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp cho chip.

Bng 15. Tc SPI theo cc bit

- SPSR (SPI Status Register): Thanh ghi trng thi ca module SPI. Trong thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi d liu c truyn hoc nhn t SPI, bit SPIF s t ng c set ln 1. Bit 6 WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1 nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi qu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp tc cho SPI.

- SPDR (SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghi gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave, d liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn trong SPDR s c truyn cho Master.

S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chung ca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi v c 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chng ta cn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tip cho cc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL, SPHA) v chn tc giao tip. Truyn thng SPI lun c khi xng bi chip Master, khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca Slave xung mc thp (gi l chn a ch) v sau

vit d liu cn truyn vo thanh ghi d liu SPDR, khi d liu va c vit vo SPDR xung gi nhp s c t ng to ra trn SCK v qu trnh truyn nhn bt u. i vi cc chip Slave, khi chn SS b ko xung n s sn sng cho qu trnh truyn nhn. Khi pht hin xung gi nhp trn SCK, Slave s bt u sample d liu n trn ng MOSI v gi d liu di trn MISO.

4.1.6.2. Truyn thng UART trn AVR Chun giao tip RS-232 c gii thiu mc 2.5.3, mc ny s lm r

module UART ca Atmega16. Vi iu khin Atmega16 c 1 module truyn thng ni tip USART, c 2 chn ta cn quan tm l chn truyn d liu TxD (Transmitted Data) v chn nhn d liu RxD (Reveived Data). V cc chn truyn/nhn d liu ch m nhim 1 chc nng c lp (hoc l truyn, hoc l nhn), kt ni cc chip AVR vi nhau (hoc kt ni AVR vi thit b h tr UART khc) cn phi u cho 2 chn ny. TxD ca thit b th nht kt ni vi RxD ca thit b 2 v ngc li. Module USART trn chip Atmega16 hot ng song cng (Full Duplex Operation), ngha l qu trnh truyn v nhn d liu c th xy ra ng thi. C 5 thanh ghi c thit k ring cho hot ng v iu khin ca USART, l: - UDR: Thanh ghi d liu, l 1 thanh ghi 8 bit cha gi tr nhn c v pht i ca USART. Thc cht thanh ghi ny c th coi nh 2 thanh ghi TXB (Transmit data Buffer) v RXB (Reveive data Buffer) c chung a ch. c UDR thu c gi tr thanh ghi m d liu nhn, vit gi tr vo UDR tng ng t gi tr vo thanh ghi m pht, chun b gi i. Ch trong cc khung truyn s dng 5, 6 hoc 7 bit d liu, cc bit cao ca thanh ghi UDR s khng c s dng.

- UCSRA (USART Control and Status Register A): L 1 trong 3 thanh ghi iu khin hot ng ca module USART.

Thanh ghi UCSRA ch yu cha cc bit trng thi nh bit bo qu trnh nhn kt thc (RXC), truyn kt thc (TXC), bo thanh ghi d liu trng (UDRE), khung truyn c li (FE), d liu trn (DOR), kim tra parity c li (PE)Mt s bit quan trng ca thanh ghi ny: UDRE (USART Data Register Empty) khi bit by bng 1 ngha l thanh ghi d liu UDR ang trng v sn sng cho mt nhim v truyn hay nhn tip theo. V th nu bn mun truyn d liu u tin bn phi kim tra xem bit UDRE c bng 1 hay khng, sau khi chc chn rng UDRE=1 hy vit d liu vo thanh ghi UDR truyn i.

U2X l bit ch nh gp i tc truyn, khi bit ny c set ln 1, tc truyn so cao gp 2 ln so vi khi bit ny mang gi tr 0. MPCM l bit chn ch hot ng a x l (multi-processor). - UCSRB (USART Control and Status Register B): y l thanh ghi quan trng iu khin USART.

RXCIE (Receive Complete Interrupt Enable) l bit cho php ngt khi qu trnh nhn kt thc. Vic nhn d liu truyn bng phng php ni tip khng ng b thng c thc hin thng qua ngt, v th bit ny thng c set bng 1 khi USART c dung nhn d liu. TXCIE (Transmit Complete Interrupt Enable) bit cho php ngt khi qu trnh truyn kt thc. UDRIE (USART Data Register Empty Interrupt Enable) l bit cho php ngt khi thanh ghi d liu UDR trng. RXEN (Receiver Enable) l mt bit quan trng iu khin b nhn ca USART, kch hot chc nng nhn d liu bn phi set bit ny ln 1. TXEN (Transmitter Enable) l bit iu khin b pht. Set bit ny ln 1 bn s khi ng b pht ca USART. UCSZ2 (Chracter size)

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