1. CPLD 2009, Mar Ron Liu

2. Agenda of Day1 Course Introduction 3. Course ObjectivesDigital Logic Basic Concept Understanding of FPGA/CPLD device Verilog HDL Simulation and Verification by ModelSim Verilog HDL for synthesis Altera design flow in Quartus Design a project with GFEC MAX II Starter Kit 4. Course Flow Introduction Coding for Synthesis FPGA/CPLD Introduction QuartusBoolean Algebra Verilog HDLPost Simulation BasicIntroduction GFECIntroductionStarter Kit ModelSim FSM Design Combination Logic Project Sequential Logic 5. Course ScheduleDay1: 3/2 Day2: 3/9 Day3: 3/16 Day4: 3/23 Day5: 3/30 8:10~11:50, 13:10~16:40 6. Tools: What we needWindows PCVerilog HDL Simulator:Modelsim, to compile and execute HDL forsimulation, debugging, verificationDevice/Board: GFEC MAX II Starter Kit, IO BoardSynthesizer/Fitter/Porgrammer: Quartus/Altera 7. Reference Material, books[Verliog ] Verilog-() 2006/09 Verilog -2007/07 Verilog FPGA()() 2008/11 [FPGA/CPLD/ASIC ]FPGA CPLDs FPGA2006/08 Quartus II [ASIC, PLD, HDL]Application-Specific Integrated Circuits, Michael John, Sebastian Smith, Addison Wesleyon-line book http://www.edacafe.com/books/ASIC/ASICs.php 8. Reference Material, Tool, Web starter Kit] GFEC MAX II Starter Kit, , CD:User GuideMAXII_SG_V2.pdf MAX II Device HandbookCD:Altera_handbookmax2_mii5v1.pdf MAX _II_Training_tutorialQuartus_II_Tutorial.ppt [Altera][ Altera DOC QuartusII Handbook Vol2, 3 Altera on-line training, http://www.altera.com/education/training/curriculum/cpld/trn-cpld.html[ModelSim]Tools on-line help [Other]http://en.wikipedia.org/