Chapter 9 Memory Management 記憶體管理 Page 2 Memory Management Background Logical versus...

Chapter 9 Memory Management記憶體管理

Memory Management

Background

Logical versus Physical Address Space

Swapping

Contiguous Allocation

Paging

Segmentation

Segmentation with Paging

Background

Program must be brought into memory and placed within a process for it to be executed.

Input queue – collection of processes on the disk that are waiting to be brought into memory for execution.

User programs go through several steps before being executed.

§ 9.1

輸入佇列

sourceprogramsource

program

loadmoduleload

module

objectmoduleobject

module

compiler orassembler

compiler orassembler

loaderloader

linkageeditor

linkageeditor

in-memorybinary

memoryimage

in-memorybinary

memoryimage

otherobject

modules

otherobject

modules

systemlibrary

systemlibrary

dynamicallyloadedsystemlibrary

dynamicallyloadedsystemlibrary

compiletime

loadtime

executiontime (run

time)

Addresses in the source program are generally symbolic (such as

count)Compiler will bind symbolic

addresses to relocatable addresses (such as “14 bytes

from the beginning)

bind relocatable addresses to

absolute addresses

MultistepProcessingof a userprogram

Each binding is a mapping from oneaddress space to

another

Each binding is a mapping from oneaddress space to

another

綁定

Binding of Instructions and Data to Memory

Compile time: If it is known at compile time where the process will reside in memory, absolute code can be generated; must recompile code if starting location changes. (MS-DOS .com format)Load time: If memory location is not known at compile time,Compiler must generate relocatable code. The final biding is delayed until load time.Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

Address binding of instructions and data to memory addresses canhappen at three different stages.

§ 9.1.1

綁定

可重置

Binding of Instructions and Data to Memory

Compile time: If it is known at compile time where the process will reside in memory, absolute code can be generated; must recompile code if starting location changes. (MS-DOS .com format)Load time: If memory location is not known at compile time,Compiler must generate relocatable code. The final biding is delayed until load time.Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

Address binding of instructions and data to memory addresses canhappen at three different stages.

§ 9.1.1

True-False Question:( ) It is necessary to determine where the

program will reside in memory before loading, otherwise the program will not be able to execute because it does not know where to locate the program.

Answer: ×

Logical vs. Physical Address Space

Logical address (virtual address) – generated by the CPU

Physical address – address seen by the memory unit

The logical and physical addresses are the same in compile-time and load-time address binding but different in execution-time address binding.

§ 9.1.2

Logical vs. Physical Address Space

Logical address (virtual address) – generated by the CPU

Physical address – address seen by the memory unit

The logical and physical addresses are the same in compile-time and load-time address binding but different in execution-time address binding.

§ 9.1.2

True-False Question:( ) Logical address can be used to learn where

the program will be running in memory before execution.

Answer: ×

The run-time mapping from virtual to physical addresses is done by the memory-management unit (MMU), which is a hardware device.The value in the relocation register is added to every address generated by a user process at the time it is sent to memory.The user program never sees the real physical addresses.

CPU

14000

memory+

relocationregister

physicaladdress

14346

logicaladdress

346

MMU

Memory Management Unit (MMU)

重置暫存器

Dynamic Loading

Routine is not loaded until it is calledUse dynamic loading to obtain better memory-space utilization; unused routine is never loaded.Useful when large amounts of code are needed to handle infrequently occurring cases, such as error routines.Although the total program size may be large, the portion that is actually used (loaded) may be much smaller.No special support from the operating system is required implemented through program design.

§ 9.1.3動態載入

Dynamic LinkingIn static linking, system language libraries are treated like any other object module and are combined by the loader into all program’s binary image, wasting disk space and main memory.In dynamic linking, linking postponed until execution time. A stub is included in the image for each library-routine reference. The stub indicates how to locate the memory-resident library routine, or how to load the library if the routine is not already present.Stub replaces itself with the address of the routine, and executes the routine.All processes that use a language library execute only one copy of the library code.

(記號 )

A small piece of code

§ 9.1.4

Version

With dynamic linking, programs reference the new version of the library automatically when the library was updated.

Since more than one version of a library may be loaded into memory, the version information is included both in the program and the library. Only the programs compiled with new library are affected…called shared library.

Overlays

Keep in memory only those instructions and data that are needed at any given time.Needed when process is larger than amount of memory allocated to it.When instruction not in memory are needed, they are loaded into space that was occupied previously by no longer needed instructions.

Pass 1 70KPass 2 80KSymbol table 20KCommon routines 30K

total 200K (only 150K available)

Overlay AOverlay B

§ 9.1.5重疊

Overlays

pass 1 pass 270K 80K

symboltable

commonroutines

overlaydriver

20K

30K

10K

Fig. 9.3 Overlays for a two-pass assembler.

SwappingA process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.

Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.

Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.

If the binding is done at assembly or load time, the process will be swapped back to the same location. If execution time binding is used, then it is possible to swap into different memory space.

§ 9.2置換

換出、換入

SwappingA process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution.

Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.

Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed.

If the binding is done at assembly or load time, the process will be swapped back to the same location. If execution time binding is used, then it is possible to swap into different memory space.

§ 9.2

True-False Question:( ) If the binding is performed at execution

time, the program will be swapped back to the same location where the program was executed last time.

Answer: ×

Schematic View of Swapping

SwappingMajor part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped.Useful to know exactly how much memory a user process is using, then swap only what is actually used, reducing swap time. For this to work, need to inform system any changes in memory requirements.A process must be completely idle before swapping, particularly with pending I/O. We may (1) never to swap a process with pending I/O, or (2) to execute I/O only into OS buffers.Modified versions of swapping are found on many systems, i.e., UNIX and Microsoft Windows.


Main memory usually divided into two partitions:– Resident operating system, usually held in low memory with

interrupt vector.– User processes then held in high memory.

Relocation-register scheme used to protect user processes from each other, and from changing operating-system code and data.Relocation register contains value of smallest physical address; limit register contains range of logical addresses –each logical address must be less than the limit register.The relocation-register scheme provides an effective way to allow the OS size to change dynamically.

§ 9.3

連續配置

界限暫存器


CPU

limitregister

relocationregister

memory

logicaladdress

<yes

+

physicaladdress

trap; addressing error

no

Fig. 9.5 Hardware support for relocation and limit registers.


Simplest memory allocation: divide memory into a number of fixed-sized partitions.

Each partition may contain exactly one process.

The degree of multiprogramming is bound by the number of partitions.

Used by IBM OS/360

分割


Simplest memory allocation: divide memory into a number of fixed-sized partitions.

Each partition may contain exactly one process.

The degree of multiprogramming is bound by the number of partitions.

Used by IBM OS/360

True-False Question:( ) Multiprogramming is impossible in fixed-

sized partition because each process may require different sized memory space.

Answer: ×

Contiguous Allocation (Cont.)Hole – block of available memory; holes of various size are scattered throughout memory.

When a process arrives, it is allocated memory from a hole large enough to accommodate it.

Operating system maintains information about:a) allocated partitions b) free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

Contiguous Allocation (Cont.)

If the hole is too large for arriving process, it is split into two: one part is allocated to the arriving process; the other is returned to the set of holes.When a process terminates, the holes are placed back in the set of holes.If the new hole is adjacent to other holes, merge to form one larger hole and check if it can satisfy any process waiting for memory.

Dynamic Storage Allocation Problem

First-fit: Allocate the first hole that is big enough.Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole.Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole.

…How to satisfy a request of size n from a list of free holes.

First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

Dynamic Storage-Allocation Problem

First-fit: Allocate the first hole that is big enough.Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole.Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole.

…How to satisfy a request of size n from a list of free holes.

First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

Multiple Choices Question:( ) Which of the following strategies does not

need to search the entire list of free holes before applying it?(a) first fit (b) best fit (c) worst fit (d) better fit

Answer: a

FragmentationExternal fragmentation – When free memory space is broken into little pieces, although total memory space exists to satisfy a request, but it is not contiguous.

50-percent rule: given N allocated blocks, another 0.5N blocks will be lost due to fragmentation.

Internal fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.

斷裂片段

FragmentationReduce external fragmentation by compaction– Shuffle memory contents to place all free

memory together in one large block.– Compaction is possible only if relocation is

dynamic, and is done at execution time.

壓緊

PagingLogical address space of a process can be noncontiguous.Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8192 bytes).Divide logical memory into blocks of same size called pages.Keep track of all free frames.To run a program of size n pages, need to find n free frames and load program.Set up a page table to translate logical to physical addresses. Internal fragmentation.

§ 9.4分頁

框

Address Translation SchemeAddress generated by CPU is divided into:– Page number (p) – used as an index into a page table

which contains base address of each page in physical memory.

– Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

p d

page number page offset

m － n n

Size of logical address space: 2m

Size of one page: 2n

the high-order m － n bits: page number

n low-order bits designate the page offset.

位移

分頁表

Address Translation Architecture

Paging Example

0 a 1 b 2 c 3 d 4 e 5 f 6 g 7 h 8 i 9 j10 k11 l12 m13 n14 o15 p

5612

0123

0

4

8

12

16

20

24

28

Ijklmnop

abcd

efgh

logicalmemory

page table

physical memory

Paging Example

When we use paging, no external fragmentation: Any free frame can be allocated to a process that needs it.

But may have internal fragmentation: If a process do not fall on page boundaries, the last frame allocated may not be completely full.

Average internal fragmentation : one-half page per process.

However, overhead involved in each page-table entry.

Generally, page sizes getting larger as processes, data sets, and main memory have become larger.

Today, pages typically are between 2 and 8 KB.

Suggest small page sizes

Suggest larger page sizes

When we use paging, no external fragmentation: Any free frame can be allocated to a process that needs it.

But may have internal fragmentation: If a process do not fall on page boundaries, the last frame allocated may not be completely full.

Average internal fragmentation : one-half page per process.

However, overhead involved in each page-table entry.

Generally, page sizes getting larger as processes, data sets, and main memory have become larger.

Today, pages typically are between 2 and 8 KB.

Suggest small page sizes

Suggest larger page sizes

True-False Question:( ) Although it is impossible for paging

scheme to generate any external fragmentation, the internal fragmentation is still inevitable.

Answer: o

User’s view and physical view

User program views memory as one single contiguous space. In fact, the user program is scattered throughout physical memory.

OS manage a frame table, recording the allocation details of physical memory.

Each entry of the frame table indicating if a page frame is free or allocated and to which page.

13

14

15

16

17

18

19

20

21

page 0page 1page 2page 3

new process

free frame list1413182015

page1

page0

page2

page3

13

14

15

16

17

18

19

20

21

page 0page 1page 2page 3

new process

free frame list15

14131820

0123

new process page table

Fig. 9.9 Free frames. (a) Before allocation. (b) After allocation

User’s View

Physical View

Structure of the Page Table

Page table can be implemented as a set of registers with very high-speed logic.For large page table, more feasible if keep it in main memory and use a page-table base register (PTBR) points to the page table and page-table length register (PRLR) indicates size of the page table.In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.This problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs)

§ 9.4.2

Structure of the Page Table

Page table can be implemented as a set of registers with very high-speed logic.For large page table, more feasible if keep it in main memory and use a page-table base register (PTBR) points to the page table and page-table length register (PRLR) indicates size of the page table.In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.This problem can be solved by the use of a special fast-lookup hardware cache called associative registers or translation look-aside buffers (TLBs)

§ 9.4.2

Short Answer Question:Please explain why it requires two memory

accesses for every instruction access if the page table is placed in main memory.

Associative RegisterAssociative registers – When presented with an item, it is compared with all keys simultaneously.

If the page number is found in the associative registers, its frame number is immediately available and used to access memory.If the page number is not in the associative registers, a memory reference to the page table must be made.– Associative register is updated for next reference

Page # Frame #

相關暫存器

page3

13

14

15

16

17

18

19

20

21

page 0page 1page 2page 3page 4page 5

new process

012345

page table

14

20

Page # Frame #

0 14

3 20

disk addressdisk address


associative register

page3

13

14

15

16

17

18

19

20

21


new process

012345

page table

14

20

Page # Frame #

0 14

3 20




True-False Question:( ) When referencing the

memory, the page table should be searched first and the associative registers next.

Answer: ×

page3

13

14

15

16

17

18

19

20

21


new process

012345

page table

14

20

Page # Frame #

0 14

3 20




True-False Question:( ) With powerful and effective

associative registers, the page table has no use and can be removed from the system architecture.

Answer: ×

Effective Access TimeAssociative Lookup = time unitAssume memory cycle time is 1 microsecondHit ration – percentage of times that a page number is found in the associative registersHit ratio = Effective Access Time (EAT)

EAT = (1 + ) + (2 + )(1 – )= 2 + –

The hit ratio is related to the number of associative registers.Motorola 68030 (for Mac.): 22 entry TLB.Intel 80486: 32 entry with 98% hit ratio.UltraSPARC I & II: two TLBs for instruction and data separately. Each is 64 entries long.

有效存取時間

Memory Protection

Memory protection implemented by associating protection bit with each frame.One bit can define a page to be read&write or read only. It also can be expanded to provide finer level of protection.Valid-invalid bit attached to each entry in the page table:– “valid” indicates that the associated page is in the

process’ logical address space, and is thus a legal page.– “invalid” indicates that the page is not in the process’

logical address space.

Illegal addresses are trapped.

page 1

page 2

page 3

page 4

page 510468

12287

0 2 v

1 3 v

2 4 v

3 7 v

4 8 v

5 9 v

6 0 i

7 0 i

page table

valid-invalid bitframe number

0

1

2 page 0

3 page 1

4 page 2

5

6

7 page 3

8 page 4

9 page 5

…

page nFig. 9.11 Valid (v) or invalid (i) bit in a page table.

Memory Protection

00000

10468

12287

page 5page 5

page 4

Internal fragmentation

Multilevel Paging

Modern computer support large address space and the page table becomes large.– 32bit address space with 4K bytes page size requires 4

megabytes page table for each process.

Simple solution: divide the page table into smaller pieces.

Two-level paging algorithm: the page table itself is also paged.

§ 9.4.3

多層分頁

Two-level Paging

Two-Level Paging ExampleA logical address (on 32-bit machine with 4K page size) is divided into:– a page number consisting of 20 bits.– a page offset consisting of 12 bits.

Since the page table is paged, the page number is further divided into:– a 10-bit page number. – a 10-bit page offset.

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the displacement within the page of the outer page table.


p1 p2 d

10 10 12

Address-Translation Scheme

Address-translation scheme for a two-level 32-bit paging architecture

p1 p2 d

p1

p2

d

logical address

outer-pagetable

page ofpage table

VAX Architecture

32-bit machine with page size 512 bytes.

logical address space is divided into four equal sections, each consists of 230 bytes.

Each section uses page table with size221 bits * 4 bytes per entry = 8 megabytes.

page offset

s p d

2 21 9

section

Page the outer page!

Two-level Paging

For a system with 64-bit logical address space, two-level is not enough.Example: page size: 4K bytes → page table 252 entries

inner page offset

p1 p2 d

42 10 12

outer page

Large

Three-level Paging

SPARC (32-bit addressing): three-levelMotorola 68030 (32-bit): four-level paging.

inner page offset

p1 p2 d

32 10 12

outer page2nd outer page

p3

10

Four-level paging!Still Large

Multilevel Paging and Performance

Since each level is stored as a separate table in memory, covering a logical address to a physical one may take four memory accesses.Even though time needed for one memory access is quintupled, caching permits performance to remain reasonable.Cache hit rate of 98 percent yields:

effective access time = 0.98 x 120 + 0.02 x 520

= 128 nanoseconds.which is only a 28 percent slowdown in memory access time.

Inverted Page Table

One entry for each real page of memory.

Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page.

Decreases memory needed to store each page table, but increases time needed to search the whole table when a page reference occurs.

Use hash table to limit the search to one — or at most a few — page-table entries.

§ 9.4.4

反轉分頁表

Inverted Page Table Architecture

Shared Pages

Reentrant code is non-self-modifying code, it never change during execution. Two or more processes can execute the same code at the same time. (i.e., text editors, compilers, window systems).

The data for two different processes will vary for each process.

Systems that use inverted page tables have difficulty implementing shared memory.

§ 9.4.5

重入

Shared Pages Example

Segmentation

User view memory as a collection of variable-sized segments with no ordering among them.Segmentation: a memory-management scheme that supports user view of memory. A program is a collection of segments. A segment is a logical unit such as:

main program,procedure, function,local variables, global variables,common block,stack,symbol table, arrays

§ 9.5

分段

Segmentation

User view memory as a collection of variable-sized segments with no ordering among them.Segmentation: a memory-management scheme that supports user view of memory. A program is a collection of segments. A segment is a logical unit such as:

main program,procedure, function,local variables, global variables,common block,stack,symbol table, arrays

§ 9.5

Short Answer Question:Segmentation allow variable sized segments to be

existed in the main memory. Compare this scheme with variable-sized partitions, which also allow different sized pages to be located in the main memory.

Logical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

Segmentation Architecture

The user specifies each address by two quantities: a segment name and an offset.

Logical address consists of a two tuple:

<segment-number, offset>

Compiler automatically constructs segments reflecting the input program.

Pascal: segments for 1. global variable, 2. procedure call stack, 3. code portion for procedure or function, 4. local variable

FORTRAN: segment for each common block.


Segment table – maps two-dimensional user-defined addresses into one-dimensional physical addresses; each table entry has: (Fig. 9.17)– base – contains the starting physical address

where the segments reside in memory.– limit – specifies the length of the segment.

Example: Fig. 9.18


s dCPU

limit base

< +

s

segmenttable

trap; addressing errorphysical memory

yes

no

Fig. 9.17 Segmentation hardware


subroutine stack

symboltable

Sqrt

mainprogram

segment 3

segment 0

segment 4

segment 1segment 2

logical address space

limit base

1000 400 40011001000

14006300430032004700

01234

segment table

segment 0

segment 3

segment 2

segment 4

segment 1

1400

2400

3200

4300

4700

5700

6300

6700

physical memoryFig. 9.18 Example of segmentation.


subroutine stack

symboltable

Sqrt

mainprogram

segment 3

segment 0

segment 4

segment 1segment 2

logical address space

limit base

1000 400 40011001000

14006300430032004700

01234

segment table

segment 0

segment 3

segment 2

segment 4

segment 1

1400

2400

3200

4300

4700

5700

6300

6700

physical memoryFig. 9.18 Example of segmentation.

Multiple Choices Question:( ) What is the physical

address translated from the logical address

(a) 3400 (b) 4500 (c) 3200 (d) 1600 (e) 400

Answer: b

2 200

Block containingsegment 4


47

0001001

0 disk address

--

--

--

--

--

disk addressdisk addressdisk address


--

--

--

segmentnumber

01234567

segmentnumber

0123456

7

segmentnumber

blockaddress

Associative registers

Segment table in memory

Virtual memory

Real memory

reference segment 4: okreference segment 5: segment fault, cause 5 to be brought in to real memory



475

0001001

0 disk address

--

--

--

--

--

disk addressdisk addressdisk address


--

--

--

segmentnumber

01234567

segmentnumber

0123456

7

segmentnumber

blockaddress

Associative registers

Segment table in memory

Virtual memory

Real memory


reference segment 4: okreference segment 5: segment fault, cause 5 to be brought in to real memory

Segmentation Architecture (Cont.)

Since segments represent a semantically defined portion, it is likely that all entries in the segment will be used the same way.MMU will check the protection bits associated with each segment-table entry to prevent illegal accesses to memory.Segments are shared when entries in the segment tables of two different processes point to the same physical location.The sharing occurs at the segment level. Thus any information can be shared if it is defined to be a segment.

Sharing of segments

Fragmentation in Segmentation

With dynamic storage allocation, usually uses best-fit or first-fit in segmentation.

May cause external fragmentation, when all blocks of free memory are too small to accommodate a segment.

Process have to wait, or use compaction.

Compaction can help? depend on the segment size.Discusses: large vs. small segment size.

§ 9.5.4


Motorola 68000 (based on flat address space) and Intel 80X86 and Pentium (based on segmentation) are both merging toward a mixture of paging and segmentation.

As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

max. no. of segments per process: 16Ksegment size limit: 4 Gigabytespage size: 4K bytes

§ 9.6


Motorola 68000 (based on flat address space) and Intel 80X86 and Pentium (based on segmentation) are both merging toward a mixture of paging and segmentation.

As shown in the following diagram, the Intel 386 uses segmentation with paging for memory management with a two-level paging scheme.

max. no. of segments per process: 16Ksegment size limit: 4 Gigabytespage size: 4K bytes

§ 9.6

True-False Question:( ) Segmentation with Paging combined the

advantages of Segmentation and Paging and therefore eliminated the problem of internal and external fragmentation all together.

Answer: x

Intel 30386 address translation


logical address space is divide into two parititions:– first partition: private, consists 8K segments

Info. about first partition is kept in the local descriptor table (LDT)

– second partition: shared, another 8K segmentsInfo. is kept in the global descriptor table (GDT)

Each entry in the LDT and GDT table consists of 8 bytes, with detailed information about a particular segment including the base location and length of the segment.


logical address (selector, offset)– selector:

– offset: 32bit number

6 segment registers caching descriptors from LDT or GDT.

physical address:base and limit info. in the LDT or GDT are used to generate a linear address.

s: segment numberg: in GDT or LDTp: protection

s g p

13 1 2

A memory addressing scheme used in processors

where the whole memory can be accessed using a single address that fits in a single

register or instruction.

p1 p2 d

10 10 12


Segment 0 : page 0 ~ 3Segment 1 : page 0 ~ 1Segment 2 : page 0 ~ 3

segmentnumber

012

Real memory

address ofpage table

0 disk loc. --0 disk loc. --1 -- 491 -- 73

1 -- 861 -- 35

1 -- 610 disk loc. --0 disk loc. --0 disk loc. --

fDiskaddress

Framenumber

012

3

0

1

012

3

Page number

Page table for segment 2



Segmentnumber

Pagenumber

Framenumber

0 2 490 3 731 0 86

2 0 611 1 35

Segment 1, page 1

Segment 0, page 2

Segment 2, page 0

Segment 0, page 3

Segment 1, page 0

35

49

61

73

86

Associative Registers

Chapter 9 Memory Management 記憶體管理 Page 2 Memory Management Background Logical versus...

Documents

Transcript of Chapter 9 Memory Management 記憶體管理 Page 2 Memory Management Background Logical versus...