BI 4

THIT K MCH GII M LED 7 ON

1.1 Mc tiu

Sinh vin s thc hin mch gii m hin th cc s t 0 n 9 s dng LED 7 on. lm tt Lab 4, sinh

vin cn phi nm trc nh v cch thit k, bin dch v m phng mt mch in n gin trn Quartus II.

1.2 Ni dung thc hnh

Cho mch sau:

Di y l bng s tht ca mch gii m cho LED-7-on trn dng hin th cc k t t 0 n 9 (cc gi tr

khc khng quan tm) Sinh vin hon thnh bng s tht sau.

Ch :

Cc on LED tch cc mc thp mc 0 on LED sng, mc 1 on LED tt

Cc gi tr X mang ngha khng quan tm (dont care)

INPUT DISPLAY OUTPUT

SW[3:0] DIGIT HEX[0] HEX[1] HEX[2] HEX[3] HEX[4] HEX[5] HEX[6]

0000 0 0 0 0 0 0 0 1

0001 1 1 0 0 1 1 1 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9 0 0 0 0 1 0 0

X X X X X X X X X

Da vo bng s tht trn sinh vin tin hnh lp ba Karnaugh cho 7 on ca HEX tng ng vi 7 hm, t 7

hm tin hnh v mch gii m cho LED-7-on bao gm 4 u vo v 7 u ra.

1.3 Hng dn thc hnh

1. To mt project Quartus mi, t tn: E/lab4/lab4_MSSV

2. Thit k mt mch theo mch logic thit k bn trn

3. Gn pin cho mch trn

4. Bin dch phn tch, tng hp v to ra file .sof

5. M phng mch trn wareform.

6. Np file thc thi ln FPGA. Kim tra hot ng ca mch.