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![Page 1: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/1.jpg)
Area-I/O Flip-Chip Routing for Chip-Package Co-Design
Progress Report
方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory
Graduate Institute of Electronics Engineering
National Taiwan University
October 24, 2008
1
![Page 2: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/2.jpg)
2
Outline
․ Contributions
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
6
3
1
45
Block
Block Port
I/O Buffer
I/O Pad1 2
3 4
5
62
6
3
1
45
3
4
21
P/G
Bump Pad
2
87
Blocks (Block Ports)I/O Buffers (I/O Pads)
Bump Pads
Intermediate Nodes and Tile Nodes Insertion
Graph Construction
Cost and Capacity Assignment
Flow Network Solving
Passing Point Assignment
Global Routing RDL Routing
RDL Routing Result Output
Net Ordering Determination
Chip-level I/O Netlist Output
Chip-level Routing
Maze Routing
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
![Page 3: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/3.jpg)
3
Outline
․ Contributions
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
6
3
1
45
Block
Block Port
I/O Buffer
I/O Pad1 2
3 4
5
62
6
3
1
45
3
4
21
P/G
Bump Pad
2
87
Blocks (Block Ports)I/O Buffers (I/O Pads)
Bump Pads
Intermediate Nodes and Tile Nodes Insertion
Graph Construction
Cost and Capacity Assignment
Flow Network Solving
Passing Point Assignment
Global Routing RDL Routing
RDL Routing Result Output
Net Ordering Determination
Chip-level I/O Netlist Output
Chip-level Routing
Maze Routing
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
![Page 4: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/4.jpg)
4
Contributions
․ Present the first Area-I/O RDL routing algorithm for chip-package co-design in the literature
Propose a network-flow based routing algorithm Consider multi-RDL assignment Extra consider the assignment among block ports and I/O pads
․ Try to achieve 100% RDL routability and the optimal global-routing wirelength
I/O padBump pad
U-turn routeCut line among sectors
Peripheral I/O’s Area I/O’s
![Page 5: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/5.jpg)
5
Outline
․ Contributions
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
6
3
1
45
Block
Block Port
I/O Buffer
I/O Pad1 2
3 4
5
62
6
3
1
45
3
4
21
P/G
Bump Pad
2
87
Blocks (Block Ports)I/O Buffers (I/O Pads)
Bump Pads
Intermediate Nodes and Tile Nodes Insertion
Graph Construction
Cost and Capacity Assignment
Flow Network Solving
Passing Point Assignment
Global Routing RDL Routing
RDL Routing Result Output
Net Ordering Determination
Chip-level I/O Netlist Output
Chip-level Routing
Maze Routing
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
![Page 6: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/6.jpg)
6
Flip-Chip Technology
․ Provides a high chip-density solution to the demand for more I/O pads of VLSI designs
․ Is popular for high-speed and low-power applications Lower power consumption Smaller delay Smaller inductance effect
Flip-Chip Package
Bump ball
I/O pad (I/O buffer)Bump pad Flip-Chip (Die)
![Page 7: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/7.jpg)
7
Flip-Chip Routing
․ In modern flip-chip designs, place the I/O pads into the whole area of the die
․ Use extra metal layers, called Re-Distribution Layers (RDL’s), to redistribute the I/O pads to the bump pads
․ Apply an RDL router to route the I/O pads to the bump pads
Cross section of RDL
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
RDL routing example
Bump pad
I/O pad
![Page 8: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/8.jpg)
8
Chip-Package Co-Design
․ Extra consider the assignment among block ports and I/O pads
Allow an RDL router to choose a proper I/O buffer for each net
․ Have more flexibility to place blocks and I/O buffers Reduce the constraints from the connections between block ports and
I/O buffers to have better floorplanning results and shorter CUP times
Package Chip
2
6
31
4
5
43
5
2 6
1
Bump pad
6
31
4
5
Block
Block port
I/O buffer
1 2
3 4
5
6
I/O pad
2
![Page 9: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/9.jpg)
9
Flip-Chip Routing Structure
․ Interval: two adjacent bump pads
․ Tile: four adjacent bump pads
․ li/wj: column i/row j of bump pads
Package-level structure Chip-level structure
![Page 10: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/10.jpg)
10
Outline
․ Contributions
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
6
3
1
45
Block
Block Port
I/O Buffer
I/O Pad1 2
3 4
5
62
6
3
1
45
3
4
21
P/G
Bump Pad
2
87
Blocks (Block Ports)I/O Buffers (I/O Pads)
Bump Pads
Intermediate Nodes and Tile Nodes Insertion
Graph Construction
Cost and Capacity Assignment
Flow Network Solving
Passing Point Assignment
Global Routing RDL Routing
RDL Routing Result Output
Net Ordering Determination
Chip-level I/O Netlist Output
Chip-level Routing
Maze Routing
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
![Page 11: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/11.jpg)
11
Problem Definition
․ Problem: Multi-layer pin assignment and Area-I/O RDL routing for chip-package co-design
․ Inputs: A die with block ports and I/O pads (buffers in
different sizes) A flip-chip package with bump pads The number of RDL’s Design rules
․ Output: A routing solution without design-rule violation
․ Objective: Connect all nets to minimize the total wirelength
![Page 12: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/12.jpg)
12
Outline
․ Contributions
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
6
3
1
45
Block
Block Port
I/O Buffer
I/O Pad1 2
3 4
5
62
6
3
1
45
3
4
21
P/G
Bump Pad
2
87
Blocks (Block Ports)I/O Buffers (I/O Pads)
Bump Pads
Intermediate Nodes and Tile Nodes Insertion
Graph Construction
Cost and Capacity Assignment
Flow Network Solving
Passing Point Assignment
Global Routing RDL Routing
RDL Routing Result Output
Net Ordering Determination
Chip-level I/O Netlist Output
Chip-level Routing
Maze Routing
PASV (L3)
Top Metal Top Metal
M7
M1Core Cells I/O Buffers
Other routing under bump
Bump Bump
Redistribution Layer
![Page 13: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/13.jpg)
13
The Routing FlowBlocks (Block Ports),I/O Buffers (I/O Pads),Bump Pads, # RDL’s
Global Routing RDL Routing
RDL Routing Result Output
Chip-level I/O Netlist Output
Chip-level Routing
1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow
1. Find a routable net order
2. Refine the global-routing paths to meet design rules
![Page 14: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/14.jpg)
14
The Routing FlowBlocks (Block Ports),I/O Buffers (I/O Pads),Bump Pads, # RDL’s
Global Routing RDL Routing
RDL Routing Result Output
Chip-level I/O Netlist Output
Chip-level Routing
1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow
1. Find a routable net order
2. Refine the global-routing paths to meet design rules
![Page 15: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/15.jpg)
15
Intermediate and Tile Nodes Insertion
․ Tile node: at the middle of each tile
․ Interval node: at the middle of each interval
Bump padIntermediate node
Tile node
I/O pad
![Page 16: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/16.jpg)
16
Basic Network Formulation
․ Min-Cost Max-Flow (MCMF) Algorithm (Concurrent Assignment) Nodes: block port p ∈ P, I/O pad q ∈ Q, bump pad b ∈ B,
intermediate node d ∈ D, tile node t ∈ T Edges: e(p, q), e(q, b), e(q, t), e(q, d), e(d, b), e(d, t), e(t, b), and e(t, d) Avoid crossing of edges => Avoid crossing of wires Add intermediate nodes and tile nodes to avoid wire congestion
I/O Pads
(Type 1)
dTile
p
I/O Pads
(Type 2)
I/O Pads
(Type 3)
I/O Pads
(Type 4)
t
b
Block Port
Cross section
d
t
b
Vertical view
Intermediate node
Bump pad
![Page 17: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/17.jpg)
17
Cost/Capacity Assignment
․ Basic edge cost=edge length
․ There are 2/10 types of nodes/edges and their capacities are Cd/Ct: maximum number of nets allowed to pass an interval/tile
Intermediate node=Cd; Tile node=Ct
e(source, p)=1, e(p, q)=1, e(q, b)=1, e(q, d)=1, e(q, t)=1, e(d, b)=1, e(d, t)=Ct, e(t, b)=1, e(t, d)=Cd, and e(b, sink)=1
d
t b
b
s t
1
1
1
1
1
1
1
1
1
1
1
CdCt
Tile node
Intermediate node
1
Block port
I/O pad
Bump pad
p
p q
q
![Page 18: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/18.jpg)
18
Routing Completion Guarantee
․ Theorem: Given a set of block ports, a set of I/O pads, and a set of bump
pads, if there exists a feasible solution computed by the MCMF algorithm, we can guarantee 100% RDL routing completion
Package-level Chip-level
2
6
31
4
5
43
5
2 6
1
Bump pad
6
31
4
5
Block
Block port
I/O buffer
1 2
3 4
5
6
I/O pad
2
![Page 19: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/19.jpg)
19
The Routing FlowBlocks (Block Ports),I/O Buffers (I/O Pads),Bump Pads, # RDL’s
Global Routing RDL Routing
RDL Routing Result Output
Chip-level I/O Netlist Output
Chip-level Routing
1. Construct a flow network to simultaneously assign and route block ports to bump pads via I/O pads 2. Consider routing resource in the flow network to avoid overflow
1. Find a routable net order
2. Refine the global-routing paths to meet design rules
![Page 20: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/20.jpg)
20
Passing-Point Assignment
․ After network solving, split edges to get independent nets without any wire crossing
According to the flows passing each tile node, refine edges Split each intermediate node and edge to get final global-
routing paths
5
4
2
1
3
52
1 4
5
3
4
31
2
4
4
31
2
4
: Bump Pads
: I/O Pads
: Intermediate Nodes : Passing Points
: Edges
: Net Segments
Tile Node
2
2
113
12
1
1
1
1
Flow
![Page 21: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/21.jpg)
21
: Bump Pad
․ Modify the net ordering determination (Hsu, in DAC-83)
․ Consist of 3 steps Step 1: redraw the boundary Step 2: decide the source s and destination d for each wire Step 3: decide the net ordering by a stack
․ Apply maze routing
: I/O Pad
Net Ordering Determination and Maze Routing
d
4
2’
1
3
5’2
1’ 4’
5
3’s
ds
ds s
d 1’ 5
2’
3’ 3’
1’ 2’ 3’5
: Passing Point : Net Segment
5
4
2’
1
3
5’2
1’ 4’
5
3’
![Page 22: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/22.jpg)
22
Outline
․ Introduction
․ Problem Formulation
․ The Routing Algorithm
․ Conclusions
![Page 23: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/23.jpg)
23
Conclusions
․ Propose a flip-chip router for chip-package co-design considering I/O assignment and total wirelength minimization
․ Try to achieve 100% RDL routability and the optimal global-routing wirelength by using network flow
![Page 24: Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.](https://reader035.fdocument.pub/reader035/viewer/2022062717/56649e1a5503460f94b07f6e/html5/thumbnails/24.jpg)
24
Schedule
․ Stage 1 (1/2008 – 4/2008): done Literature survey Development of a placement and routing algorithm considering
the objectives
․ Stage 2 (5/2008 – 7/2008): done Implementation of the placement and routing algorithm
․ Stage 3 (8/2008 – 9/2008): done Optimization of the objectives
․ Stage 4-1 (9/2008 – 11/2008): done GUI generation and integration of all functions Paper writing and documentation
․ (Extra) Stage 4-2 (9/2008 – ) Extensions to Etron designs
․ (Extra) Stage 4-3 (9/2008 – ) Study the Area-I/O Flip-Chip Routing for Chip-Package Co-
Design