9-26GHz Wideband CMOS LNA Design thesis-9367519 · 9−25GHz寬頻COMS LNA 9−25GHz Wideband CMOS...

925GHz COMS LNA

925GHz Wideband CMOS LNA Design

925GHz COMS LNA


StudentDarren (Qi-Yuan) Horng

AdvisorRobert (Shu-I) Hu

A Thesis

Submitted to College of Electrical and Computer Engineering

National Chiao Tung University

in partial Fulfillment of the Requirements

for the Degree of

Master of Science in

Electronics and Electro-Optical Engineering

August 2008

Hsinchu, Taiwan, Republic of China

i

925GHz CMOS LNA

0.18um RF-CMOS

9 25GHz LNA 0.18um CMOS LNA 3 10GHz 0.18um LNA 24GHz 0.18um CMOS Ka LNA

L R-C nMOS 0.18um CIC S21 10-16dB GHz 4.5dB Vdd 1.2 2.0 58111mW 0.945 x 1.295 mm

ii


StudentQi-Yuan Horng

AdvisorsDr. Shu-I Hu

Degree Program of Electrical and Computer Engineering National Chiao Tung University

ABSTRACT

A procedure is to introduce a 925GHz wide band LAN design which uses

0.18um RF-CMOS technology. In general, the 0.18um CMOS LNA usually be designed for 310GHz operating range. Otherwise, the narrowband LNA design already is proved that it could work at 24GHz. So, we would like to design a LNA and it can work at Ka band.

The CIC measured result shows LNA S21 has 10-16dB gain and it has 4.5dB noise figure when operate at 9GHz, with 58111mW power consumption for Vdd ranging from 1.22.0V. The chip size is 0.945 x 1.295mm.

iii

LNA

-

iv

925GHz CMOS LNA i

925GHz Wideband CMOS LNA Design ii

iii

iv

1~ 12 v

1 80 vi

1

8

52

55

57

59

v

1 6 2 17 3 31 4 41 5 43 6 45 7 47 8 48 9 49 10 VDD 49 11 (1.4V) 50 12 (2.0V) 51

vi

1 Arecibo radio telescope 1 2 Arecibo radio telescope 1 3 SKA 2 4 6 5 LFB RFB CFB 8 6 Output loading circuit9 7 The circuits input impedance10 8 First stage circuit11 9 .11 10 12 11 14 12 ..14 13 15 14 S11 .15 15 S22 16 16 S21 16 17 S12 16 18 Smith chart17 19 Noise Figure 17 20 Layout 18 21 Momentum S 19 22 Y Deembedding19 23 Deembedding 20 24 layout 20 25 S 21 26 Layout grounding 22 27 Vd power trace 23 28 23 29 S11 24 30 S22 24 31 S21 25 32 S12 25 33 Smith chart 25 34 Noise Figure 26 35 S11 26

vii

36 S22 26 37 S21 27 38 S12 27 39 Smith chart 27 40 Noise Figure 28 41 28 42 Inter-stage stability analysis 29 43 Inter-stage stability analysis 29 44 Inter-stage stability analysis 30 45 Inter-stage stability analysis 30 46 Inter-stage stability analysis 30 47 layout 31 48 S11 32 49 S22 32 50 S21 33 51 S12 33 52 Smith chart 34 53 Noise Figure 34 54 S11 35 55 S22 35 56 S21 36 57 S12 36 58 Smith chart 37 59 Noise Figure 37 60 F/F38 61 S/S39 62 F/S39 63 S/F40 64 F/F41 65 S/S42 66 F/S42 67 S/F43 68 F/F 44 69 S/S 45 70 F/F 46 71 S/F 46 72 47 73 48

viii

74 52 75 Circuit Layout and Photo53 76 S 53 77 IP1dB 54 78 Noise Figure 54 79 Revision on Drain Bias Isolation 55 80 Revision on Circuit Layout 56

1

ContactGoldeneyeArecibo radio telescope 1 2 305 7 pulsar

ALMA Atacama Large Millimeter Array NSF 5 Square Kilometre ArraySKA 10

1 Arecibo radio telescope 2 Arecibo radio telescope

SKA

2

(The Canberra Time) SKA (Earth-like planets)(pulsars)

ESA

-- Square Kilometer ArraySKA 3 (SKA ) 200

3 SKA

SKA 10 SKA pulsars -- 100

3

SKA 100 MHz 25 GHz 1997 MAC 2.4GHz ISM 2Mbit/s

1999 : 802.11a 802.11b

5GHz 54Mbit/s 2.4GHz 11Mbit/s 2003 802.11g 2.4GHz 54Mbit/s 2004 1 IEEE 802.11 540Mbit/s 802.11b 50 802.11g 10 802.11n 802.11n 2006

2002 Federal

Communications Commission (FCC) 3.1 GHz 10.6 GHz

4

10Mbps 1Gbps 10Gbps

Ka (18GHz)

Ka 17.7G~21.2GHz

3G~4GHz C Ku Ka

Ka VSAT

5

Ka QV

Space Communication Architecture

Working Group (SCAWG) NASA Space Communication and Navigation Architecture Recommendations for 2005-2030 4[1]

SCA 4 1). Earth, 2). Moon, 3).

Mars vicinity and 4). Deep Space UHFSLKKu Ka Ground-based Earth Element Near-Earth Relay Element 13GHz ~ 15GHz Ground-based Earth Element Launch VehiclesEarth Orbital UserLunar Surface Orbital User 22GHz ~ 27GHz 9G-25GHz

6

4

1

1). MOS 3G~10GHzMOS Ka

SKA 100 MHz 25 GHz

EW/ECM 9G~26GHz

Ka 17.7G~21.2GHz

13G ~ 15GHz

22G ~ 27GHz

7

2). SKA IC MOS MOS

3). Ultra Wideband LNA Noise Figure Noise Figure L-C nMOS 0.18um 9G~25GHz

8

1). nMOS RC

nMOS [2] 5 1 50 Sin 2 LFBRFB CFB

5 LFB RFB CFB

5(a) Yin(=1/Zin) Yin = j Cgs + j Cgd { 1 [(j Cgd Gm)/j (Cgd + CFB)]} j (Cgs + Cgd) + [Cgd Gm/(Cgd + CFB)] (1)

Yin LC

9

[3]~[10]

RFB(a) CFB(a)LFB

6 (a) The resistive-loading circuit with R as its output loading. (b) The

capacitive-loading circuit with C as its output loading.

: Zin = (1/jCgs) + [ LFB( Gm + jCgs)/Cgs] (1/jCgs) + (LFB Gm/Cgs) (2) Rds Gm Cgd

LFB :

Zin (1/jCgs) + (LFB Gm/Cgs) [ 1 + Cgd ( 1 + Gm RFB )/Cgs]-1 (3) = Rds/(Rds + RFB + j LFB) (4) LFB

10

7 (a) To find out the circuits input impedance, values of Y and Z , which are indicated by the arrows, need to be derived first. (b) The equivalent circuit from the input impedances point-of-view where R , C , L come from Y ,

while R , C , L are from Z . Zin Y Z Zin = ( Y + 1/Z )-1 (5) Y = jCgd + ( R + 1/ jC + jL )-1 (6) With R = CFB/GmCgd (7) C = GmRdsCgd (8) L = ( LFBCFB/Gm Rds Cgd ) ( 1 + Gm Rds ) (9) Z = 1/jCgs + ( 1/R + jC + 1/jL )-1 (10) With R = GmLFB/Cgs (11) C = Cgs/GmRds (12) L = ( LFBGm Rds CFB )/Cgs (13)

2).

DC 8

11

8 First stage circuit

3). : L-C

M2~M5 nMOS S21 8 :

9

12

10 (1) LNA (2) LNA (3) ADS (4) 3inter-stage stability (5) 5inter-stage stability (6) (7) Cadence DRCLVS (8) LayoutMomentumSADS (9) IC

10

13

: 1). nMOS nr

S22 nMOS nr M1 32 M2=M3=16M4=M5=8

2).

3). Current Density

Current Density M1 23mA M2 M3 13mAM4 M5 8mA M1 3 , 3um 9um 9um M1 70 31mA

M2 M5 2

70 Current Density

4).

1 M1 M2 Current Density L13 15um M2~M5 11

14

11

5). Vd

CHOKE ADS

0~40GHz Mu 1

K 1>0 12

12

15

6). First version circuit: 13

13

7).

a) S11 under -11dB 14

14 S11

16

b) S22 under -11dB 15

15 S22

c) S21Gain 21dB 0.7dB

16

16 S21

d) S12 under -60dB 17

17 S12

17

e) S11 S22 smith chart 18

18 Smith chart

f) NFNoise Figure

2.747~5.679. 19

19 Noise Figure

Tech. BW

(GHz)S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

Simulate Result

0.18 mCMOS 9-25 < -11 < -11 210.7 < -60 2.84-5.4

3

2

18

8). Layout 20

1.36 x 1.36 (mm2)

20 Layout

19

9). Momentum S layout Momentum

layoutSADS ADS 21

21 Momentum S

S 22 23

[11][12]

22 Y Deembedding

20

23 Deembedding

10). layout Momentum S

Layout Momentum S ADS Layout

11). Layout S ADS

( 24)

24 layout

21

25 S21 S11

M1 L3L3 GND M3 C4 Layout

25 S

12). CIC

a). layout Pad size 75mm X 75mm Pad 50mm X 50 mm

b). M3 L3 GND layout

c). 1.36 X 1.36 (mm2)

die size die

22

layout 0.945 X 1.295 (mm2) 33%

d). e). inter-stage stability analysis f).

Grounding 26

26 Layout grounding

g). L13

die size L13 layout layer2 layer3 ground Vd power

23

27

27 Vd power trace

13). 28

28

24

ADS2005 Vg 0.8V Vd 1.4V 2.0V

). : Vg = 0.8V and Vd = 1.4V

a) S11-11dB 29

29 S11


30 S22

c) S21Gain 19.5dB 1 dB

31

25

31 S21

d) S12 under -62dB 32

32 S12

e) S11 S22 smith chartS11 S22

33

33 Smith chart

26

f) NFNoise Figure 3.337~5.843.

34

34 Noise Figure

LNA Vd 1.4V

). : Vg = 0.8V and Vd = 2V a) S11-11dB 35

35 S11


27

36 S22

c) S21Gain 22dB 1 dB 37

37 S21

d) S12 under -60dB

38

38 S12

28

e) S11 S22 smith chart 39

39 Smith chart

f) NFNoise Figure

2.897~5.454. 40

40 Noise Figure

g)

0~40GHz Mu 1

K 1>0

29

41

41

h) Inter-stage stability analysis

MOS, M1 Mu 1 K 1B>0 42

42 Inter-stage stability analysis

MOS, M2 Mu 1 K 1B>0 43


30

MOS, M3 Mu 1 K 1B>0 44


MOS, M4 Mu 1 K 1B>0 45


MOS, M5 Mu 1 K 1B>0 46


31

42 46 Inter-stage stability analysis 9~25GHz S11 -11dB S22 -11dB 19.5 dB LNA NF

Tech.

BW (GHz)

S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Simulate Result

0.18 mCMOS 9-25 < -11 < -12 19.51 < -62 3.33-5.8

4 1.4

Simulate Result

0.18 mCMOS 9-25 < -11 < -11 221 < -60 2.89-5.4

5 2.0

3

14). layout Layout S ADS ( 47)

47 layout

32

[8] Momentum S Layout Vd 1.4V 2.0V : 9G ~ 25GHz : Vg = 0.8V and Vd = 1.4V

1 S11 9G ~ 25GHz S11 under -10dB 48

4 S11

2 S22 49 LNA under -14dB -14.264dB LNA S22 49

49 S22

33

3 S21S21 Gain 20.5 dB 1 dB 50

50 S21

4 S1212 S12 -60dB S12 27.2GHz under -58dB 12 51

51 S12

34

5 52 S11 S22 smith chart MOS S11

52 Smith chart

6 NF: Noise Figure

2.840~5.431 53

53 Noise Figure

Vd = 1.4V

35

: 9G ~ 25GHz : Vg = 0.8V and Vd = 2V

7 S11 Vd 2V 55 9G ~ 25GHz under -10dB

54 S11

8 S22 Vd 2V under -13dB 15.8GHz -13.497dB 55

55 S22

36

9 S21Gain 20.5 dB 1 dB 56

56 S21

10 S12 under -60dB 57

57 S12

S LNA

layout

37

11 S11 S22 smith chart 58S22 smith chart S11 S11 S22

58 Smith chart

12 NF Noise Figure

2.840~5.431. 59

59 Noise Figure

38

13

MOS , MOS Fast/FastSlow/SlowFast/SlowSlow/Fast Resistance Worst case Vd = 1.4V Vd = 2.0V 60~67

MOS

: Vg = 0.8V and Vd = 1.4V

a. Fast/FastResistance=Worst 60

60 F/F

S11 9GHz~25GHz -10dB S22 -15.535 dB S12 60 dB21 19.6 dB

39

b. Slow/SlowResistance=Worst 61

61 S/S

S11 9GHz~25GHz -10dB S22 -13.253 dB S12 60 dB21 12.204 dB c. Fast/SlowResistance=Worst 62

62 F/S

40


d. Slow/FastResistance=Worst 63

63 S/F


41

4 MOS Vdd 1.4V Slow/Slow S21

S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Stable

Fast/Fast < -9.5 < -15 20.61 < -60 3.27-5.6

9 1.4

Slow/Slow < -10 < -1313.1

0.9 < -57

3.62-6.22

1.4

Fast/Slow < -9.8 < -15 19.71 < -59 3.32-5.8

2 1.4

Slow/Fast < -10 < -13 14.61 < -57 3.44-5.9

3 1.4

4

: Vg = 0.8V and Vd = 2V e. Fast/FastResistance=Worst 64

64 F/F


42

f. Slow/SlowResistance=Worst 65

65 S/S


g. Fast/SlowResistance=Worst 66

66 F/S


43

h. Slow/FastResistance=Worst 67

67 S/F


MOS Vdd 2.0V

Slow/Slow S21

S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Stable

Fast/Fast < -10 < -14 23.31 < -61 2.81-5.3

6 2.0

Slow/Slow < -11 < -1215.1

0.8 < -59

3.12-5.81

2.0

Fast/Slow < -10 < -14 22.31 < -61 2.86-5.5

0 2.0

Slow/Fast < -11 < -1317.4

0.8 < -59

2.96-5.54

2.0

5

44

, Fast/FastSlow/Slow Resistance Worst case Vd = 1.4V Vd = 2.0V 68~ 71

: Vg = 0.8V and Vd = 1.4V

i. RFCAP=Fast/FastResistance=Worst 68

68 F/F

S11 9GHz~25GHz -9.65dB S22 -15.213 dB S12 60 dB21 15.4 dB

45

j. RFCAP= Slow/SlowResistance=Worst 69

69 S/S

S11 9GHz~25GHz -10dB S22 -13.725 dB

S12 58 dB21 17.5 dB

6 Vdd 1.4V S21

S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Stable

Fast/Fast < -10 < -15 16.51.1 < -59 3.49-5.8

8 1.4

Slow/Slow < -10 < -13.7 18.11 < -58.7 3.16-5.7

1 1.4

6

46

: Vg = 0.8V and Vd = 2.0V k. RFCAP=Fast/FastResistance=Worst 70

70 F/F

S11 9GHz~25GHz -10dB S22 -14.3 dB

S12 60 dB21 18.5 dB

l. RFCAP= Slow/SlowResistance=Worst 71

71 S/S

47


7 Vdd 2.0V

S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Stable

Fast/Fast < -10.2 < -13.9 19.51 < -60.8 2.98-5.5

3 2.0

Slow/Slow < -10 < -12.9 20.61.1 < -60.5 2.74-5.3

7 2.0

7

70.0 C Vd = 1.4V Vd = 2.0V 72~ 73

: Vg = 0.8V and Vd = 1.4V m. Temperature=70.0 C 72

72

48


: Vg = 0.8V and Vd = 2.0V

n. Temperature=70.0 C 73

73


S11 (dB)

S22 (dB)

S21 (dB)

S12 (dB)

NF (dB)

VDD (V)

Stable

Fast/Fast < -10 < -15.1 14.60.8 < -59 3.96-6.5

7 1.4

Slow/Slow < -11 < -14.2 17.50.8 < -60 3.35-6.1

4 2.0

8

49

14 0.18um

21 9

Tech. BW

(GHz)

S11

(dB)

S22

(dB)

S21

(dB)

NF

(dB)

VDD

(V)

This work 0.18 mCMO

S 9-25

50

VDD NF 5 die size * [1][2][13][14]

S11 [dB]. < -10

S22 [dB]. < -14

S21 [dB]. 17.6 0.7

S12 [dB]. < -58

BW [GHz]. 9 ~ 25

NF [dB @9GHz]. 3.2

NF [dB @26GHz]. 5.7

Power Consumption Vd = 1.4V, 80 mW

11 (1.4V)

S11 [dB]. < -10

S22 [dB]. < -13

S21 [dB]. 22.5 1.0

S12 [dB]. < -60

BW [GHz]. 9 ~ 25

NF [dB @9GHz]. 2.8

51

NF [dB @25GHz]. 5.4

Power Consumption Vd = 2.0V, 130 mW

12 (2.0V)

52

CIC On Wafer S N.F

Vg 0.8V Vd 1.4V~2V .

S11S22S21S12

Noise Figure Analyzer Noise Figure

74 ( pitch 100um 3 Pin RF pitch 100um 3 Pin DC )

74

53

Circuit Layout and Photo

75 Circuit Layout and Photo

S Parameter Measured Results

76 S

54

IP1dB Measured Results

77 IP1dB

Noise Figure Measured Results

78 Noise Figure

S11 9GHz~20.5GHz -10dB20.5GHz~ 25GHz -7dB S22 -10dB Vd=2.0V ,S21 2.0V 10 dB

55

S11 TSMC 0.18um RF-CMOS technology , Ka LNA S21 , tsmc model 20GHz MOS Pad

Noise Figure Ground

79 Revision on Drain Bias Isolation

56

80 Revision on Circuit Layout

Add more GND Pads

Add more by-pass capacitors on

drain bias

57

[1] NASA Space Communication and Navigation Architecture Recommendations for 2005-2030 Space Communication Architecture Working Group (SCAWG)

[2] Wide-Band Matched LNA Design Using Transistor s Intrinsic Gate-Drain Capacitor Robert Hu

[3] A GaAs monolithic 6 GHz low-noise amplifier for satellite receivers R. C. Mott, IEEE Trans. Microw. Theory Tech., vol. 37, no. 3, pp. 565 570, Mar. 1989. [4] A CMOS Low-Noise Amplifier for UltraWidebandWireless Applications M.F. CHOU, W.S. WUEN, C.C. WU, K.A. WEN, and C.Y. CHANG, Nonmembers IEICE TRANS. FUNDAMENTALS, VOL.E88 A, NO.11 NOVEMBER 2005 [5] A gain-controllable wide-band low-noise amplifier in low-cost 0.8-_m Si BiCMOS technology F. Seguin, B. Godara, F. Alicalapa, and A. Fabre, IEEE Trans. Microw. Theory Tech., vol. 52, no. 1, pp. 154 160, Jan. 2004. [6] A low supply voltage SiGe LNA for ultra-wideband front ends D. Barras, F. Ellinger, H. Jackel, and W. Hirt IEEE Microw. Wireless Compon. Lett., vol. 14, no. 10, pp. 469 471, Oct. 2004. [7] Ultra-low-noise 1.2 1.7-GHz cooled GaAsFET amplifiers S. Weinreb, D. L. Fenstermacher, and R. W. Harris, IEEE Trans. Microw. Theory Tech., vol. MTT-82, no. 6, pp. 849 853, Jun. 1982. [8] Cryogenic wide-band ultra-lownoise IF amplifiers operating at ultra-low DC power

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N.Wadefalk, A. Melberg, I. Angelov, M. E. Barsky, S. Bui, E. Choumas, R. W. Grundbacher, E. L. Kollberg, R. Lai, N. Rorsman, P. Starski, J. Stenarson, D. C. Streit, and H. Zirath IEEE Trans. Microw. Theory Tech., vol. 51, no. 6, pp. 1705 1711, Jun. 2003. [9] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design Englewood Cliffs, NJ: Prentice-Hall, 1984. [10] R. Goyal, High-Frequency Analog Integrated Circuit Design New York: Wiley, 1995.

[11] Modeling toolkits 0_DEEMB.WPS | 18.03.02, De-embedding Agilent Technologies, dept.: EEsof, D-82024 Taufkirchen (Munich), Germany [12] IC Application & Design magazine 2005 May

[13] A 3 10-GHz low-noise amplifier with LC-ladder matching network A. Ismail and A.A. Abidi, IEEE J. Solid-State Circuits, vol.39, no.12, pp.2269 2277, 2004. [14] 0.18 um 3 6 GHz CMOS broad-band LNA for UWB radio C. P. Chang and H. R. Chuang, Electron. Lett., vol. 41, pp. 696 697, Jun. 2005.

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Takau, 1976

9-26GHz Wideband CMOS LNA Design thesis-9367519 · 9−25GHz寬頻COMS LNA 9−25GHz Wideband CMOS...

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