8255:ppi & 8259:pic
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Transcript of 8255:ppi & 8259:pic
8255A : PPI 8259A : PIC
:: Prepared By ::Adarsh Patel
8255A : PPI 8259A : PIC 2
Content - Introduction to 8255A
Block diagram Different I/O modes
- Introduction to 8259A Block diagram Different interrupt modes
:: Reference ::Microprocessor Architecture, Programming, and Applications With the 8085 - By Ramesh Gaonkar
http://www.slideshare.net/anuja1310/interfacing-8255
8255A : PPI 8259A : PIC 3
Introduction of 8055A
8255A is widely used, programmable, parallel I/O device.
It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset).
PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation.
Functions of Ports are defined by Control word.
Controls
Group A
Port A Port C Upper (C7 to C4)
Group B
Port C lower (C3 to C0) Port B
8255A Programmable Peripheral Interface
8255A : PPI 8259A : PIC 4
Cont .
8255A Modes
MODES
BSR BIT SET-RESET I/O MODE
MODE 0
Basic I/O
Mode
MODE 1 :
Strobed I/O Mode
MODE 2 :
Strobed
Bi-directional I/O
5
Cont .Block
diagram8255A
8255A : PPI 8259A : PIC
6
Cont .
8255A Control word format for I/O mode
8255A : PPI 8259A : PIC
• Byte A : I / O mode• Byte B : BSR (Bit Set / reset)
Modes
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Modes
This functional configuration provides simple input and output operations for each of the three ports.
No “handshaking” is required, data is simply written to or read from a specified port.
MODE 0
MODE 1
Ports A and B are programmed as input or output ports, Port C is used for handshaking.
Handshake Signals are Exchanged between the MPU and peripherals Prior to data transfer.
Input and Output Data are Latched.
8255A : PPI 8259A : PIC 8
Cont .
8255A : PPI 8259A : PIC 9
Cont .
8255A : PPI 8259A : PIC 10
Cont .
MODE 2
This mode is used in applications such as data transfer between two computers or floppy disk controller interface.
Port A is programmed to be bi-directional Port C is for handshaking Port B can be either input or output in mode 0 or mode 1
8255A : PPI 8259A : PIC 11
Introduction of 8059A
8259A PIC adds eight vectored priority encoded interrupts to the microprocessor.
Compatible With 8086, 8088 Microprocessors Eight-Level Priority Controller Expandable to 64 Levels Priority levels Various types of Interrupt Modes Individual Request Mask Capability The ability to accept level-triggered or edge-triggered
inputs. Individual Request Mask Capability
8259A Programmable Interrupt Controller (PIC)
128255A : PPI 8259A : PIC
Block diagram : 8259A
Block diagram
13
Cont .
8255A : PPI 8259A : PIC
PIN diagram : 8259A
8255A : PPI 8259A : PIC 14
READ / WRITE LOGIC
The function of this block is to accept output commands from the CPU.
It contains the Initialization Command Word ( lCW ) registers and Operation Word ( OCW ) registers which store the various control formats for device Command operation.
This function block also allows the status of the 8259A to be transferred onto the Data Bus.
Cont .
CONTROL LOGIC INT (Interrupt) Output Connected to Interrupt pin of Microprocessor. When interrupt occurs this pin goes high. INTA ( Interrupt Acknowledge) Input from Microprocessor
8255A : PPI 8259A : PIC 15
CASCADE BUFFER
This block is used to expand the number of interrupt level by cascading two or more 8259As.
Also generates buffer enable signals. Generates control signals for cascade operation.
Cont .
INTERRUPT REGISTER AND PRIORITY RESOLVER
IRR stores the current status of the interrupt request inputs.
ISR stores all the levels that are being Serviced. IMR stores masking bits of the Interrupt lines to be
masked. The PR Examines these three register sand Determines
whether INT should be sent to the MPU.
8255A : PPI 8259A : PIC 16
Priority mode
FULLY NESTED MODE This is a general purpose mode where all IR’s are
arranged in highest to lowest. IR0 highest and IR7 lowest. In addition, any IR Can be Assigned the Highest priority
in this Mode.
AUTOMATIC ROTATION MODE
In this mode a device after being serviced receives the lowest priority.
SPECIFIC ROTATION MODE
In this user can select any IR for lowest priority thus fixing all priorities.
8255A : PPI 8259A : PIC 17
Programming
ICW1 Programming is for defining the interrupt levels for each IRQ
ICW2 programming is for cascade or normal mode ICW3 programming for automatic or manual end of
interrupt ICW4 for programming nested or specific rotation or
automatic mode for priority resolver
8259A Programming
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Summary
Basics of 8255A PPI Different I/O mode of 8255A Basics of 8259A PIC Different interrupt mode of
8259A Programming Mode of 8259A