6. FND, LED DOT-MATRIX 제어실습 -...
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6. FND, LED DOT-MATRIX 제어 실습
Transcript of 6. FND, LED DOT-MATRIX 제어실습 -...
6. FND, LED DOT-MATRIX 제어 실습
FND의 데이터 출력
7-segment의구성◦ 숫자를 표시하기 위해서 7개의 LED가 사용되므로 7-Segment라는 이름으로 불림
◦ SYS-Lab 5000의 7-Segment
FND 숫자 표시(VHDL) - 1library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fnd01 isPort ( SEG_A : out STD_LOGIC;
SEG_B : out STD_LOGIC;SEG_C : out STD_LOGIC;SEG_D : out STD_LOGIC;SEG_E : out STD_LOGIC;SEG_F : out STD_LOGIC;SEG_G : out STD_LOGIC;SEG_DP : out STD_LOGIC;DIGIT : out STD_LOGIC_VECTOR (5 downto 0));
end fnd01;
architecture Behavioral of fnd01 issignal seg_int : std_logic_vector (7 downto 0);signal seg_in : std_logic_vector (3 downto 0);begin
FND 숫자 표시(VHDL) - 2seg_in <= "0011";DIGIT <= "000001";process(seg_in)begincase seg_in iswhen "0000" => seg_int <= "00111111"; when "0001" => seg_int <= "00000110";when "0010" => seg_int <= "01011011";when "0011" => seg_int <= "01001111";when "0100" => seg_int <= "01100110";when "0101" => seg_int <= "01101101";when "0110" => seg_int <= "01111101";when "0111" => seg_int <= "00100111";when "1000" => seg_int <= "01111111";when "1001" => seg_int <= "01101111";when others => seg_int <= "00000000";end case;
end process;SEG_A <= seg_int(0); SEG_B <= seg_int(1); SEG_C <= seg_int(2);SEG_D <= seg_int(3); SEG_E <= seg_int(4); SEG_F <= seg_int(5);SEG_G <= seg_int(6); SEG_DP <= seg_int(7);
end Behavioral;
FND 숫자 표시(Verilog) - 1module fnd01(SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP, DIGIT);output SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP;output [5:0] DIGIT;
reg [7:0] seg_int;wire [3:0] seg_in;
assign seg_in = 4'b0011;assign DIGIT = 6'b000001;
always @(seg_in)case (seg_in)0 : seg_int = 8'b00111111;1 : seg_int = 8'b00000110;2 : seg_int = 8'b01011011;3 : seg_int = 8'b01001111;4 : seg_int = 8'b01100110;5 : seg_int = 8'b01101101;6 : seg_int = 8'b01111101;7 : seg_int = 8'b00100111;8 : seg_int = 8'b01111111;
FND 숫자 표시(Verilog) - 2
9 : seg_int = 8'b01101111;default : seg_int = 8'b00000000;
endcase
assign SEG_A = seg_int[0]; assign SEG_B = seg_int[1];assign SEG_C = seg_int[2]; assign SEG_D = seg_int[3];assign SEG_E = seg_int[4]; assign SEG_F = seg_int[5];assign SEG_G = seg_int[6]; assign SEG_DP = seg_int[7];
endmodule
FND 숫자 표시 (UCF File)
Spartan 3의 UCF 파일의내용 Virtex 4의 UCF 파일의내용
FND에 특정 데이터 출력
7-segment에 출력되는 데이터 공용 개별 7-segment를 on/off 할 수 있는 구조◦ 동시에 6개의 7-segment를 모두 on 6개 모두 같은 데이터 값으로 출력
◦ 7-segment의 각 자리에 6, 5, 4, 3, 2, 1의 숫자를 출력할 경우 7-segment output data에 6을 표현하기 위한 데이터를 지정 DIGIT6은 on하고 나머지 DIGIT5~0은 off 5에 대한 데이터를 7-segment output data에 지정 DIGIT5만 on이 되고 나머지 DIGIT6,4~0은 off
FND에 1, 2, 3, 4, 5, 6 출력
잔상 효과에 의한 착시 현상 이용◦ 1/60 이하로 빠르게 변하도록 구성
◦ SYS-Lab 5000의 22.118400MHz clock을 64분주
◦ 345.6khz의 클럭으로 각 자리의 숫자 선택
◦ 각 자리에는 6, 5, 4, 3, 2, 1의 숫자 표시
FND에 1, 2, 3, 4, 5, 6 출력(VHDL) - 1
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fnd02 isPort ( clock : in STD_LOGIC;
SEG_A, SEG_B, SEG_C, SEG_D : out STD_LOGIC;SEG_E, SEG_F, SEG_G, SEG_DP : out STD_LOGIC;DIGIT : out STD_LOGIC_VECTOR (5 downto 0));
end fnd02;
architecture Behavioral of fnd02 issignal seg_int : std_logic_vector (7 downto 0);signal count : std_logic_vector (9 downto 0);signal seg_in : std_logic_vector (3 downto 0);
beginprocess(clock)begin
FND에 1, 2, 3, 4, 5, 6 출력(VHDL) - 2
if clock'event and clock='1' thencount <= count + '1';
end if;end process;process(clock, count(9 downto 7))begin -- 7-segment의 출력될 자릿수 선택
if clock'event and clock='1' thencase count(9 downto 7) is
when "000" => seg_in <= "0001"; DIGIT <= "000001";when "001" => seg_in <= "0010"; DIGIT <= "000010";when "010" => seg_in <= "0011"; DIGIT <= "000100";when "011" => seg_in <= "0100"; DIGIT <= "001000";when "100" => seg_in <= "0101"; DIGIT <= "010000";when "101" => seg_in <= "0110"; DIGIT <= "100000";when others => seg_in <= "0000"; DIGIT <= "000000";
end case;end if;
end process; process(seg_in)begin
FND에 1, 2, 3, 4, 5, 6 출력(VHDL) - 3case seg_in iswhen "0000" => seg_int <= "00111111";when "0001" => seg_int <= "00000110";when "0010" => seg_int <= "01011011";when "0011" => seg_int <= "01001111";when "0100" => seg_int <= "01100110";when "0101" => seg_int <= "01101101";when "0110" => seg_int <= "01111101";when "0111" => seg_int <= "00100111";when "1000" => seg_int <= "01111111";when "1001" => seg_int <= "01101111";when others => seg_int <= "00000000";
end case;end process;
SEG_A <= seg_int(0); SEG_B <= seg_int(1);SEG_C <= seg_int(2); SEG_D <= seg_int(3);SEG_E <= seg_int(4); SEG_F <= seg_int(5);SEG_G <= seg_int(6); SEG_DP <= seg_int(7);
end Behavioral;
FND에 1, 2, 3, 4, 5, 6 출력(Verilog) - 1module fnd02(clock, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP,
DIGIT);input clock;output SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F;output SEG_G, SEG_DP;output reg [5:0] DIGIT;reg [7:0] seg_int;reg [9:0] count;reg [3:0] seg_in;always @(posedge clock)
count <= count + 1;always @(posedge clock) // 7-segment의 출력될 자릿수 선택
case (count[9:7])0 : begin seg_in = 4'b0001; DIGIT = 6'b000001; end1 : begin seg_in = 4'b0010; DIGIT = 6'b000010; end2 : begin seg_in = 4'b0011; DIGIT = 6'b000100; end3 : begin seg_in = 4'b0100; DIGIT = 6'b001000; end4 : begin seg_in = 4'b0101; DIGIT = 6'b010000; end5 : begin seg_in = 4'b0110; DIGIT = 6'b100000; enddefault : begin seg_in = 4'b0000; DIGIT = 6'b000000; end
endcase
FND에 1, 2, 3, 4, 5, 6 출력(Verilog) - 2
always @(seg_in)case (seg_in)
0 : seg_int = 8'b00111111;1 : seg_int = 8'b00000110;2 : seg_int = 8'b01011011;3 : seg_int = 8'b01001111;4 : seg_int = 8'b01100110;5 : seg_int = 8'b01101101;6 : seg_int = 8'b01111101;7 : seg_int = 8'b00100111;8 : seg_int = 8'b01111111;9 : seg_int = 8'b01101111;default : seg_int = 8'b00000000;
endcaseassign SEG_A = seg_int[0]; assign SEG_B = seg_int[1];assign SEG_C = seg_int[2]; assign SEG_D = seg_int[3];assign SEG_E = seg_int[4]; assign SEG_F = seg_int[5];assign SEG_G = seg_int[6]; assign SEG_DP = seg_int[7];
endmodule
FND 동작 예
SYS-Lab 5000의 7-segment에 숫자 출력
FND에 카운트 값 출력
카운터를 동작◦ SYS-Lab 5000의 clock 신호 사용
◦ 카운터의 결과 값을 7-segment에 숫자 출력
◦ 7-segment에는 16진 수의 표기
◦ a, b, c, d, e, f의 문자 추가
동작 예
FND 출력 데이터
a, b, c, d, e, f 출력 되도록 수정
a 0 1 0 1 1 1 1 1 0x5F
b 0 1 1 1 1 1 0 0 0x7C
c 0 1 0 1 1 0 0 0 0x58
d 0 1 0 1 1 1 1 0 0x5E
E 0 1 1 1 1 0 0 1 0x79
F 0 1 1 1 0 0 0 1 0x71
숫자 DP G F E D C B A HEX
FND에 카운터 값 출력(VHDL) - 1
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fnd03 isPort ( clock : in STD_LOGIC;
SEG_A, SEG_B, SEG_C, SEG_D : out STD_LOGIC;SEG_E, SEG_F, SEG_G, SEG_DP : out STD_LOGIC;DIGIT : out STD_LOGIC_VECTOR (5 downto 0));
end fnd03;
architecture Behavioral of fnd03 issignal seg_int : std_logic_vector (7 downto 0);signal count : std_logic_vector (9 downto 0);signal seg_in : std_logic_vector (3 downto 0);signal cnt : std_logic_vector (33 downto 0);
beginprocess(clock)
FND에 카운터 값 출력(VHDL) - 2begin
if clock'event and clock='1' thencount <= count + '1';
end if;end process;process(clock, count(9 downto 7))begin
if clock'event and clock='1' thencase count(9 downto 7) is
when "000" => seg_in <= cnt(13 downto 10); DIGIT <= "000001";when "001" => seg_in <= cnt(17 downto 14); DIGIT <= "000010";when "010" => seg_in <= cnt(21 downto 18); DIGIT <= "000100";when "011" => seg_in <= cnt(25 downto 22); DIGIT <= "001000";when "100" => seg_in <= cnt(29 downto 26); DIGIT <= "010000";when "101" => seg_in <= cnt(33 downto 30); DIGIT <= "100000";when others => seg_in <= "0000"; DIGIT <= "000000";
end case;end if;
end process; process(count(7))begin
FND에 카운터 값 출력(VHDL) - 3if count(7)'event and count(7)='1' then
cnt <= cnt + '1';end if;
end process;process(seg_in)begin
case seg_in iswhen "0000" => seg_int <= "00111111";when "0001" => seg_int <= "00000110";when "0010" => seg_int <= "01011011";when "0011" => seg_int <= "01001111";when "0100" => seg_int <= "01100110";when "0101" => seg_int <= "01101101";when "0110" => seg_int <= "01111101";when "0111" => seg_int <= "00100111";when "1000" => seg_int <= "01111111";when "1001" => seg_int <= "01101111";when "1010" => seg_int <= "01011111";when "1011" => seg_int <= "01111100";when "1100" => seg_int <= "01011000";
FND에 카운터 값 출력(VHDL) - 4
when "1101" => seg_int <= "01011110";when "1110" => seg_int <= "01111001";when "1111" => seg_int <= "01110001";
when others => seg_int <= "00000000";end case;
end process;SEG_A <= seg_int(0);SEG_B <= seg_int(1);SEG_C <= seg_int(2);SEG_D <= seg_int(3);SEG_E <= seg_int(4);SEG_F <= seg_int(5);SEG_G <= seg_int(6);SEG_DP <= seg_int(7);
end Behavioral;
FND에 카운터 값 출력(Verilog) - 1module fnd03(clock, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP, DIGIT);
input clock;output SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP;output reg [5:0] DIGIT;
reg [7:0] seg_int;reg [9:0] count;reg [33:0] cnt;reg [3:0] seg_in;always @(posedge clock)
count <= count + 1;always @(posedge clock)
case (count[9:7])0 : begin seg_in = cnt[13:10]; DIGIT = 6'b000001; end1 : begin seg_in = cnt[17:14]; DIGIT = 6'b000010; end2 : begin seg_in = cnt[21:18]; DIGIT = 6'b000100; end3 : begin seg_in = cnt[25:22]; DIGIT = 6'b001000; end4 : begin seg_in = cnt[29:26]; DIGIT = 6'b010000; end5 : begin seg_in = cnt[33:30]; DIGIT = 6'b100000; enddefault : begin seg_in = 4'b0000; DIGIT = 6'b000000; end
endcase
FND에 카운터 값 출력(Verilog) - 2always @(posedge count[7])
cnt <= cnt + 1;always @(seg_in)
case (seg_in)0 : seg_int = 8'b00111111;1 : seg_int = 8'b00000110;2 : seg_int = 8'b01011011;3 : seg_int = 8'b01001111;4 : seg_int = 8'b01100110;5 : seg_int = 8'b01101101;6 : seg_int = 8'b01111101;7 : seg_int = 8'b00100111;8 : seg_int = 8'b01111111;9 : seg_int = 8'b01101111;10: seg_int = 8'b01011111;11: seg_int = 8'b01111100;12: seg_int = 8'b01011000;13: seg_int = 8'b01011110;14: seg_int = 8'b01111001;15: seg_int = 8'b01110001;default : seg_int = 8'b00000000;
endcase
FND에 카운터 값 출력(Verilog) - 3
assign SEG_A = seg_int[0];assign SEG_B = seg_int[1];assign SEG_C = seg_int[2];assign SEG_D = seg_int[3];assign SEG_E = seg_int[4];assign SEG_F = seg_int[5];assign SEG_G = seg_int[6];assign SEG_DP = seg_int[7];
endmodule
FND 시계 구현
시:분:초의 값 출력◦ 7-segment의 각각 2자리의 숫자를 사용
◦ 7-segment에 숫자로 시간 값을 표현
◦ FND를 사용한 시계 구성블록
FND 시계 동작
SYS-Lab 5000의 clock을 분주◦ 1초에 해당하는 sec_clk_l 신호
◦ 초에 해당하는 숫자의 1의 자리 표시
◦ 초에 해당하는 숫자의 10의 자리 표현 sec_clk_h를 만듦
◦ 순차적으로 분을 표시하는 min_clk_l◦ 이 신호를 받는 블록에서 min_clk_h 생성
◦ 마찬가지로 hour_clk_l, hour_clk_h를 생성 이들 신호에 따라 각각의 시:분:초의 1의 자리와 10의 자리에 해당하는 수를 계수할 수 있도록 구성하고 이 값을 7-segment를 통하여 출력
FND 시계 (VHDL) - 1library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fnd04 is
Port ( clock : in STD_LOGIC;SEG_A, SEG_B, SEG_C, SEG_D : out STD_LOGIC;SEG_E, SEG_F, SEG_G, SEG_DP : out STD_LOGIC;DIGIT : out STD_LOGIC_VECTOR (5 downto 0));
end fnd04;architecture Behavioral of fnd02 is
signal seg_int : std_logic_vector (7 downto 0);signal count : std_logic_vector (14 downto 0);signal seg_in : std_logic_vector (3 downto 0);signal cnt : std_logic_vector (9 downto 0);signal sec_clk_l,sec_clk_h,min_clk_l,min_clk_h,hour_clk_l,hour_clk_h :
std_logic;
FND 시계 (VHDL) - 2signal sec_l,min_l,hour_l : std_logic_vector (3 downto 0);signal sec_h,min_h : std_logic_vector (2 downto 0);signal hour_h : std_logic_vector(1 downto 0);
beginprocess(clock)begin
if clock'event and clock='1' thencount <= count + '1';
end if;end process;process(clock, count(9 downto 7))begin
if clock'event and clock='1' thencase count(9 downto 7) is
when "000" => seg_in <= sec_l; DIGIT <= "000001";when "001" => seg_in <= '0'&sec_h; DIGIT <= "000010";when "010" => seg_in <= min_l; DIGIT <= "000100";when "011" => seg_in <= '0'&min_h; DIGIT <= "001000";
FND 시계 (VHDL) - 3when "100" => seg_in <= hour_l; DIGIT <= "010000";when "101" => seg_in <= "00"&hour_h; DIGIT <= "100000";when others => seg_in <= "0000"; DIGIT <= "000000";
end case;end if;
end process;process(count(14),cnt,sec_clk_l)begin
if count(14)'event and count(14)='1' thenif cnt="1010100010" then
cnt <= (others=>'0');sec_clk_l <= '1';
elsif cnt="0101010001" thencnt <= cnt + '1';sec_clk_l <= '0';
elsecnt <= cnt + '1';sec_clk_l <= sec_clk_l;
end if;end if;
end process;
FND 시계 (VHDL) - 4process(sec_clk_l,sec_l,sec_clk_h)begin
if sec_clk_l'event and sec_clk_l='1' thenif sec_l="1001" then
sec_l <= "0000";sec_clk_h <= '1';
elsif sec_l="0100" thensec_l <= sec_l + '1';sec_clk_h <= '0';
elsesec_l <= sec_l + '1';sec_clk_h <= sec_clk_h;
end if;end if;
end process;
process(min_clk_l,sec_h,sec_clk_h)begin
if sec_clk_h'event and sec_clk_h='1' thenif sec_h="101" then
FND 시계 (VHDL) - 5sec_h <= "000";min_clk_l <= '1';
elsif sec_h="100" thensec_h <= sec_h + '1';min_clk_l <= '0';
elsesec_h <= sec_h + '1';min_clk_l <= min_clk_l;
end if;end if;
end process;
process(min_clk_l,min_l,min_clk_h)begin
if min_clk_l'event and min_clk_l='1' thenif min_l="1001" then
min_l <= "0000";min_clk_h <= '1';
FND 시계 (VHDL) - 6elsif min_l="0100" then
min_l <= min_l + '1';min_clk_h <= '0';
elsemin_l <= min_l + '1';min_clk_h <= min_clk_h;
end if;end if;
end process;process(hour_clk_l,min_h,min_clk_h)begin
if min_clk_h'event and min_clk_h='1' thenif min_h="101" then
min_h <= "000";hour_clk_l <= '1';
elsif min_h="100" thenmin_h <= min_h + '1';hour_clk_l <= '0';
FND 시계 (VHDL) - 7else
min_h <= min_h + '1';hour_clk_l <= hour_clk_l;
end if;end if;
end process;
process(hour_clk_l,hour_l,hour_clk_h,hour_h)begin
if hour_clk_l'event and hour_clk_l='1' thenif hour_h="10" then
if hour_l="0011" thenhour_l <= "0000";hour_clk_h <= '1';
elsif hour_l="0001" thenhour_l <= hour_l + '1';hour_clk_h <= '0';
elsehour_l <= hour_l + '1';
FND 시계 (VHDL) - 8end if;
elseif hour_l="1001" then
hour_l <= "0000";hour_clk_h <= '1';
elsif hour_l="0100" thenhour_l <= hour_l + '1';hour_clk_h <= '0';
elsehour_l <= hour_l + '1';hour_clk_h <= hour_clk_h;
end if;end if;
end if;end process;
process(hour_clk_h,hour_h)begin
FND 시계 (VHDL) - 9if hour_clk_h'event and hour_clk_h='1' then
if hour_h="10" thenhour_h <= "00";
elsehour_h <= hour_h + '1';
end if;end if;
end process;process(seg_in)begin
case seg_in iswhen "0000" => seg_int <= "00111111";when "0001" => seg_int <= "00000110";when "0010" => seg_int <= "01011011";when "0011" => seg_int <= "01001111";when "0100" => seg_int <= "01100110";when "0101" => seg_int <= "01101101";when "0110" => seg_int <= "01111101";when "0111" => seg_int <= "00100111";
FND 시계 (VHDL) - 10when "1000" => seg_int <= "01111111";when "1001" => seg_int <= "01101111";when "1010" => seg_int <= "01011111";when "1011" => seg_int <= "01111100";when "1100" => seg_int <= "01011000";when "1101" => seg_int <= "01011110";when "1110" => seg_int <= "01111001";when "1111" => seg_int <= "01110001";when others => seg_int <= "00000000";
end case;end process;
SEG_A <= seg_int(0);SEG_B <= seg_int(1);SEG_C <= seg_int(2);SEG_D <= seg_int(3);SEG_E <= seg_int(4);SEG_F <= seg_int(5);SEG_G <= seg_int(6);SEG_DP <= seg_int(7);
end Behavioral;
FND 시계 (Verilog) - 1module fnd02(clock, SEG_A, SEG_B, SEG_C, SEG_D, SEG_E, SEG_F, SEG_G, SEG_DP, DIGIT);
input clock;output SEG_A, SEG_B, SEG_C, SEG_D;output SEG_E, SEG_F, SEG_G, SEG_DP;output reg [5:0] DIGIT;
reg [7:0] seg_int;reg [14:0] count;reg [9:0] cnt;reg [3:0] seg_in;reg sec_clk_l,sec_clk_h;reg min_clk_l,min_clk_h;reg hour_clk_l,hour_clk_h;reg [3:0] sec_l,min_l,hour_l;reg [2:0] sec_h,min_h;reg [1:0] hour_h;
always @(posedge clock)count <= count + 1;
FND 시계 (Verilog) - 2always @(posedge clock)
case (count[9:7])0 : begin seg_in = sec_l; DIGIT = 6'b000001; end1 : begin seg_in = {1'b0,sec_h}; DIGIT = 6'b000010; end2 : begin seg_in = min_l; DIGIT = 6'b000100; end3 : begin seg_in = {1'b0,min_h}; DIGIT = 6'b001000; end4 : begin seg_in = hour_l; DIGIT = 6'b010000; end5 : begin seg_in = {2'b00,hour_h}; DIGIT = 6'b100000; enddefault : begin seg_in = 4'b0000; DIGIT = 6'b000000; end
endcasealways @(posedge count[14])
if (cnt=='d674)begin
cnt <= 10'h00;sec_clk_l <= 1;
endelse if (cnt=='d337)
begincnt <= cnt + 1;sec_clk_l <= 0;
FND 시계 (Verilog) - 3end
elsebegin
cnt <= cnt + 1;sec_clk_l <= sec_clk_l;
endalways @(posedge sec_clk_l)
if (sec_l==4'b1001)begin
sec_l <= 4'b0000;sec_clk_h <= 1;
endelse if (sec_l==4'b0100)
beginsec_l <= sec_l + 1;sec_clk_h <= 0;
endelse
begin
FND 시계 (Verilog) - 4sec_l <= sec_l + 1;sec_clk_h <= sec_clk_h;
endalways @(posedge sec_clk_h)
if (sec_h==3'b101)begin
sec_h <= 3'b000;min_clk_l <= 1;
endelse if (sec_h==3'b100)
beginsec_h <= sec_h + 1;min_clk_l <= 0;
endelse
beginsec_h <= sec_h + 1;min_clk_l <= min_clk_l;
end
FND 시계 (Verilog) - 5always @(posedge min_clk_l)
if (min_l==4'b1001)begin
min_l <= 4'b0000;min_clk_h <= 1;
endelse if (min_l==4'b0100)
beginmin_l <= min_l + 1;min_clk_h <= 0;
endelse
beginmin_l <= min_l + 1;min_clk_h <= min_clk_h;
endalways @(posedge min_clk_h)
if (min_h==3'b101)begin
min_h <= 3'b000;hour_clk_l <= 1;
FND 시계 (Verilog) - 6end
else if (min_h==3'b100)begin
min_h <= min_h + 1;hour_clk_l <= 0;
endelse
beginmin_h <= min_h + 1;hour_clk_l <= hour_clk_l;
endalways @(posedge hour_clk_l)
if (hour_h==2'b10)begin
if (hour_l==4'b0011)begin
hour_l <= 4'b0000;hour_clk_h <= 1;
end
FND 시계 (Verilog) - 7else if (hour_l==4'b0001)
beginhour_l <= hour_l + 1;hour_clk_h <= 0;
endelse
hour_l <= hour_l + 1;end
elsebegin
if (hour_l==4'b1001)begin
hour_l <= 4'b0000;hour_clk_h <= 1;
endelse if (hour_l==4'b0100)
beginhour_l <= hour_l + 1;hour_clk_h <= 0;
end
FND 시계 (Verilog) - 8elsebegin
hour_l <= hour_l + 1;hour_clk_h <= hour_clk_h;
endend
always @(posedge hour_clk_h)if (hour_h==2'b10)
hour_h <= 2'b00;else
hour_h <= hour_h + 1;always @(seg_in)
case (seg_in)0 : seg_int = 8'b00111111;1 : seg_int = 8'b00000110;2 : seg_int = 8'b01011011;3 : seg_int = 8'b01001111;4 : seg_int = 8'b01100110;5 : seg_int = 8'b01101101;6 : seg_int = 8'b01111101;
FND 시계 (Verilog) - 97 : seg_int = 8'b00100111;8 : seg_int = 8'b01111111;9 : seg_int = 8'b01101111;10: seg_int = 8'b01011111;11: seg_int = 8'b01111100;12: seg_int = 8'b01011000;13: seg_int = 8'b01011110;14: seg_int = 8'b01111001;15: seg_int = 8'b01110001;default : seg_int = 8'b00000000;
endcaseassign SEG_A = seg_int[0];assign SEG_B = seg_int[1];assign SEG_C = seg_int[2];assign SEG_D = seg_int[3];assign SEG_E = seg_int[4];assign SEG_F = seg_int[5];assign SEG_G = seg_int[6];assign SEG_DP = seg_int[7];
endmodule
LDM(LED Dot Matrix) 구성 및 동작
LDM◦ LED Dot Matrix
◦ LED를 5×7, 8×8, 16×16 등의 MATRIX 로 배열한 디스플레이 장치
◦ 다양한 문자, 기호를 표시할 수 있는 디스플레이 장치
◦ 8행 × 8열로 구성된 LDM의 구성
알파벳 'A' 출력 0 라인만 ON 나머지 1~7 라인 OFF 첫 번째 줄 “00011000” 출력
1 라인만 ON 나머지 라인 모두 OFF 두 번째 줄 “00100100” 출력
LDM의구성7 6 5 4 3 2 1 0
0
1
2
3
4
5
6
7
LDM(LED Dot Matrix) 출력
SYS-Lab 5000에 출력될 데이터15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0x1818
1 0x2438
2 0x4208
3 0x4208
4 0x7E08
5 0x4208
6 0x423E
7 0x0000
8 0x7C1C
9 0x4222
10 0x4222
11 0x7C04
12 0x4208
13 0x4210
14 0x7C3E
15 0x0000
LDM(LED Dot Matrix) 출력 설계
ISE의 Project Navigator를 실행◦ File New Project 선택
◦ Source Wizard에서VHDL 또는Verilog에 대해clock, dot_data(15:0), scan_data(0:15) 지정
LDM(LED Dot Matrix) 출력(VHDL) - 1
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ldm01 is
Port ( clock : in STD_LOGIC;dot_data : out STD_LOGIC_VECTOR (15 downto 0);scan_data : out STD_LOGIC_VECTOR (0 to 15));
end ldm01;
architecture Behavioral of ldm01 issignal cnt : std_logic_vector(18 downto 0);
beginprocess(clock,cnt)begin
if clock'event and clock='1' thencnt <= cnt + '1';
end if;end process;
LDM(LED Dot Matrix) 출력(VHDL) - 2
process(clock,cnt)
begin
if clock'event and clock='1' then
case cnt(18 downto 15) is
when X"0" => dot_data <= x"1818"; scan_data <= x"0001";
when X"1" => dot_data <= x"2438"; scan_data <= x"0002";
when X"2" => dot_data <= x"4208"; scan_data <= x"0004";
when X"3" => dot_data <= x"4208"; scan_data <= x"0008";
when X"4" => dot_data <= x"7E08"; scan_data <= x"0010";
when X"5" => dot_data <= x"4208"; scan_data <= x"0020";
when X"6" => dot_data <= x"423E"; scan_data <= x"0040";
when X"7" => dot_data <= x"0000"; scan_data <= x"0080";
when X"8" => dot_data <= x"7C1C"; scan_data <= x"0100";
when X"9" => dot_data <= x"4222"; scan_data <= x"0200";
LDM(LED Dot Matrix) 출력(VHDL) - 3
when X"A" => dot_data <= x"4222"; scan_data <= x"0400";
when X"B" => dot_data <= x"7C04"; scan_data <= x"0800";
when X"C" => dot_data <= x"4208"; scan_data <= x"1000";
when X"D" => dot_data <= x"4210"; scan_data <= x"2000";
when X"E" => dot_data <= x"7C3E"; scan_data <= x"4000";
when X"F" => dot_data <= x"0000"; scan_data <= x"8000";
when others => dot_data <=x"0000"; scan_data <= x"0000";
end case;
end if;
end process;
end Behavioral;
LDM(LED Dot Matrix) 출력(Verilog) - 1
module ldm01(clock, dot_data, scan_data);input clock;output reg [15:0] dot_data;output reg [0:15] scan_data;
reg [18:0] cnt;always @(posedge clock)
cnt <= cnt + 1;always @(posedge clock)
case(cnt[18:15])0 : begin dot_data <= 16'h1818; scan_data <= 16'h0001; end1 : begin dot_data <= 16'h2438; scan_data <= 16'h0002; end2 : begin dot_data <= 16'h4208; scan_data <= 16'h0004; end3 : begin dot_data <= 16'h4208; scan_data <= 16'h0008; end4 : begin dot_data <= 16'h7E08; scan_data <= 16'h0010; end5 : begin dot_data <= 16'h4208; scan_data <= 16'h0020; end6 : begin dot_data <= 16'h423E; scan_data <= 16'h0040; end7 : begin dot_data <= 16'h0000; scan_data <= 16'h0080; end8 : begin dot_data <= 16'h7C1C; scan_data <= 16'h0100; end9 : begin dot_data <= 16'h4222; scan_data <= 16'h0200; end
LDM(LED Dot Matrix) 출력(Verilog) - 2
10: begin dot_data <= 16'h4222; scan_data <= 16'h0400; end11: begin dot_data <= 16'h7C04; scan_data <= 16'h0800; end12: begin dot_data <= 16'h4208; scan_data <= 16'h1000; end13: begin dot_data <= 16'h4210; scan_data <= 16'h2000; end14: begin dot_data <= 16'h7C3E; scan_data <= 16'h4000; end15: begin dot_data <= 16'h0000; scan_data <= 16'h8000; enddefault: begin dot_data <= 16'h0000; scan_data <= 16'h0000; end
endcaseendmodule
LDM(LED Dot Matrix) 출력 UCF file - 1
Spartan 3의 UCF파일의 내용 Virtex 4의 UCF파일의 내용
LDM(LED Dot Matrix) 출력 UCF file - 2
SYS-Lab 5000에서의 동작 화면
Spartan 3의 UCF파일의 내용 Virtex 4의 UCF파일의 내용
LDM(LED Dot Matrix) 구동 실습
LDM에 0 ~ 3의 숫자를 일정 시간 간격으로 업데이트하여 출력◦ SYS-Lab 5000의 clock을 적절히 계수하여 숫자 0 → 1 → 2 → 3 → 0 → 1 → 2 → 3 …… 의 순서로 반복하여 출력
◦ 22.1184MHz의 클럭을 2^24 = 16,777,216로 분주 약 0.76초마다 하나씩 숫자가 변하도록 구성
LDM에 표시될 숫자 디자인
숫자 0의 패턴15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0000
1 03C0
2 07E0
3 0E70
4 0C30
5 0C30
6 0C30
7 0C30
8 0C30
9 0C30
10 0C30
11 0C30
12 0E70
13 07E0
14 03C0
15 0000
LDM에 표시될 숫자 디자인
숫자 1의 패턴15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0000
1 01C0
2 03C0
3 06C0
4 0CC0
5 00C0
6 00C0
7 00C0
8 00C0
9 00C0
10 00C0
11 00C0
12 00C0
13 00C0
14 1FF8
15 0000
LDM에 표시될 숫자 디자인
숫자 2의 패턴15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0000
1 07E0
2 0FF0
3 1C38
4 3818
5 0038
6 0070
7 00E0
8 01C0
9 0380
10 0700
11 0E00
12 1C00
13 3FFC
14 3FFC
15 0000
LDM에 표시될 숫자 디자인
숫자 3의 패턴15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0000
1 07C0
2 1FF0
3 3838
4 3018
5 0018
6 0070
7 07E0
8 07E0
9 0030
10 0018
11 3018
12 3838
13 1FF0
14 07C0
15 0000
LDM 숫자 표시 예제(VHDL) - 1
library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ldm02 is
Port ( clock : in STD_LOGIC;dot_data : out STD_LOGIC_VECTOR (15 downto 0);scan_data : out STD_LOGIC_VECTOR (0 to 15));
end ldm02;
architecture Behavioral of ldm02 issignal cnt : std_logic_vector(24 downto 0);
beginprocess(clock,cnt)begin
if clock'event and clock='1' thencnt <= cnt + '1';
end if;end process;
LDM 숫자 표시 예제(VHDL) - 2
process(clock,cnt)begin
if clock'event and clock='1' thencase cnt(24 downto 23) iswhen "00"=>
case cnt(18 downto 15) iswhen X"0" => dot_data <= x"0000"; scan_data <= x"0001";when X"1" => dot_data <= x"03C0"; scan_data <= x"0002";when X"2" => dot_data <= x"07E0"; scan_data <= x"0004";when X"3" => dot_data <= x"0E70"; scan_data <= x"0008";when X"4" => dot_data <= x"0C30"; scan_data <= x"0010";when X"5" => dot_data <= x"0C30"; scan_data <= x"0020";when X"6" => dot_data <= x"0C30"; scan_data <= x"0040";when X"7" => dot_data <= x"0C30"; scan_data <= x"0080";when X"8" => dot_data <= x"0C30"; scan_data <= x"0100";when X"9" => dot_data <= x"0C30"; scan_data <= x"0200";when X"A" => dot_data <= x"0C30"; scan_data <= x"0400";when X"B" => dot_data <= x"0C30"; scan_data <= x"0800";when X"C" => dot_data <= x"0E70"; scan_data <= x"1000";when X"D" => dot_data <= x"07E0"; scan_data <= x"2000";
LDM 숫자 표시 예제(VHDL) - 3
when X"E" => dot_data <= x"03C0"; scan_data <= x"4000";when X"F" => dot_data <= x"0000"; scan_data <= x"8000";when others => dot_data <=x"0000"; scan_data <= x"0000";end case;
when "01"=>case cnt(18 downto 15) iswhen X"0" => dot_data <= x"0000"; scan_data <= x"0001";when X"1" => dot_data <= x"01C0"; scan_data <= x"0002";when X"2" => dot_data <= x"03C0"; scan_data <= x"0004";when X"3" => dot_data <= x"06C0"; scan_data <= x"0008";when X"4" => dot_data <= x"0CC0"; scan_data <= x"0010";when X"5" => dot_data <= x"00C0"; scan_data <= x"0020";when X"6" => dot_data <= x"00C0"; scan_data <= x"0040";when X"7" => dot_data <= x"00C0"; scan_data <= x"0080";when X"8" => dot_data <= x"00C0"; scan_data <= x"0100";when X"9" => dot_data <= x"00C0"; scan_data <= x"0200";when X"A" => dot_data <= x"00C0"; scan_data <= x"0400";when X"B" => dot_data <= x"00C0"; scan_data <= x"0800";when X"C" => dot_data <= x"00C0"; scan_data <= x"1000";when X"D" => dot_data <= x"00C0"; scan_data <= x"2000";
LDM 숫자 표시 예제(VHDL) - 4
when X"E" => dot_data <= x"1FF8"; scan_data <= x"4000";when X"F" => dot_data <= x"0000"; scan_data <= x"8000";when others => dot_data <=x"0000"; scan_data <= x"0000";end case;
when "10"=>case cnt(18 downto 15) iswhen X"0" => dot_data <= x"0000"; scan_data <= x"0001";when X"1" => dot_data <= x"07E0"; scan_data <= x"0002";when X"2" => dot_data <= x"0FF0"; scan_data <= x"0004";when X"3" => dot_data <= x"1C38"; scan_data <= x"0008";when X"4" => dot_data <= x"3818"; scan_data <= x"0010";when X"5" => dot_data <= x"0038"; scan_data <= x"0020";when X"6" => dot_data <= x"0070"; scan_data <= x"0040";when X"7" => dot_data <= x"00E0"; scan_data <= x"0080";when X"8" => dot_data <= x"01C0"; scan_data <= x"0100";when X"9" => dot_data <= x"0380"; scan_data <= x"0200";when X"A" => dot_data <= x"0700"; scan_data <= x"0400";when X"B" => dot_data <= x"0E00"; scan_data <= x"0800";when X"C" => dot_data <= x"1C00"; scan_data <= x"1000";when X"D" => dot_data <= x"3FFC"; scan_data <= x"2000";
LDM 숫자 표시 예제(VHDL) - 5
when X"E" => dot_data <= x"3FFC"; scan_data <= x"4000";when X"F" => dot_data <= x"0000"; scan_data <= x"8000";when others => dot_data <=x"0000"; scan_data <= x"0000";end case;
when "11"=>case cnt(18 downto 15) iswhen X"0" => dot_data <= x"0000"; scan_data <= x"0001";when X"1" => dot_data <= x"07C0"; scan_data <= x"0002";when X"2" => dot_data <= x"1FF0"; scan_data <= x"0004";when X"3" => dot_data <= x"3838"; scan_data <= x"0008";when X"4" => dot_data <= x"3018"; scan_data <= x"0010";when X"5" => dot_data <= x"0018"; scan_data <= x"0020";when X"6" => dot_data <= x"0070"; scan_data <= x"0040";when X"7" => dot_data <= x"07E0"; scan_data <= x"0080";when X"8" => dot_data <= x"07E0"; scan_data <= x"0100";when X"9" => dot_data <= x"0030"; scan_data <= x"0200";when X"A" => dot_data <= x"0018"; scan_data <= x"0400";when X"B" => dot_data <= x"3018"; scan_data <= x"0800";when X"C" => dot_data <= x"3838"; scan_data <= x"1000";when X"D" => dot_data <= x"1FF0"; scan_data <= x"2000";
LDM 숫자 표시 예제(VHDL) - 6
when X"F" => dot_data <= x"0000"; scan_data <= x"8000";when others => dot_data <=x"0000"; scan_data <= x"0000";end case;
when others => dot_data <=x"0000"; scan_data <= x"0000";end case;
end if;end process;
end Behavioral;
LDM 숫자 표시 예제(Verilog) - 1module ldm02(clock, dot_data, scan_data);
input clock;output reg [15:0] dot_data;output reg [0:15] scan_data;reg [24:0] cnt;
always @(posedge clock)cnt <= cnt + 1;
always @(posedge clock)case(cnt[24:23])0 : begin
case(cnt[18:15])0 : begin dot_data <= 16'h0000; scan_data <= 16'h0001; end1 : begin dot_data <= 16'h03C0; scan_data <= 16'h0002; end2 : begin dot_data <= 16'h07E0; scan_data <= 16'h0004; end3 : begin dot_data <= 16'h0E70; scan_data <= 16'h0008; end4 : begin dot_data <= 16'h0C30; scan_data <= 16'h0010; end5 : begin dot_data <= 16'h0C30; scan_data <= 16'h0020; end6 : begin dot_data <= 16'h0C30; scan_data <= 16'h0040; end7 : begin dot_data <= 16'h0C30; scan_data <= 16'h0080; end
LDM 숫자 표시 예제(Verilog) - 28 : begin dot_data <= 16'h0C30; scan_data <= 16'h0100; end9 : begin dot_data <= 16'h0C30; scan_data <= 16'h0200; end10: begin dot_data <= 16'h0C30; scan_data <= 16'h0400; end11: begin dot_data <= 16'h0C30; scan_data <= 16'h0800; end12: begin dot_data <= 16'h0E70; scan_data <= 16'h1000; end13: begin dot_data <= 16'h07E0; scan_data <= 16'h2000; end14: begin dot_data <= 16'h03C0; scan_data <= 16'h4000; end15: begin dot_data <= 16'h0000; scan_data <= 16'h8000; enddefault: begin dot_data <= 16'h0000; scan_data <= 16'h0000; endendcaseend
1 : begincase(cnt[18:15])0 : begin dot_data <= 16'h0000; scan_data <= 16'h0001; end1 : begin dot_data <= 16'h01C0; scan_data <= 16'h0002; end2 : begin dot_data <= 16'h03C0; scan_data <= 16'h0004; end3 : begin dot_data <= 16'h06C0; scan_data <= 16'h0008; end4 : begin dot_data <= 16'h0CC0; scan_data <= 16'h0010; end5 : begin dot_data <= 16'h00C0; scan_data <= 16'h0020; end6 : begin dot_data <= 16'h00C0; scan_data <= 16'h0040; end
LDM 숫자 표시 예제(Verilog) - 3
7 : begin dot_data <= 16'h00C0; scan_data <= 16'h0080; end8 : begin dot_data <= 16'h00C0; scan_data <= 16'h0100; end9 : begin dot_data <= 16'h00C0; scan_data <= 16'h0200; end10: begin dot_data <= 16'h00C0; scan_data <= 16'h0400; end11: begin dot_data <= 16'h00C0; scan_data <= 16'h0800; end12: begin dot_data <= 16'h00C0; scan_data <= 16'h1000; end13: begin dot_data <= 16'h00C0; scan_data <= 16'h2000; end14: begin dot_data <= 16'h1FF8; scan_data <= 16'h4000; end15: begin dot_data <= 16'h0000; scan_data <= 16'h8000; enddefault: begin dot_data <= 16'h0000; scan_data <= 16'h0000; endendcaseend
2 : begincase(cnt[18:15])0 : begin dot_data <= 16'h0000; scan_data <= 16'h0001; end1 : begin dot_data <= 16'h07E0; scan_data <= 16'h0002; end2 : begin dot_data <= 16'h0FF0; scan_data <= 16'h0004; end3 : begin dot_data <= 16'h1C38; scan_data <= 16'h0008; end4 : begin dot_data <= 16'h3818; scan_data <= 16'h0010; end5 : begin dot_data <= 16'h0038; scan_data <= 16'h0020; end
LDM 숫자 표시 예제(Verilog) - 4
6 : begin dot_data <= 16'h0070; scan_data <= 16'h0040; end7 : begin dot_data <= 16'h00E0; scan_data <= 16'h0080; end8 : begin dot_data <= 16'h01C0; scan_data <= 16'h0100; end9 : begin dot_data <= 16'h0380; scan_data <= 16'h0200; end10: begin dot_data <= 16'h0700; scan_data <= 16'h0400; end11: begin dot_data <= 16'h0E00; scan_data <= 16'h0800; end12: begin dot_data <= 16'h1C00; scan_data <= 16'h1000; end13: begin dot_data <= 16'h3FFC; scan_data <= 16'h2000; end14: begin dot_data <= 16'h3FFC; scan_data <= 16'h4000; end15: begin dot_data <= 16'h0000; scan_data <= 16'h8000; enddefault: begin dot_data <= 16'h0000; scan_data <= 16'h0000; endendcaseend
3 : begincase(cnt[18:15])0 : begin dot_data <= 16'h0000; scan_data <= 16'h0001; end1 : begin dot_data <= 16'h07C0; scan_data <= 16'h0002; end2 : begin dot_data <= 16'h1FF0; scan_data <= 16'h0004; end3 : begin dot_data <= 16'h3838; scan_data <= 16'h0008; end4 : begin dot_data <= 16'h3018; scan_data <= 16'h0010; end
LDM 숫자 표시 예제(Verilog) - 5
5 : begin dot_data <= 16'h0018; scan_data <= 16'h0020; end6 : begin dot_data <= 16'h0070; scan_data <= 16'h0040; end7 : begin dot_data <= 16'h07E0; scan_data <= 16'h0080; end8 : begin dot_data <= 16'h07E0; scan_data <= 16'h0100; end9 : begin dot_data <= 16'h0030; scan_data <= 16'h0200; end10: begin dot_data <= 16'h0018; scan_data <= 16'h0400; end11: begin dot_data <= 16'h3018; scan_data <= 16'h0800; end12: begin dot_data <= 16'h3838; scan_data <= 16'h1000; end13: begin dot_data <= 16'h1FF0; scan_data <= 16'h2000; end14: begin dot_data <= 16'h07C0; scan_data <= 16'h4000; end15: begin dot_data <= 16'h0000; scan_data <= 16'h8000; enddefault: begin dot_data <= 16'h0000; scan_data <= 16'h0000; endendcaseend
default: begin dot_data <= 16'h0000; scan_data <= 16'h0000; endendcase
endmodule
