354 33 Powerpoint-slides CH21

8/12/2019 354 33 Powerpoint-slides CH21

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N. Senthil Kumar,

M. Saravanan &

S. Jeevananthan


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HARDWARE FEATURES OF 8096

Oxford University Press 2013


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Parallel Ports and its

Structure in 80968096 has five 8-bit Input / output ports.The ports are named as

Port 0

Port 1

Port 2

Port 3

Port 4



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Port 0 Port 0 is an input only port, which is also used as the

analog input port for the Analog to Digital converter

(ADC).

So if the analog input features of 8096 are not used,these eight port 0 lines can be used as the input port.

The address of the port 0 is 0E(hex), which lies in the

On-chip memory

Thus the status or voltage of port 0 pins can be read

from the address 0EH.



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Port 1 Port 1 is a quasi-bi-directional port; meaning that port 1

can be used as input or output.

Port 1 is mapped at the internal memory address 0FH.

If any one of the port 1 pin is to be used as an input then

the software should write a 1 onto its corresponding bit

in the address 0FH, before reading the status of that bit.

For example, if bit 0 and bit 1 of Port1 is to be used as

input port, output the byte 0000 0011 to the port 1 first,then read the status of the bit 0 and bit 1 of port 1.



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Port 2 Port 2 has three types of port lines input only; output

only and quasi-bi-directional.

Except the P2.6 and P2.7 (sixth and seventh pin of

Port 2), the remaining port 2 pins have alternatefunctions as given below.

Address of Port 2 is 10H.

If a particular alternate function is not used, then the

appropriate port 2 pin can be used as an input or

output pin.

P2.6 and P2.7 function is similar to that of Port 1 pins



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Port Structure of Port 2


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Bit Functions of Port 2


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Ports 3 and 4 Ports 3 and 4 pins have two functions.

They are either bi-directional ports with open drain

outputs or system bus pins which memory controller

uses when it is accessing off chip memory.

Since we are using the external address and data bus,port 3 and port 4 lines are not available for the user.

If the line is low, the pins always act as the system bus.

Otherwise they act as bus pins only during a memory

access.

If these pins are being used as ports, 1s must be written

to them prior to bus operations.


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Port Structure of Ports 3, 4


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Input / Output Control Register 0

(IOC0)

IOC0 is located at 0015H.

The four HSI lines can be enabled or disabled

to the HSI unit by setting or clearing bits in

IOC0.

Timer 2 functions including clock and reset

sources are also determined by IOC0.


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Bit Format of IOC0


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Input / Output Control Register 1 IOC1 is used to select some pin functions and enable or disable

some interrupt sources.

Port pin 2.5 can be selected to be the PWM output instead of a

standard output by setting D0 bit of IOC1.

Using D1 bit, the external interrupt source can be selected to be

either EXTINT (same pin as P2.2) or Analog channel 7(ACH7, samepin as P0.7).

Timer1 and timer 2 overflow interrupts can be individually enabled

or disabled using the bits D2 and D3.

The HS1 interrupt can be selected to activate either when there is 1

FIFO entry or 7 entries depending upon D7 bit.

Port pin P2.0 can be selected to be the TXD output by setting D5

bit. HSO.4 & HSO.5 can be enabled or disabled to the HSO unit

using D4 and D6 bits.


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IOC1 is used to select some pin functions and enable or disable

some interrupt sources. Port pin 2.5 can be selected to be the PWM output instead of a

standard output by setting D0 bit of IOC1.

Using D1 bit, the external interrupt source can be selected to be

either EXTINT (same pin as P2.2) or Analog channel 7(ACH7, same

pin as P0.7).

Timer1 and timer 2 overflow interrupts can be individually enabled

or disabled using the bits D2 and D3.

The HS1 interrupt can be selected to activate either when there is 1

FIFO entry or 7 entries depending upon D7 bit.

Port pin P2.0 can be selected to be the TXD output by setting D5

bit. HSO.4 & HSO.5 can be enabled or disabled to the HSO unit

using D4 and D6 bits.

Input / Output Control Register 1


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Input / Output Status Register 0

(IOS0)

There are two I/O status registers, IOS0 and

IOS1.

The address of the IOS0 register is 0015H.

It holds the current status of the HSO lines

and CAM.


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Bit Format of Input / Output Status

Register 0 (IOS0)


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Input / Output Status Register 1 (IOS1)

IOS1 is located at 0016H.

It contains status bits for the timers and HSI/0.

Whenever the processor reads this register all of the

time related flags (bits 5 through 0) are cleared. This applies not only to explicit reads such as:

LDB AL, IOS1

But also to implicit reads such as;JB IOS1.3, THERE which jumps to THERE if bit 3

of IOS1 is set.


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Bit Format of Input / OutputStatus Register1 (IOS1)


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Timers Two 16-bit timers are available for use on

8096.

The first is designated Timer1, the second,

Timer 2.

Timer 1 is used to synchronize events to real

time, while timer 2 can be clocked externally

and synchronizes events to externaloccurrences.


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Timer 1 The 8096s timer 1 is a 16 bit counter which is

clocked every 2 micro seconds (i.e. every eight

internal clock cycles).

It can be read from at any time but must

never be written to.

Further, while 000BH contains the upper byte

of timer 1 and 000AH contains its lower byte.


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Timer 1 Operation and Control


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The hardware accepts only reads of the entire 2-byte

word as in example.ADD HSO-TIME, Timer1, #15

which reads timer1 value and adds 15 to that value andstores the result in HSO-TIME.

Timer 1 is used in conjunction with the high-speed input/output system.

They make up the 8096s programmable timer capabilitywhich times input events and controls the timing foroutput events.

Timer 1 can be cleared only by executing a reset. IOC1 isused to enable the interrupts when the timer 1overflows.

The overflow can be read from the status register IOS1.



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Timer 2 Timer 2 is a 16-bit event counter.

It must be clocked by a signal coming into the chip

on either of two pins.

Timer 2 is counted on both the rising edges and thefalling edges of the input signal and the minimum

time between edges is 2.0 microseconds.

This corresponds to a square wave input having a

max frequency of 250 KHz.


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Reset for Timer 2 Write a 1 to bit 1 of IOCO. This resets timer 2. (But does not hold it at

reset) Setup the high-speed output facility to reset timer 2. This permits Timer 2

to be reset when it (timer 2) has reached a certain count. In this way a

modulo-N-counter of input events can be produced, perhaps to generate

an interrupt and an output pulse each time that a rotating gear makes one

complete revolution. Receive a rising input edge on high-speed input pin HSI.0. This also

permits us to determine the time when resetting took place, since the

rising edge into HSI.0 can be used to capture the value of timer 1 at that

instant.

Receive a rising input edge on T2RST. This choice might be used in place ofHSI.0 if we do not actually need to know the time when resetting takes

place. In this way HSI.0 is released to carry out a timing function.

All of these options are controlled by what is written into Input/output

control register 0 (IOCO)


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Interrupts

There are 21 sources of interrupts on the 8096.

These sources are grouped into 8 interrupt types.

Each of the eight types of interrupt has its own

interrupt vector.

In addition to the 8 standard interrupts, there is a

TRAP instruction, which acts as software generated

interrupt.


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Interrupt Sources The external interrupts can be applied to the Pins EXTINT or ACH7, this

forms the first group of interrupts.

The serial port interrupts TI and RI form the next group of interrupts.

The software timers 0,1,2,3 form another group of interrupts along with

starting of ADC.

The HSI.0 input can be used as an interrupt. Any such HSO operation if

completed can interrupt the processor. This forms a group of interrupts.

The HSI unit can be programmed to record the timing of any input

appearing at the HIS pins.

After the recoding of any event on HSI pins, the processor can be

interrupted with the Interrupt named HSI data available.

The ADC unit can also interrupt the processor after the completion of theconversion.

The last group of interrupts is the timer overflow interrupt and they are

programmed to count up to the desired count value and then to give an

interrupt to the processor.


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Interrupt Sources


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Interrupt Vector Locations and Their

Priorities


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Polling Routine

All micro controllers must execute a polling routine todetermine the source of the interrupt whenever an

interrupt occurs.

That is first part of the interrupt service is used to poll

each possible sources of the interrupt to determine

which caused the interrupt.


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Polling Routine to Determine the Source of Interrupt


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Vectored Interrupt


In vectored interrupts, each source of an interrupt leadsdirectly to the code, which needs to be executed to service

that specific source.

In vectored priority interrupt, one source of an interrupt

may be receiving service when a higher priority source

suddenly becomes ready for service. Rather than making the higher priority source wait, the

micro controller will let the higher priority source preempt

the lower one.

The lower priority service routine is put on hold until thehigher priority service routine is finished, at which point

the lower one picks up again.


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Vectored Priority Interrupt


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Vectored Priority Interrupt

On the left, interrupt service routine 5 is shown

interrupting the main line program.

In the middle of its execution, the higher priority

interrupts service routine 3 comes in and gets serviced,where after that 5 finishes up.

The right part of the figure is intended to illustrate the

higher priority 3 source getting service and causing the

servicing of the interrupt source 5 to be delayed until it is

done.


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Priority of Pending Interrupts

handled automatically by CPU


Another possibility, which is almost as good as no interrupt service

routine takes very long, is illustrated in the next slide.

It keeps interrupts disabled throughout its service routine. While it is

being serviced, four other sources become ready for service. At the completion of the first interrupt service routine, the four

interrupt sources which are pending (i.e. waiting) are automatically

sorted out by the CPU, which immediately goes into the service routine

for the highest priority source.

The only difference between this case and the previous case is the

duration of the longest interrupt service routine, since this is maximum

amount of increased latency. (i.e. increased delay) which any source will

see.


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Priority of Pending Interrupts handledautomatically by CPU


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Interrupt Control


The 8096 support the interrupt response to any of 21 different sources. Each interrupt source filters through a sequence of enabling conditions to

determine whether it can actually interrupt CPU operation.

Fundamental to interrupt operation is the status word or PSW.

The most significant byte of PSW contains the CPUs flag bits.

One of these bits, PSW bit 9 is the global interrupt enable bit I and iscleared at reset time, disabling all interrupt initially. It is set under

program control to enable any interrupt to the CPU.

The program status word (PSW) contains a global disable bit I, which is

set or cleared using the EI or DI instruction.

The three register that control the interrupt system are(i) INT_PENDING REGISTER

(ii) INT_MASKING REGISTER

(iii) PROGRAM STATUS WORD


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Interrupt Pending Register


When the hardware detects one of the eight

interrupts, it sets the corresponding bit in the

interrupt pending register (INT_PENDING, 09H).

When the interrupt vector is read, the pending bit is

cleared automatically.

This register can be read or modified as a byte

register.

It can be read to determine which of the interrupts

are pending at any given time or modified to eitherclear pending interrupts or generate interrupts under

software control.


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Interrupt Pending Register Any software, which modifies the INT_PENDING register,

should ensure that the entire operation is indivisible.

The easiest way to do this is to use the logical instructions

in the two or three operand format.

For example, to invoke the Analog to Digital conversion

complete - interrupt service routine, we can execute thefollowing:

ORB INT_PENDING, # 0000 0010 B

We can also eliminate a pending interrupt by clearing the

associated bit of INT_PENDING i.e.ANDB INT_PENDING, # 11111101B : clears

the A/D interrupt.


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Bit Format of Interrupt

Pending Register



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Interrupt Mask Register


Individual interrupts can be enabled or disabled by setting

or clearing bits in the interrupt mask register.

The format of this register is same as that of the interrupt

pending register.

A one in any bit position will enable the correspondinginterrupt source and a zero will disable it.

The INT_MASK register can be read or written as byte

register.

The INT_MASK register also can be accessed as the lowereight bits of the PSW so the PUSHF and POPF instruction

save and restore the INT_MASK register as well as the

global interrupt lockout and the arithmetic flags.


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Global Disable


The processing of all interrupts can be disabled by

clearing the I bit in the PSW.

Setting the I bit will enable interrupt that have mask

register bits, which are set.

The I bit is controlled by the EI (Enable Interrupts) and DI

(Disable Interrupts) instructions. The I bit only controls the actual servicing of interrupt.

Interrupts that occur during periods of lockout will be

held in the pending register and serviced in a prioritized

basis when the lockout period ends. The priority encoder looks at all the interrupts that are

both pending and enabled and selects the one with the

highest priority.


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Global Disable

When the interrupt controller decides to process aninterrupt, it executes a Call to an interrupt service

Routine (ISR).

The address of ISR is contained in the corresponding

interrupt vector location.

The interrupt controller clears the associated pending bit

then pushes the return address on to the stack.

As an example, consider HSI data available CPU will

receive an interrupt when the high-speed inputs FIFO is

full, if three conditions are met. Bit 7 of the IOC1 (I/O control register 1) is set

Bit 2 of psw, which is also bit 2 of INT_MASK is set.

The I (Interrupt enable) bit in the PSW is set.


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Program Status Word (PSW)


The program status word (PSW) is a collection ofBoolean flags, which contain information

concerning the state of users program.

The high byte of the PSW contains status flags and

the low byte contains an interrupt mask register. The PSW can be saved in the system stack with a

single operation (PUSHF) and restored in a link

manner (POPF).


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Bit format of Program

Status Word



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Program Status Word


The designers of the 8096 have permitted us the flexibility of

installing our own priority scheme in place of priority shown

previously.

For example, suppose we choose to give the A/D conversion

complete - interrupt the highest priority and the high-speed

output interrupt the next highest priority. In this case, the A/D conversion complete interrupt service

routine, ADCC-ISR, will take the following form

ADCC-ISR: PUSH F : Save the PSW, then clear PSW

.. : Service A/D converter (with I=0)

....

POP F : Restore PSW

RET : and return from interrupt

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