07L09-Term Project (LC3).ppt [호환 모드] -...

Term Project:Single Bus Processor

Design and simulate the LC-3 processor Design and simulate the LC-3 processor using VHDL

Register Files

Register File consists of 8 registers:n Two 16-bit output busses: SR1 and SR2n One 16-bit input bus: DR

SelSR1

SelSR2SR1 SR1

SelSR1

SelSR216

163

3

3

Register is selected by:n SelSR1 selects the register to

put on SR1n SelSR2 selects the register to

put on SR2 SelDR

DR

SR2

DRin

SR2

DR

SelDR

CLK

16

163put on SR2n SelDR selects the register to be

written via DR when DRin is 1

Behaves as a combinational logic block:

w SelSR1 or SelSR2 valid = > SR1

LC-3 Architecture 2

w SelSR1 or SelSR2 valid = > SR1 or SR2 valid after “access time.”

Register Files

3SelSR1

16DR

R0

R1

R2

R3

R4

mux...

16

16 SR1

Decoder R4

R5

R6

R7

mux

...

16 SR2

...

Decoder

LC-3 Architecture 3

3

SelSR23

SelDR DRin Clock

Single Bus Architecture

Accumulator based architecture16SelDR MAR

R0R1R2R3R4R5R6R7

16SelDRDRin

MDR

MARMemory

Unit

R7

1616

16

SelSR1SelSR2

Src1Src2ALUop

PC

IRControl

Unit

LC-3 Architecture 4

InternalSystem

Bus

Unit

I nstruction Set Architecture

ISA = All of the programmer-visible components and operations of the computer

memory organizationn memory organizationw address space -- how may locations can be addressed?w addressibility -- how many bits per location?

n register setw how many? what size? how are they used?

n instruction setopcodesw opcodes

w data typesw addressing modes

ISA provides all information needed for someone that wants towrite a program in machine language (or translate from a high-level language to machine language).

LC-3 Architecture 5

(or translate from a high-level language to machine language).

Memory and Registers

Memoryn address space: 216 locations (16-bit addresses)n addressability: 16 bits

Registersn temporary storage, accessed in a single machine cycle

w accessing memory generally takes longer than a single cycle

n eight general-purpose registers: R0 - R7n eight general-purpose registers: R0 - R7w each 16 bits widew R7 is used to store the return address in subroutine jumpw how many bits to uniquely identify a register?

n other registersw not directly addressable, but used by (and affected by) instructions

LC-3 Architecture 6

w not directly addressable, but used by (and affected by) instructionsw PC (program counter), CC (condition codes), MAR (memory address

register), MDR (memory data register)

I nstruction Set

Opcodesn 15 opcodesn Operate instructions: ADD, AND, NOTn Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STIn Control instructions: BR, JSR, JMP, RET, TRAPn some opcodes set/clear condition codes, based on result:

w N = negative, Z = zero, C = carry

Data TypesData Typesn 16-bit 2’s complement integer

Addressing Modesn How is the location of an operand specified?n non-memory addresses: immediate, register

LC-3 Architecture 7

non-memory addresses: immediate, registern memory addresses: PC-relative, indirect, base+offset

Data Processing I nstructions

Only three operations: ADD, AND, NOT

Source and destination operands are registersn These instructions do not reference memory.n ADD and AND can use “immediate”mode,

where one operand is hard-wired into the instruction.

LC-3 Architecture 8

Data Movement I nstructions

Load -- read data from memory to registern LD: PC-relative moden LDR: base+offset moden LDI: indirect mode

Store -- write data from register to memoryn ST: PC-relative moden ST: PC-relative moden STR: base+offset moden STI: indirect mode

Load effective address -- compute address, save in register

LC-3 Architecture 9

registern LEA: immediate moden does not access memory

Control I nstructions

Used to alter the sequence of instructions(by changing the Program Counter)

Conditional Branch : BR[nzc]n branch is taken if a specified condition is true

w signed offset is added to PC to yield new PCn else, the branch is not takenn else, the branch is not taken

w PC is not changed, points to the next sequential instruction

Unconditional Branch : JMP, JSR, RETn always changes the PC

TRAP

LC-3 Architecture 10

TRAPn changes PC to the address of an OS “service routine”n routine will return control to the next instruction (after TRAP)

Branch I nstructionBranch specifies one or more condition codes.

I f the set bit is specified, the branch is taken.

n PC-relative addressing: target address is made by adding signed offset (IR[8:0])

R1 ← x3100R3 ← 0R2 ← 12

R4 ← M[R1]R3 ← R3+R4

adding signed offset (IR[8:0]) to current PC.

n Note: PC has already been incremented by FETCH stage.

n Note: Target must be within 256 words of BR instruction.

R2=0? R3 ← R3+R4R1 ← R1+1R2 ← R2-1

NO

YES


256 words of BR instruction.

I f the branch is not taken, the next sequential instruction is executed.

Condition Codes

LC-3 has three condition code registers:N -- negativeZ -- zeroZ -- zeroC -- carry

Set by any instruction that writes a value to a register(ADD, AND, NOT, LD, LDR, LDI, LEA)(ADD, AND, NOT, LD, LDR, LDI, LEA)

Exactly one will be set at all timesn Based on the last instruction that altered a register


I nstruction Format

opcode reg reg 0 reg0 0

opcode reg reg 1 offset5

opcode reg reg 0 reg0 0

opcode reg offset9

opcode reg offset6reg

opcode reg offset9

opcode offset111

opcode 0 0 0 0 0 0reg0 0 0


opcode offset80 0 0 0

Register Addressing Modes

NOT R3, R5R0R1NOT R3 R5

0101 0000 1111 0000

1010 1111 0000 1111

R1R2R3R4R5R6R7

1001 011 101 111111IR

NOT R3 R5

NOT

16

16

16


Immediate Addressing Mode

Immediate field is sign-extended

0000 0000 0000 0100R0

ADD R1 R4 -2

ADD R1, R4, # -2

0000 0000 0000 0100

0000 0000 0000 0110

R1R2R3R4R5R6R7

0001 001 100 1 11110IR

ADD R1 R4 -2

SEXT

1111 1111 1111 1110

5

16

1111 1111 1111 1110

ADD

16

16

16


PC-Relative Addressing Mode

Want to specify address directly in the instructionn But an address is 16 bits, and so is an instruction!n After subtracting 4 bits for opcode and 3 bits for register, we

have 9 bits available for address.

Solution:n Use the 9 bits as a signed offset from the current PC.Use the 9 bits as a signed offset from the current PC.

9 bits:Can form any address X, such that:

Remember that PC is incremented as part of the FETCH phase;

255offset256 +≤≤−255PCX256PC +≤≤−


Remember that PC is incremented as part of the FETCH phase;This is done before the EVALUATE ADDRESS stage.

PC-Relative Addressing Mode

LD R2, x1AFR0

LD R2 x1AF

0100 0000 0001 1001PC

0000 0000 0000 0101R1R2R3R4R5R6R7

0010 010 110101111IR

LD R2 x1AF

SEXT

1111 1111 1010 1111

9

16

1111 1111 1010 1111

ADD

16

16

16

16


MAR MDR

Memory

16 16

Base + Offset Addressing Mode

With PC-relative mode, can only address data within 256 words of the instruction.n What about the rest of memory?

Solution # 2:n Use a register to generate a full 16-bit address.

4 bits for opcode, 3 for src/dest register,3 bits for baseregister -- remaining 6 bits are used as a signed offset.

n Offset is sign-extended before adding to base register.


Base + Offset Addressing Mode

LDR R1, R2, x1D

0000 1111 0000 1111R0

LDR R1 R2 x1D 0000 1111 0000 11110010 0011 0100 0101

R1R2R3R4R5R6R7

SEXT

0000 0000 0001 1101

6

16

1010 001 010 011101IR

LDR R1 R2 x1D

0000 0000 0001 1101

ADD

16

16

16

16


MAR MDR

Memory

16 16

I ndirect Addressing Mode

With PC-relative mode, can only address data within 256 words of the instruction.n What about the rest of memory?

Solution # 1: n Read address from memory location,

then load/store to that address.then load/store to that address.

First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store.


I ndirect Addressing Mode

LDI R3, x1CCR0

LDI R3 x1CC

0100 1010 0001 1100PC

0000 0000 0000 0101

R1R2R3R4R5R6R7

1010 011 111001100IR

LDI R3 x1CC

SEXT

1111 1111 1100 1100

9

16

1111 1111 1100 1100

ADD

16

16

16


MAR MDR

Memory

16

I nstruction Set

0 0 0 1 DR SR1ADD 0 SR20 00 0 0 1 DR SR1 1 Imm5

RegisterImmediate

0 0 0 0BR PCoffset9 PC-RelativeN Z C

0 1 0 1 DR SR1AND 0 SR20 00 1 0 1 DR SR1 1 Imm5

RegisterImmediate

0 0 0 1 DR SR1 1 Imm5 Immediate0 0 1 0 DRLD PCoffset9 PC-Relative0 0 1 1 RsST PCoffset9 PC-Relative

0 1 0 0 PCoffset11 PC-Relative0 1 0 0JSR 0 0 0 0 0 0 Base register0 Base0 0

1

1 0 0 1 DR Rs 1 1 1 1 1 1NOT Register1 0 1 0 DRLDI PCoffset9 Indirect

0 1 1 0 DRLDR offset6 Base+offsetBase

1 0 1 1 RsSTI PCoffset9 Indirect

0 1 1 1 RsSTR offset6 Base+offsetBase


1 1 0 0JMP 0 0 0 0 0 0 Base register0 0 0 Base1 1 0 1RET 0 0 0 0 0 0 register0 0 0 R7

1 1 1 1TRAP TrapVector80 0 0 01 1 1 0 DRLEA PCoffset9 PC-Relative

Psudo-Direct

I nstruction SetOperation opcode Example Macro-operation Addressing mode

1001 NOT R1, R2 R1ß ~ R2 Register

AND R1, R2, R3 R1ß R2 & R3 RegisterData

Processing0101

AND R1, R2, R3 R1ß R2 & R3 Register

AND R1, R2, # x2 R1ß R2 & x2 Immeadate

0001ADD R1, R2, R3 R1ß R2 + R3 Register

ADD R1, R2, # x2 R1ß R2 + x0002 Immeadate

0010 LD R1, x123 R1ß M[PC+ x0123] Relative

0110 LDR R1, R2, x12 R1ß M[R2+ x12] Base-Offset

1010 LDI R1, x123 R1ß M[ M[PC+ x123] ] IndirectData

Movement

1010 LDI R1, x123 R1ß M[ M[PC+ x123] ] Indirect

1110 LEA R1, x123 R1ß PC + x123 Relative

0011 ST R1, x123 M[PC+ x0123] ß R1 Relative

0111 STR R1, R2, x12 M[R2+ x12] ß R1 Base-Offset

1011 STI R1, x123 M[ M[PC+ x123] ] ß R1 Indirect

ProgramControl

0000 BR[nzc] x123 If [nzc] PCß PC + x123 Relative


Control 1100 JMP R1 PCß R1 Register

0100JSR R1 R7ßPC; PCßR1 Register

JSR x123 R7ßPC; PCß PC + x123 Relative

1101 RET PCß R7 Implicit

Sample Program

Address I nstruction Comments

x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1 ← x3100 x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1 ← x3100 (PC+ 0xFF)

x3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3 ← 0

x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 ← 0

x3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2 ← 12

I f Z, goto x300A x3004 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 I f Z, goto x300A (PC+ 5)

x3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 Load next value to R4

x3006 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 Add to R3

x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 I ncrement R1 (pointer)

Decrement R2


X3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 Decrement R2 (counter)

x3009 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Goto x3004 (PC-6)

Program (1 of 2)


x3000 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 ← 0 (counter)x3000 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2 ← 0 (counter)

x3001 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 R3 ← M[x3102] (ptr)

x3002 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 I nput to R0 (TRAP x23)

x3003 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1 ← M[R3]

x3004 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 R4 ← R1 – 4 (EOT)

x3005 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 I f Z, goto x300E

x3006 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 R1 ← NOT R1

x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 R1 ← R1 + 1


X3008 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 R1 ← R1 + R0

x3009 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 I f N or C, goto x300B

Program (2 of 2)


x300A 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 R2 ← R2 + 1x300A 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 R2 ← R2 + 1

x300B 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 R3 ← R3 + 1

x300C 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1 ← M[R3]

x300D 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 Goto x3004

x300E 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 R0 ← M[x3013]

x300F 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 R0 ← R0 + R2

x3010 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Print R0 (TRAP x21)

x3011 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 HALT (TRAP x25)


X3012 Starting Address of File

x3013 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 ASCI I x30 (‘0’)

Single Bus Architecture

Accumulator based architecture16SelDR MAR

R0R1R2R3R4R5R6R7

16SelDRDRin

MDR

MARMemory

Unit

R7

1616

16

SelSR1SelSR2

Src1Src2ALUop

PC

IRControl

Unit


InternalSystem

Bus

Unit

Basic Single Bus Architecture

R0MAR

1616

16

MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R7

PC

MemoryUnit

1616

MAR

16

16

16

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

MDR

1616

16

16

IR R/W

MDRin

Data bus

SelMDRSrc1Src2

1 0

1616

PCout


MDR

16

IRin

… R/W

16Control

Unit

Control bus

ALUout MDRout

Register Transfer Logic

MARßPCPCßPC+2MDRßM[MAR]IRßMDRIR[15:12]

DR ß ~SRSet CCNOT

AND DRßSR1&SR2Set CCIR[5] 0Set CC

DRßSR1&SExt(IR[4:0])Set CC

1

ADD DRßSR1+SR2Set CCIR[5]

1

0


DRßSR1+SExt(IR[4:0])Set CC

1


MARßPC+SExt(IR[8:0]) MDRßM[MAR] DRßMDRSet CC

LD

MARßPC+SExt(IR[8:0]) MDRßM[MAR] MARßMDRLDI MARßPC+SExt(IR[8:0]) MDRßM[MAR]

MDRßM[MAR] DRßMDRSet CC

MARßMDRLDI

MARßBase+SExt(IR[5:0]) MDRßM[MAR] DRßMDRSet CC

LDR

LEA DRßPC+SExt(IR[8:0])Set CC

MARßPC+SExt(IR[8:0]) MDRßSR M[MAR]ß MDRST

MARßPC+SExt(IR[8:0]) MDRßM[MAR]

MDRßSR M[MAR]ßMDR

MARßMDRSTI

LEA Set CC


MDRßSR M[MAR]ßMDR

MARßBase+SExt(IR[5:0]) MDRßSR M[MAR]ßMDRSTR


PCßPC+SExt(IR[8:0])BR IR[11:9]&NZC

False

True

JMP PCßBase

PCßPC+SExt(IR[10:0])

JSR R7ßPC PCßBase0IR[11]

1

PCßR7RET


TRAP MARßZExt[IR[7:0]] MDRßM[MAR]R7ßPC PCßMDR

I nstruction CycleFetch cycle Execute cycle

MARßPCPCßPC+1

MDRßM[MAR]

ExecuteADD, AND, NOT,

LD, LDI, LDR,

IRßMDR

IR[15:12]

LD, LDI, LDR,LEA,

ST, STI, STR,BR

JMP, JSR/JSRR,RET, TRAP


IR[15:12]

R0MAR

1616

16

16 MARin

SelDRDRin

Fetch Cycle Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

MemoryUnit

1616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout1616

IR

16

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

16

Src1Src2


IRin

…

ControlUnit

MDR

16

R/W

16

Control bus

MDRoutALUout

NOT (Register)

1 0 0 1 Dst Src 1 1 1 1 1 1NOT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Fetch Cycle

DR ß ~SR

IR[15:12]

Fetch Cycle

NOT

DR ß ~SRSet CC


Note: Src and Dstcould be the same register.

NOT (Register) Architecture

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

MemoryUnit

1616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout1616

16

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

16

Src1Src2

1001 DR SR 111 111

IRNOT

CC


IRin

…

ControlUnit

MDR

16

R/W

16

Control bus

MDRoutALUout3NZC

CCin

CC

ADD/ AND (Register)this zero means “register mode”

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 Dst Src1ADD 0 Src20 015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Fetch CycleFetch Cycle15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 1 Dst Src1AND 0 Src20 0

IR[15:12]IR[5]=0

Fetch Cycle

ADD

DRßSR1+SR2

IR[15:12]IR[5]=0

Fetch Cycle

AND

DRßSR1&SR2DRßSR1+SR2Set CC

DRßSR1&SR2Set CC


R0MAR

1616

16

16 MARin

SelDRDRin

ADD/ AND (Register) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

MemoryUnit

1616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout1616

16

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

16

Src1Src2

0x01 DR SR1 000 SR2

IRADD/AND

CC


IRin

…

ControlUnit

MDR

16

R/W

16

Control bus

MDRoutALUout3NZC

CCin

CC

ADD/ AND ( Immediate)this zero means “immediate mode”

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 1 Dst Scr 1 Imm5ADD15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Fetch CycleFetch Cycle15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 0 1 Dst SrcAND 1 Imm5

IR[15:12]IR[5]=1

Fetch Cycle

ADD

DRßSR1+SExt(IR[4:0])

IR[15:12]IR[5]=1

Fetch Cycle

AND

DRßSR1&SExt(IR[4:0])

Note: Immediate field issign-extended.

DRßSR1+SExt(IR[4:0])Set CC

DRßSR1&SExt(IR[4:0])Set CC


ADD/ AND ( Immediate) Architecture

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD/AND5,6,9,11

161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0x01 DR SR1 1 Imm5

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

LD (PC-Relative)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 0 DstLD PCoffset9Fetch Cycle

MARßPC+SExt(IR[8:0])

IR[15:12]

Fetch Cycle

LD


MDRßM[MAR]

DRßMDRSet CC


R0MAR

1616

16

16 MARin

SelDRDRin

LD (PC-Relative) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0010 DR PCoffset9

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

LDI ( I ndirect)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 1 0 DstLDI PCoffset9Fetch Cycle


IR[15:12]

Fetch Cycle

LDI


MDRßM[MAR]

MDRßM[MAR]

MARßMDR


MDRßM[MAR]

DRßMDRSet CC

R0MAR

1616

16

16 MARin

SelDRDRin

LDI ( I ndirect) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

1010 DR PCoffset9

IR


ANDTrSrc1

3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

LDR (Base+ Offset)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 0 Dst Base offset6LDRFetch Cycle

MARßBase+SExt(IR[5:0])

IR[15:12]

Fetch Cycle

LDR


MDRßM[MAR]

DRßMDRSet CC


R0MAR

1616

16

16 MARin

SelDRDRin

LDR (Base+ Offset) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

160110 DR BR Offset6

IR

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


ANDTrSrc1

3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

LEA (PC-Relative)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 0 Dst PCoffset9LEAFetch Cycle

IR[15:12]

Fetch Cycle

LEA

DRßPC+SExt(IR[8:0])DRßPC+SExt(IR[8:0])Set CC


R0MAR

1616

16

16 MARin

SelDRDRin

LEA (PC-Relative) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

1110 DR PCoffset9

IR


ANDTrSrc1

3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

ST (PC-Relative)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 1 1 ScrST PCoffset9Fetch Cycle


IR[15:12]

Fetch Cycle

ST


MDRßSR

M[MAR]ß MDR


ST (PC-Relative) Architecture

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0011 SR PCoffset9

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

STI ( I ndirect)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 0 1 1 SrcSTI PCoffset9Fetch Cycle


IR[15:12]

Fetch Cycle

STI


MDRßM[MAR]

MDRßSR

MARßMDR


MDRßSR

M[MAR]ßMDR

R0MAR

1616

16

16 MARin

SelDRDRin

STI ( I ndirect) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

1011 SR PCoffset9

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

STR (Base+ Offset)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 1 1 1 Src Base offset6STRFetch Cycle


IR[15:12]

Fetch Cycle

STR


MDRßSR

M[MAR]ßMDR


R0MAR

1616

16

16 MARin

SelDRDRin

STR (Base+ Offset) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0111 SR BR Offset6

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

BR (PC-Relative)15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0BR PCoffset9N Z CFetch Cycle

IR[15:12]

Fetch Cycle

BR

IR[11:9]&NZCFalse


True

LC-3 Architecture 54What happens if bits [11:9] are all zero? All one?

R0MAR

1616

16

16 MARin

SelDRDRin

BR (PC-Relative) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0000 NZC PCoffset9

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

JMP (Register)

Jump is an unconditional branch -- always taken.n Target address is the contents of a register.n Allows any target address.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 0 0JMP 0 0 0 0 0 00 0 0 Base

Fetch Cycle

IR[15:12]

JMP

PCßBase


R0MAR

1616

16

16 MARin

SelDRDRin

JMP (Register) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

1100 000 BR 000000

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

JSR (Register/ PC-Relative)

0 1 0 0JSR 0 0 0 0 0 00 0 0 Base15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Fetch Cycle

0 1 0 0 PCoffset11JSR 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JSR

R7ßPC

IR[15:12]

Fetch Cycle

PCßPC+SExt(IR[10:0])PCßBase

IR[11]0

1


R0MAR

1616

16

16 MARin

SelDRDRin

JSR (Register) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0100 0 00 BR 000000

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

R0MAR

1616

16

16 MARin

SelDRDRin

JSR (PC-Relative) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

0100 1 PCoffset11

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

RET (Register)

.1 1 0 1RET 0 0 0 0 0 00 0 0 R7

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Fetch Cycle

PCßR7

IR[15:12]

Fetch Cycle

RET

PCßR7


R0MAR

1616

16

16 MARin

SelDRDRin

RET (Register) Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16

1101 000 R7 000000

IR


3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

TRAP15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1TRAP TrapVector80 0 0 0Fetch Cycle

Calls a service routine, identified by 8-bit “trap vector.”

vector routine

x23 input a character from the keyboard

IR[15:12]

Fetch Cycle

TRAP

MARßZExt[IR[7:0]]

When routine is done, PC is set to the instruction following TRAP.

x23 input a character from the keyboard

x21 output a character to the monitor

x25 halt the program

MARßZExt[IR[7:0]]

MDRßM[MAR]R7ßPC

PCßMDR


PC is set to the instruction following TRAP.

R0MAR

1616

16

16 MARin

SelDRDRin

TRAP Architecture

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1101 000 R7 000000

IR

1 0

ADD5,6,9,11

1 0

16 161616

16

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


ControlUnit

3NZC

IRin

CCin

…ALUout

CC MDR

16

R/W

16

Control bus

MDRout

Complete RTLMARßPC; PCßPC+2MDRßM[MAR]IRßMDRIR[15:12]

DR ß ~SR; Set CCNOT

AND DRßSR1&SR2; Set CCIR[5]0AND DRßSR1&SR2; Set CC

DRßSR1&SExt(IR[4:0]); Set CC

IR[5]

1

ADD DRßSR1+SR2; Set CC

DRßSR1+SExt(IR[4:0]); Set CC

IR[5]

1

0

MARßPC+SExt(IR[8:0]) MDRßM[MAR] DRßMDR; Set CCLD

MARßPC+SExt(IR[8:0]) MDRßM[MAR] MDRßM[MAR] DRßMDR; Set CCMARßMDRLDI

MARßBase+SExt(IR[5:0]) MDRßM[MAR] DRßMDR; Set CCLDR

MARßPC+SExt(IR[8:0]) MDRßSR M[MAR]ß MDRST

MARßPC+SExt(IR[8:0]) MDRßM[MAR] MDRßSR M[MAR]ßMDRMARßMDRSTI

MARßBase+SExt(IR[5:0]) MDRßSR M[MAR]ßMDRSTR

LEA DRßPC+SExt(IR[8:0]); Set CC

PCßPC+SExt(IR[8:0])BR IR[11:9]&NZC

1

0

JMP PCßBase


JMP PCßBase


JSR R7ßPC PCßBase0

IR[11]

1

PCßR7RET

TRAP MARßZExt[IR[7:0]] MDRßM[MAR]; R7ßPC PCßMDR

Complete Architecture

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

161010 011 111 0 01 100

IR

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


ANDTrSrc1

3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

Memory-mapped I nput

MAR

16

MARin

KBSR KBDR

Address Logic

InputR/W

MemoryUnit

MAR

16

R/W

InternalSystem Bus

Address bus

16

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


MDR

16 16

MDRout

Memory-mapped Output

MAR

16

MARin

DSR DDR

Address Logic

OutputR/W

MemoryUnit

MAR

16

R/W

InternalSystem Bus

Address bus

16

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


MDR

16 16

MDRout

Memory-mapped I / O revisited

MAR

16

MARin

KBSR KBDR

Address Logic

InputR/W DSR DDR

Address Logic

OutputR/W

MemoryUnit

MAR

16

R/W

InternalSystem Bus

Address bus

16

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


MDR

16 16

MDRout

Simple Polling Routines

START LDI R1, A ;Loop if Ready not set BRzp START LDI R0, B ;If set, load char to R0 LDI R0, B ;If set, load char to R0 BR NEXT_TASK

A .FILL xFE00 ;Address of KBSRB .FILL xFE02 ;Address of KBDR

Input a character from keyboard

START LDI R1, A ;Loop if Ready not set BRzp START STI R0, B ;If set, send char to DDRBR NEXT_TASK

A .FILL xFE04 ;Address of DSRB .FILL xFE06 ;Address of DDR


B .FILL xFE06 ;Address of DDR

Output a character to the monitor

Keyboard Echo: combine the above

START LDI R1,KBSR ;Loop if KB not ready START LDI R1,KBSR ;Loop if KB not ready BRzp START LDI R0,KBDR ;Get character

ECHO LDI R1,CRTSR ;Loop if monitor not ready BRzp ECHO STI R0,CRTDR ;Send character BR NEXT_TASKBR NEXT_TASK

KBSR .FILL xFE00 ;Address of KBSRKBDR .FILL xFE02 ;Address of KBDRDSR .FILL xFE04 ;Address of DSRDDR .FILL xFE06 ;Address of DDR


Example: Print a string

LEA R1, STR ;Load address of stringLEA R1, STR ;Load address of stringLOOP LDR R0, R1, #0 ;get next char to R0

BRZ DONE ;string ends with 0LP2 LDI R3, DSR ;Loop until MON is ready

BRzp LP2 STI R0, DDR ;Write next character ADD R1, R1, #1 ; Set address to next char ADD R1, R1, #1 ; Set address to next char BR LOOP

STR .STRINGZ "Char String"DONE HALT


Complete Architecture

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

PCout

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

161010 011 111 0 01 100

IR

SExt

16SelSrc2 SelSrc1

SelSExt

Src1Src2

16

CC

PCout

MDR

16

R/W

MDRin

Data bus

SelMDR 1 0

16


ANDTrSrc1

3NZC

IRin

CCin

…

ControlUnit ALUout

CC MDR

16

R/W

16

Control bus

MDRout

Finite State MachinePcout, MARin, SelPC=1, PCinRead, SelMDT=0, MDRinMDRout, IRinIR[15:12]

SelSR1=SR1, SelSrc=0, NOT, ALUout, SelDR=DR, Drin, CCinNOTAND SelSR1=SR1, SelSrc=0, SelSR2=SR2, SelSrc2=0, AND, ALUout, SelDR=DR, Drin, CCin

SelSR1=SR1, SelSrc=0, SelSExt=5, SelSrc2=1, AND, ALUout, SelDR=DR, Drin, CCin

IR[5]0

1 SelSR1=SR1, SelSrc=0, SelSExt=5, SelSrc2=1, AND, ALUout, SelDR=DR, Drin, CCin

ADD IR[5]

1

0

SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, ALUout, MARin Read, SelMDR=0, MDRin MDRout, SelDR, Drin, CCinLD

SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, ALUout, MARin Read, SelMDR=0, MDRin

Read, SelMDR=0, MDRin MDRout, SelDR=DR, Drin, CCin

MDRout, MARinLDI

SelSR1=BR, SelSrc1=0, SelSExt=6, SelSrc2=1, ADD, ALUout, MARin Read, SelMDR=0, MDRin MDRout, SelDR=DR, Drin, CCinLDR

LEA SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, ALUout, SelDR=DR, Drin, CCin

SelSR1=SR1, SelSrc=0, SelSR2=SR2, SelSrc2=0, AND, ALUout, SelDR=DR, Drin, CCin

SelSR1=SR1, SelSrc=0, SelSExt=5, SelSrc2=1, AND, ALUout, SelDR=DR, Drin, CCin

SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, ALUout, MARin SelSR1=SR, SelSrc1=0, TrSrc1, ALUout, SelMDR=1, MDRin WriteST

SelSR1=1, SelSExt=9, SelSR2=1,ADD, ALUout, MARin Read, SelMDR=0, MDRin

SelSR1=SR, SelSrc1=0, TrSrc1, ALUout, SelMDR=1, MDRin Write

MDRout, MARinSTI

SelSR1=BR, SelSrc1=0, SelSExt=6, SelSrc2=1, ADD, ALUout, MARin SelSR1=SR, SelSrc1=0, TrSrc1, ALUout, SelMDR=1, MDRin WriteSTR

LEA SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, ALUout, SelDR=DR, Drin, CCin

SelSrc1=1, SelSExt=9, SelSrc2=1, ADD, PCSel=0, PCin

BR IR[11:9]&NZC

1

0

JMP


JMP SelSR1=BR, SelSrc1=0, TrSrc1, ALUout, SelPC=0, PCin

SelSrc1=1, SelSExt=11, SelSrc2=1, Add, ALUout, PCSel=0, PCin

JSR Pcout, SelDR=R7, DRin SelSR1=BR, SelSrc1=0, TrSrc1, ALUout, SelPC=0, PCin0

IR[11]

1

SelSR1=R7, SelSrc1=0; TrSrc1, ALUout, SelPC=0, PCinRET

TRAP SelEExt=8, SelSrc2=1, TrSrc2, ALUout, MARin Read, SelMDR=0, MDRin, PCout, SelDR=R7,DRin MDRout, SelPC=0, PCin

Complete Architecture (MUX version)

R0MAR

1616

16

16 MARin

SelDRDRin

0000 0000 0000 0101

R1R2R3R4R5R6R70100 1010 0001 1100

PC

16

MemoryUnit

161616

MAR

16

16

+2

1 0

16

16 16

SelPC

PCinR/W

SelSR1SelSR2

InternalSystem Bus

Address bus

MDR

1 0

ADDNOTAND

5,6,9,11

1 0

16 161616

16

16

16

1010 011 111 0 01 100

IR

SExt

16SelSrc2 SelSrc1

SelSExt

R/W

SelBus MDRin

Data bus

SelMDRSrc1Src2

1 0

1616

CC


MDRANDTrSrc1

16

3NZC

IRin

CCin

… R/W

16Control

Unit

Control bus

CC0 1 2

07L09-Term Project (LC3).ppt [호환 모드] -...

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