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Signal flow graph modelling of multi-state boostDCDC converters

M. Veerachary

Abstract: A systematic procedure and guidelines for developing the unified flow graph model of amulti-state boost DCDC converter is presented. From this unified model it is possible topredetermine the complete behaviour of the converter system. The proposed method provides easeof model formulation and avoids the mathematical complexity involved in obtaining the unifiedmodel. Usefulness of the proposed method is demonstrated through an example of three stateboost converters. A simplified procedure is described that can be used to deduce large-signal, small-signal and steady-state from the unified signal flow graph of the converter. Large-signal modelsmodels have been developed and programmed in the TUTSIM simulator. Large-signal responsesagainst supply and load disturbances were obtained. Theoretical results, obtained from theproposed signal flow graph method, are compared with PSIM power electronic simulator results.Experimental results are provided to validate the proposed modelling method.

1 Introduction

The switch-mode DCDC converter has evolved into anessential component for electronic equipment [1] and isfinding widespread applications in computers, batterychargers, solar cell based power converters used in spacepower conditioning systems etc. A wide variety of types ofconverter topologies have been developed by differentresearchers to cater for predefined needs. These includesimple basic converters such as buckboost and buck-boost,isolated converters, complex converters such as cascade,

interleaved converters etc. For front-end applications, boosttopology is a good choice. This boost topology has certainadvantages, such as simplicity of design, low switch stressand high conversion efficiency. However, the conventionaltwo-state boost converter control-to-output small-signaltransfer function has right-half plane (RHP) zero and itintroduces stability problems[2, 3]. A method to eliminatethe RHP zero is proposed for the simple boost converter, byintroducing an additional degree of control freedom in theconverter. This is done by providing an additional free-wheeling mode for the inductor in addition to converterboosting and capacitor charging modes. However, incor-poration of an extra freewheeling mode for the inductorrequires additional switching elements, and modelling of thesystem becomes a difficult task.

The state-space averaging method is the most popularapproach used for modelling of DCDC switchingconverters[4]. However, this method is sometimes tedious,especially when the converter circuit contains a largenumber of elements. Furthermore, the linearised modelsdo not predict large-signal stability information, and areonly sufficient to predict small-signal stability. Large-signal

models are proposed, but these models do not provide ageneralised model, which can predict the complete beha-viour of the circuit. To overcome some of the problemsdescribed, a signal flow graph (SFG) non-linear modellingmethod was developed for PWM converters [57]. Thebenefits that can be achieved from this method are: (i) itconverts the switching converter, two or multi-state, into aunified dynamic model, (ii) from the unified model, it ispossible to derive large-signal, small-signal and steady-statemodels with minimum effort, (iii) it is easier to arrive atsmall-signal models with minimum mathematical manip-

ulations, (iv) it provides the designer with an easy way offinding large-signal global behaviour when it is combinedwith the use of TUTSIM/ SIMULINK simulator: (v) it ispossible to derive various relationships between the circuitvariables without any difficulty: and (vi) it is also possibleto incorporate the cause and effect relationship of thedynamics etc.

However, the SFG method has so far happen appliedonly for simple two-state converters like buck, boost andbuckboost converters etc. Furthermore, there are noprescribed guidelines to be followed while drawing the flowgraphs for DCDC converters. In this paper, general rulesto be followed while developing the signal flow graphs for

the DCDC converter are given and then the SFG methodis applied to the analysis of a three-signal state boost DCDC converter system. Unified SFG models are developedand then derivation of large-signal, small-signal and steady-state models from the unified SFG models is demonstrated.Simulation and experimental results are given to substanti-ate the SFG modelling of the multi-state boost DCDCconverters.

2 General rules for drawing signal flow graphs ofDCDC converters

The following general rules must be observed while drawingthe signal flow graphs of DCDC converter systems:

(i) The sequence of nodes should be in the sequence ofelements, (inductors or capacitors), appearing in the circuit.Improper sequence of nodes results in a graph in which the

The author is with the Department of Electrical Engineering, Indian Institute ofTechnology Delhi, New Delhi 110 016, India

r IEE, 2004

IEE Proceedingsonline no. 20040680

doi:10.1049/ip-epa:20040680

Paper first received 21st July 2003 and in revised form 30th April 2004.Originally published online: 10th August 2004

IEE Proc.-Electr. Power Appl., Vol. 151, No. 5, September 2004 583

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number of closed loops and forward paths different fromthe true graph.

(ii) While drawing the SFGs, first voltage node and thencurrent node should be indicated for inductive elements.For capacitive elements, first current node should beindicated and then voltage node should follow.

(iii) Individual loops must be considered while writing downthe circuit loop voltage equations using Kirrchoffs voltagelow (KVL).

(iv) While using Kirrchoffs current low (KCL) at junctionpoints, shunt branch currents always must be expressed interms of other currents.

(v) The source current node is a sink node and receivessignals from all those inductors that have a commonterminal with the source.

(vi) The number of switching functions, (K1, K2, y, Kn,where n is the number of operating modes, in this casen 3), depends on the number of operating modes of thecircuit.

(vii) In the simplified SFG the closed loops are mainlyformed from the inductive and capacitive branch nodes.

The following Section uses the above rules to develop theunified signal flow graph of the three-state boost convertersystem.

3 Development of unified signal flow graph forthree state boost converter

This Section describes the SFG development of three-stateDCDC boost converter as shown in Fig. 1. This converterhas one additional mode of operation compared to theconventional boost converter, which mainly improves thedynamics of the converter system. Though the additionaloperating mode, freewheeling of the input inductor,eliminates the problem of the RHP zero, it requires anadditional switching element and increases complexity inmodelling. Particularly, considerable amount of mathema-tical simplificationis needed in arriving the small-signalmodels and controller design for the converter system. Asalready shown in the introduction, when the convertersystem contains a greater number of stages, then small-signal transfer functions derivation becomes a complex task.The proposed signal flow graph approach, given in thispaper, overcomes some of the problems existing in theconventional methods. For demonstration of SFG model-ling of multi-state converters, a three-state boost convertersystem is considered and a general discussion to obtain theunified model is given in the first stage. In the second stage,

development of the remaining models, large-signal, small-signal and steady-state, of the converter from the unifiedSFG is discussed. The assumptions used in the analysis ofthe system are: (i) switching elements of the converter

system are assumed to be ideal, (ii) the switches operate in apredefined sequence, (iii) the stray capacitances areneglected, and (iv) passive components, R, L, and C, areassumed tobe linear time-invariant.

In the general case for this converter system moretopologies are possible depending on the controlledmethodology employed, arising from the additional degreeof freedom introduced by the freewheeling of the inductor.As an illustration, detailed analysis ispresented here for thefollowing steady-state switching cycle sequence 1: free-wheeling of boost inductor, charging of boost inductor andcharging of output capacitor. However, developing theunified SFGs for other switching schemes should be similarto the one presented here.

For the continuous inductor current mode, the switchingsequence 1 described above results in three modes ofoperation in one cycle time period and these are: mode 1,mode 2 and mode 3, respectively. During the time 0otrt1(mode-1) the devices Sf, Df; during t1otrt2 (mode-2) thedevicesSf,Sm, and duringt2otrT(mode-3) the deviceDmare conducting, and thus generating three different sub-circuits. The converter switches between these three sub-circuits, which are linear, and so a linear, system theory canbe used for them. Considering the mode 1 operation as

reference, signal flow graphs G1, G2, and G3 are drawn forthe above three different sub-circuits sharing commonnodes and parts of the branches. These three signal flowgraphs are combined to form a simplified signal flow graph.While merging the graphs (G1, G2 and G3) into a singlegraphG, some of the branches may exist in the three graphsand some may not. Branches that exist in G1but not in G2,G3are replaced by K1branches, and the branches that existinG2but not in G1,G3are replaced by K2branches and soon. The resulting graph topology, can be mathematicallywritten as:

G X3

j1

KjGj 1

where K1, K2 and K3 are the switching functions, whosevalues depend on the switching times, defined by thefollowing expressions:

K1 for 0ot t1

for t1ot T

2

K2 0 for 0ot t11 for t1ot t10 for t2ot t1

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