設計於深次微米 CMOS 製程之功率感知高速類比數位轉換積體電路 (Power-Aware...

台大電機系陳信樹副教授

National Taiwan UniversityDepartment of Electrical Engineering

設計於深次微米 CMOS製程之功率感知高速類比數位轉換積體電路(Power-Aware High-Speed ADC in Deep Submicron CMOS)

文化大學電機系 2011年先進電機電子科技研討會

NTUEE ; Mixed-Signal IC Lab 陳信樹

Outline

Motivation High-speed ADC IC design example Digitally-assisted algorithm and architecture Circuit implementation Experimental results Summary

2


High-Speed ADC Applications

Ref [1]

3


Power-Aware High-Speed ADC Trends

Power / Energy Higher resolution requires more energy to achieve.

Speed / Bandwidth Resolution and speed are trade-offs.

Bottleneck SAR architecture saves power and chip area, but speed is limited

by its conversion algorithm. Pipelined architecture achieves high speed by concurrent

operations, but OPAs consume considerable power. Digitally assisted ADCs

Digitally assisted algorithm alleviates analog circuit requirement; therefore, it takes advantages of advanced processes to trade little digital power to gain the benefits from analog part.

4


High-Speed ADC Energy vs. SNDR

Energy is proportional to resolution (SNDR). FOM (Power / (Sample rate * 2ENOB)) is an indicator to compare different ADC designs. State-of-the-art ADC designs approach 10fJ/c.s. Current world record is 4fJ/c.s. Ref [2]

5


High-Speed ADC Bandwidth vs. SNDR

Bandwidth is inverse proportional to resolution (SNDR). State-of-the-art high-speed high-resolution ADCs are limited by clock jitter around

0.1psrms. Ref [2]

6


Experiment 1 - Low-Power High-Speed Two-Step ADC

Rearrange the timing of two-channel MDACs and apply a self-timing technique to alleviate comparator comparison time and charge injection disturbance

Slightly increases CADC accuracy to ease OPA signal swing design

Ref [3]

Technology 0.13μmResolution 6-bitActive area 0.16mm2

Supply voltage 1.2VSample rate 1-GS/sSFDR (Fin@Nq) 40.7dBSNR (Fin@Nq) 33.8dBSNDR (Fin@Nq) 33.7dBPower 49mWFoM 1.24pJ/c.s.

3bFlash

CADC

4bFlash

FADC1

4bFlash

FADC2

Shared Resister Ladder Clock Generator

Encoderand

Digital Correction

Logic

Vin7

15

15

6b

MDAC2

MDAC1

7


Relieve MSB accuracy requirement by the sub-range concept with overlapping

Reduce total input capacitance by using the double-unit-sized coupling-capacitor

Ref [4]

Experiment 2 - Low-Power High-Speed Sub-range SAR ADC

Technology 0.13μmResolution 12-bitActive area 0.096mm2

Supply voltage 1.2VSample rate 10MS/sSFDR (Fin@Nq) 69.8dBSNR (Fin@Nq) 61.2dBSNDR (Fin@Nq) 59.7dBPower 3mWFoM 0.38pJ/c.s.

Digital Error Correction Circuit

State Control

Coarse 6b Registers + overlapping logic

Sub Range Capacitor Array

Sample

Analog Circuit

12b

Clock

VrnVrp

VinnVinp

6b 6bGain

Control

Capacitor array output

Fine

6b

8


Attain high conversion speed by adopting non-constant-radix switching method

Compared to conventional non-binary designs, its DAC implementation is simpler.

Experiment 3 - Low-Power High-Speed SAR ADC

Technology 90nmResolution 10-bitChip area 1.029mm2

Supply voltage 1.0VSample rate 40MS/sSFDR (Fin@Nq) 61.9dBSNDR (Fin@Nq) 54.1dBPower 1.34mWFoM 81.1fJ/c.s.

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Achieve high speed with a low-gain OPA by using digitally-assisted architecture, thus the OPAs have excellent power efficiency

A simple gain-error self calibration method without external precise references requires only 168 calibration clock cycles.

Ref [5]

Experiment 4 - Low-Power High-Speed Pipelined ADC

2b Sub-ADC

Digital Error Correction

Dout

7b SA Registers

Calibration Sequence Controller

Calibration Comparator

10

3

VIN

7

2.5b Stagewith

Calibration Capacitor

7b SA Registers

3

7

2.5b Stagewith


7b SA Registers

3

7

2.5b Stage

23

VREF12

2.5b Stagewith


Clock-Boost Input

Switch

Technology 90nmResolution 10-bitActive area 0.21mm2

Supply voltage 1.2VSample rate 320MS/sSFDR (Fin@Nq) 66.7dBSNDR (Fin@Nq) 51.2dBPower 42mWFoM 0.44pJ/c.s.

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Digitally-Assisted High-Speed ADC Example (Experiment 4)

Digitally assisted architecture is future trend to achieve excellent power efficiency.

10b, several hundreds MS/s Pipeline ADCs are widely used in wireless and cloud computing systems but suffer from OPA design in deep submicron CMOS processes. Decreased OPA DC gain Smaller signal swing

11


Pipeline ADC Accuracy

OPA gain

Less Ro of MOSFET in advanced technologies Reduced gain from each stage of OPA More gain stages introduce poles and decrease bandwidth. For 10b accuracy, the 1st stage MDAC requires 66dB OPA DC gain.

Capacitor mismatch Raw matching can attain 10b accuracy, not an issue!

12


Closed-Loop Gain Error

1 1

,1 1 1/CL

AA

A A

13

For finite A, closed-loop gain ACL is smaller than ideal gain, 1/.

Gain error can be compensated by adjusting .


8

1

88, 1, 2

8 8 8ref s f ps

out in i os i f ss f p i s

f

V C C CCV V D V D C C

C C C CC

A

Due to finite A, closed-loop gain is less than ideal value of 4. adjustment is proposed to correct MDAC gain error.

8 comp.

Cf

+Vout

-Vout

Cs

Cs

Cs

+Vref -Vref

A

8

Cp

Sub-ADC

Vos

14

MDAC Gain Error


Proposed MDAC with a Calibration Capacitor

A calibration capacitor, Ccal, is added as a positive feedback to adjust Closed-loop gain can achieve 10b accuracy with low DC gain A of 30dB.

8 comp.

Ccal

Cf

Vos+Vout

-Vout

Cs

Cs

Cs

+Vref -Vref

A

8

Cp

Sub-ADC

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Self-Calibrated Algorithm (1)

Self-calibrated procedure starts with the last stage MDAC. After MDAC is calibrated, it is treated as “ideal” MDAC. Ideal MDACs subtract 3Vref/8 and then multiply 4. Under-Calibration MDAC samples Vref/8 and then multiplies 4.

Σ Σ ΣVin

ref

3V

8 ref

3V

8

IdealMDAC

ref

1V

2

To SAR Controller

Under-CalibrationMDAC

AV 4 4


IdealMDAC

ref

1V

8

Vout

16


Self-Calibrated Algorithm (2) – Gain Error

Output is Vref/2 when no gain error Using successive approximation method with iterations, the closed-

loop gain reaches 4 with 10b accuracy.

, _

,1 _" "

,2 _" "

( ) (4 ) : 8

3( ) (4 ) ( ) 4

8 8 2 2

3 4( ) 4

2 2 8 2 2

refout under calibration AV AV

ref ref ref AV refout stage ideal AV

ref AV ref ref ref AV refout stage ideal

out

VV gain error

V V V VV

V V V V VV

V

1

," " _" "

4:

2 2

Nref AV ref

N stage ideal

V VN number of MDAC stages

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Proposed ADC Architecture

2b Sub-ADC

Digital Error Correction

Dout

7b SA Registers

Calibration Sequence Controller


10

3

VIN

7

2.5b Stagewith


7b SA Registers

3

7

2.5b Stagewith


7b SA Registers

3

7

2.5b Stage

23

VREF12

2.5b Stagewith


Clock-Boost Input

Switch

On-chip foreground analog self-calibrated technique Gain errors of first three stages are calibrated

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Calibration Step

128 calibration steps Each step affects 0.14 % of MDAC gain (~4) with OPA gain of 40dB

b6 b5 b4 b3 b2 b1 b0

2Cs Cs

2Cs 8Cs 4Cs 2Cs Cs 4Cs 2Cs Cs

Cs

Opampinput

Opampoutput

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Calibration Range

Ccal in this work can calibrate OPA with a minimum DC gain of 30dB

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OPA

Use small L to increase bandwidth without considering gain Calibration mode has more compensation capacitance Simulation results: DC gain 40dB, closed-loop BW 1.36GHz

VINP VINN

VOP VON

Vb1

Vcmfb1 Vcmfb2

VDD

Vb2

CALb CALb

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Chip Micrograph

0.21mm2 active area in 90 nm low-power CMOS

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Measured DNL

Before calibration: +1.7 / -1.0 LSB After calibration: +0.7/-0.6 LSB

Before calibration After calibration

23


Measured INL

Before calibration: +15.6/-15.2 LSB After calibration: +0.8/-0.9 LSB

Before calibration After calibration

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Measured Dynamic Performance

At low Fin, SNDR ≈ 54.2dB, ENOB ≈ 8.7bit

At Nyquist Fin, SNDR ≈ 51.2dB, ENOB ≈ 8.2bit

ERBW ≈ 160MHz

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Measured FFT

SNDR ≈ 52.8dB and SFDR ≈ 57.8dB when Fs = 320MHz and Fin = 128MHz

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Measured Performance Summary

JSSC09 [7] ISSCC07 [8] This Work

Technology (nm) 90 130 90Calibration Method Foreground Foreground

/BackgroundForeground

Sample Rate (MS/s) 500 205 320Resolution (bit) 10 10 10DNL/INL (LSB) 0.4/1.0 0.15/0.6 0.7/0.9Peak SNDR (dB) 55.8 56 54.2SNDR (dB) at Fs/2 53 56 51.2SFDR (dB) - 73.5 66.7Power (mW) 55 92.5 42FoM (fJ/c.-s.) 301 881 442Active Area (mm2) 0.49 0.52 0.21Note Calibration

circuit is off-chip

Input buffer power is included

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Summary

A simple self-calibrated algorithm is proposed to correct gain error

resulting from low gain OPA in deep submicron CMOS. The self-calibrated process does not require a precise external

reference and can be done within only 168 clock cycles. Smallest active area of 0.21mm2 in 90nm CMOS including

calibration circuit The prototype ADC achieves 320MS/s conversion rate, 8.7 ENOB

and only consumes 42mW. Nice power efficiency is obtained. Power efficiency is the key to high-speed ADC IC designs.

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Reference

[1] http://www.analog.com/library/analogdialogue/archives/39-06/architecture.html[2] B. Murmann, "ADC Performance Survey 1997-2010," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html[3] H. Chen et al., “A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-m CMOS,” IEEE

J. Solid-State Circuits, vol. 44, no. 11, pp. 3051-3059, Nov. 2009.[4] H. Chen et al., “A 3mW 12b 10MS/s Sub-Range SAR ADC” in IEEE Asian Solid-State

Circuits Conf. Dig. Tech. Papers, Taipei, Taiwan, pp. 153-156, Nov. 2009.[5] H. Chen et al., “A 10b 320MS/s Self-Calibrated Pipeline ADC” in IEEE Asian Solid-

State Circuits Conf. Dig. Tech. Papers, Peking, China, pp. 173-176, Nov. 2010.[6] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution

Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.

[7] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009.

[8] B. Hernes et al.,”A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13m CMOS,” ISSCC Dig. Tech. Papers, pp. 462-463, Feb. 2007.

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設計於深次微米 CMOS 製程之功率感知高速類比數位轉換積體電路 (Power-Aware...

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