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7. Microprogrammed Control

충남대학교 정보통신공학과박 종 원

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컴퓨터구조 1Control Unit( 제어장치 )1) Hardwired CU sequential circuit 기본 operation 들로 구성된 Instruction set 고속 , 수정불가능 RISC(Reduced Instruction Set Computer) Basic Computer, SUN UltraSPARC III, MIPS R10000, HP PA-RISC MAX2, IBM and Motorola PowerPC, ARM, SuperH, Trimedia TM5200

2) Microprogrammed CU ROM 또는 WCM(Writable Control Memory) 모든 operation 들을 수행하는 Instruction set 저속 , 수정용이 CISC(Complex Instruction Set Computer) PC(Intel 80x86), IBM 360/370, VAX 11/780, Motorola 68000,TI TMS320C54x

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WCM

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Address sequencing( 다음 주소 발생 )

1) CAR CAR + 12) Branch(Unconditional or Conditional)3) A mapping process: the first address of routine4) Subroutine call and return

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Address sequencing

1. CAR CAR + 12. Branch (Unconditional or Conditional)3. A mapping process: the first address of routine4. Subroutine call5. Subroutine return

2, 4 3 5 1

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DR

CAR

151413121110 0

6 5 4 3 2 1 0

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Mutually exclusive group( 속도 향상을 위한 병렬화 )AC 4 + 3 + 4 + 1 = 12(4 bit)AR 2 + 1 = 3(2 bit)PC 2 + 1 = 3(2 bit)DR 4 + 1(Write) + 1 = 6(3 bit)

F1 F2 F3 3 bit 3 bit 3 bit

AC AR PC DR 4 bit 2 bit 2 bit 3 bit

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VerticalHorizontalDiagonal

Operation CD BR

Operation CD BR

20 + 1 (5 Bits)

20 Bits0 1 2 3 19

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The fetch routineAR PCDR M[AR], PC PC + 1AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0

ORG 64FETCH: PCTAR U JMP NEXT READ, INCPC U JMP NEXT DRTAR U MAPINDRCT: READ U JMP NEXT DRTAR U RET

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5. Basic Computer Organization

Fetch T0: AR PCT1: IR M[AR], PC PC + 1

DecodeT2: D0 ,…D7 Decode IR(12-14), AR IR(0-11), I IR(15)

IndirectD7’IT3: AR M[AR]

15 14 13 12

E I

DecoderD0 D1 ,…D7

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컴퓨터구조 1 ORG 100 ADD PA I BRANCH AD STORE SUM HLTAD, EXCHANGE SA I STORE SUM HLTPA, HEX 200SA, HEX 275SUM, HEX 0 END200 5275 20

AC -10 PC 100DR CAR 64ARSBR

Control Memory

PC

Main Memory

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10

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AC(Accumulator)

D0T5: AC AC DRD1T5: AC AC + DRD2T5: AC DRpB11: AC(0-7) INPR __rB9: AC ACrB7: AC shr AC, AC(15) ErB6: AC shl AC, AC(0) E rB11: AC 0

rB5: AC AC + 1

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Branch Logic

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S1 = I1

S0 = I1I0 + I1’TL = I1’I0T

JMP

CALLRETMAP