Διάλεξη 06 - Ακολουθιακά Κυκλώματα - Μανδαλωτές Και...
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Transcript of Διάλεξη 06 - Ακολουθιακά Κυκλώματα - Μανδαλωτές Και...
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6
: Flip-Flop
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2008
SR Latch
JK Flip-Flop
D Flip-Flop
Timing Definitions
Latch vs Flip-Flop
2
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2008
3
: Flip-Flop
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2008
.
. .
4
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2008
(=)
5
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2008
()
()
(milliseconds)
6
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2008
7
: Flip-Flop
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2008
(latch )
8
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2008
9
A, C
1. B
,
B, ,
,
A C
Vi2 Vo2 Vo1 Vi1
cascaded inverters
A
Vi1 = Vo2
C
B
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2008
Latches vs Flip-Flops
10
(Latches) level sensitive
( ) high ( low) - transparent mode
() low ( high) - hold mode
Flip-Flops (edge-triggered)
edge sensitive positive edge-triggered: 0 1
negative edge-triggered: 1 0
latches (.., master-slave flip-flops)
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2008
SR Latch
11
: Flip-Flop
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2008
SR Latch NOR
NOR latch
S=R=1 , S, R
Active High ( high
S,R Set, Reset)
12
0Q Q
R S Qn+1 ! Qn+1
0 0 Qn !Qn Memory
0 1 1 0 Set
1 0 0 1 Reset
1 1 0 0 Not allowed
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2008
SR Latch
13
QQ'=11
QQ'=00
R, S
01 10
SR=00 SR=00
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
SR=10
SR=01
SR=00 SR=10
SR=00 SR=01
SR=11 SR=11
SR=01 SR=10
SR=11
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2008
SR Latch
14
Reset Hold Set Set Reset Race
R
S
Q
\Q
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2008
SR Latch NAND
S=R=0 , S,R
Active Low (
S, R)
15
1Q Q
S R Qn+1 ! Qn+1
1 1 Qn !Qn Memory
0 1 1 0 Set
1 0 0 1 Reset
0 0 1 1 Not allowed
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2008
SR Latch (1)
16
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2008
SR Latch (2)
17
R=S=1, R, S
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2008
SR Latch (3)
18
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2008
SR Latch (4)
19
CMOS clocked SR flip-flop clock signal f
W/L Q5, Q6
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2008
SR Latch (5)
20
CMOS clocked SR flip-flop. random-access memory (SRAM) chips
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2008
JK Flip-Flop
21
: Flip-Flop
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2008
JK Latch
J = clocked-set , K=clocked-reset
Active High
, Clock=high
Clock=low ( )
SR latch S=R=0 (NAND )
J=K=1
latch ( ) ,
NAND ,
J, K T Flip-Flop
(Toggle)
22
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2008
JK Flip-Flop
JK latch clock high, ,
latch
!
flip-flop
,
edge-triggered
Master-Slave
: edge-triggered
register ()
23
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2008
Race (around) Problem in Latch-based designs
24
Q
Qf
D
1
t
t
tloo p
f
Signal can race around during f = 1
0 1 clock=high < tloop (propagation delay loop)
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2008
Master-Slave JK Flip-Flop
master , slave
( )
( )
preset (SD) reset (RD) flip-flop.
active low, low
25
:
Clock high: master latch
transparent mode (
)
slave hold mode (
low
)
Clock low: master latch
hold mode slave
transparent mode
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2008
Master-Slave JK Flip-Flop
Master-Slave :
high, slave latch
(
master latch)
low, master latch J, K
( slave latch
master latch,
)
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: high to low Master-Slave level-sensitive latches flip-flop edge-triggered
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2008
Ones catching
slave reset, clock high
NAND , J K
spike glitch (
J, K) J master latch set
reset latch , K
J 1 slave clock
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NAND SR latch, ones catching master slave JK FF :
high ( ) () JK edge-triggered
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2008
Edge-Triggered
28
f
I n XN 2
N 1
O u t
f
In
X
O u t
tp L H
= M ono-Stab le M ulti-V ib ra tor
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2008
JK Edge-Triggered Flip-Flop
high, J, K S, R latch
NAND
low, J, K NAND
level sensitive
29
FF
low ,
J, K (
setup)
S
R , J, K
latch
( . CK=low )
NAND gates 1
2 NAND
0 SR latch
1, 1
Q, Q.
spikes
J, K setup
> edge-triggered
, negative edge-triggered
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2008
Timing Definitions
30
t
CLK
t
D
tC-Q
t hold t su
t
Q OUTPUT STABLE
DATA STABLE
D
Clk
Q
edge-triggered tsetup: (
)
thold:
tC-Q: worst case ( ) D Q
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2008
Flip-Flops
31
QJ
KQ
f
T
f
QJ
KQ
ff
D
Q
Qf
T Q
Qf
D
Toggle Flip -F lop D elay F lip -F lop
J= K . Q clock - . 0 1
D F-F clock
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2008
D Flip-Flop
32
: Flip-Flop
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2008
D Flip-Flop
D S, R latch
Q D ( )
positive edge-triggered
level sensitive (transparent) latch
: JK latch transparent D latch
33
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2008
D latch
C=1
1 on 2 off
D . Q D (transparent)
C=0
1 off 2 on
D
, , 2
CMOS
Level-Sensitive : transparent mode C=1 -
34
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2008
Master-Slave D Flip-Flop
edge-triggered master-slave
C=1
TG 1,4 on 2,3 off ( a)
C=0
TG 1,4 off 2,3 on ( b)
D
2
D
D
3
( )
Q D
C=1
35
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2008
Master-Slave D Flip-Flop- overlapping clocks
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f
f
f
f D
InA
B
f
f
O verlapping C locks C an C ause
R ace C onditions
U ndefined S ignals
, . high
= In
In master slave flip-flops F-F race conditions
clock generation (. )
propagation delays clock routing network (clock skew)
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2008
Master-Slave D Flip-Flop 2 phase non-
overlapping clocks
37
f
f
f
f D
In
f
f
tf 12
o 2 non overlapping clocks t12 clock routing delays.
t12 master-slave FFs , In
FFs inverters=pseuodostatic latch
To t12 FFs leakage ( ( t12
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2008
2-phase dynamic flip-flop
38
ff
DIn
Input Sam pled
O utput Enable
f
f
- refreshing ( 6 transistors- pipelined data paths register files DSP microprocessors) : 2 clocks 4 complementary transmission gates
chip,t12 = die (chip)
t12
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2008
Master-Slave D Flip-Flop
CMOS Master-Slave D Flip-Flop
( )
39
CLK=0, TG1, TG4=ON &TG2, TG3=OFF, Master slave, slave F-F ( F-F ) , master F-F CLK=1, TG1, TG4=OFF &TG2, TG3=ON, Master D ( D ), slave D master : Q D clock (C) (C=1)
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D Flip-Flop
Positive edge-triggered D Flip-Flop TTL ( NAND )
:
40
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2008
Latch vs Flip-Flop
41
: Flip-Flop
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2008
Latches vs Flip-Flops
42
(Latches) level sensitive
( ) high ( low) - transparent mode
() low ( high) - hold mode
Flip-Flops (edge-triggered)
edge sensitive positive edge-triggered: 0 1
negative edge-triggered: 1 0
latches (.., master-slave flip-flops)
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2008
Latches vs Flip-Flops
43
latch, flip-flop register
latch level sensitive
register () edge-triggered
flip-flop edge-triggered
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2008
Latches vs Flip-Flops
44
Latch
low
D
Clk
Q D
Clk
Q
Register (positive edge-triggered)
Clk Clk
D D
Q Q
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2008
Latches vs Flip-Flops
45
positive edge-triggered
flip-flop
transparent (level-sensitive)
latch
D
Clk
Qedge
Qlatch
high
D
Clk
Q
D
Clk
Q
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2008
Latches vs Flip-Flops
46
Unclocked latch propagation delay
Level-sensitive latch Clock high (Tsu/Th
)
propagation delay
( )
Master-slave flip-flop Clock high (Tsu/Th
)
propagation delay
Negative edge-triggered
flip-flop
High-to-low
(Tsu/Th
)
propagation delay
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2008
47
: Flip-Flop
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2008
1 ( )
48
CMOS
5V VIH VIL 2.42 2.0 V
0.4 4.6 V .
.
,
.
; ;
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2008
1-
49
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2008
1-
50
100
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2008
2
51
SR flip-flop VDD=5V, VT=1V K1=K2=K3=K4=K. K5=K6 flip-flop VDD/2.
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2008
2
52
1=3=2=4 latch VDD/2=2.5V. Q high (VDD) low. Q3 VGS=-5V. Q5 Q 2.5V latch .
Q3 ,Q5 Q2 , Q1, Q4 Q6
K5(2(VGS5 VT)VDS5-V2
DS5) = K3(2(VGS3 VT)VDS3-V2
DS3)
5 (2(5-1)2.5- 2.52) = 3 (2(5-1)2.5- 2.52)
5=3
:
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2008
2.1-
53
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2008
2.1-
54
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2008
2.1-
55
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2008
3
56
A: Clk, J, K JK master-slave flip-flop 24. FF (Reset), Q master slave latches.
Q: To master latch Clk high. , master latch , Clk=high J slave. master latch Clk=high. master latch slave Clk. master slave latch :
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2008
4
57
JK edge-
triggered flip-flop .
flip-flop (Set).
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2008
4
58
JK edge-triggered flip-flop
J K Clk.
:
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2008
5
D flip-flop 30 1
6.
() Clk=D=Low S=R=High,
.
flip-flop .
() () CLK=High.
59
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2008
5
60
() Clk=D=Low G2, G3 G4 1 .
G1 1 0. To latch
1 ,
G5=1 G6=0.
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2008
5
61
() D=0 G4=1. E flip-flop
, G6 1 G3=1.
G2 0
G1 1 G5 1.
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2008
E II
2008
62
,
&
& ,
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2008
Back-up Slides
63
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2008
SR Latch
64
4 ( )
4 ,
SR=11 SR flip-flop NOR
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
SR=00 SR=11 SR=00
SR=10
SR=01
SR=00 SR=10
SR=00 SR=01
SR=11 SR=11
SR=10 SR=01
SR=01 SR=10
SR=11
00 11
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2008
SR Latch
65
QQ'=11 R, S
01 10
SR=00 SR=00
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
SR=10
SR=01
SR=00 SR=10
SR=00 SR=01
SR=11 SR=11
SR=01 SR=10
SR=11
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2008
Timing Definitions
66
: Flip-Flop
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2008
Timing Definitions
67
t
CLK
t
D
tC-Q
t hold t su
t
Q OUTPUT STABLE
DATA STABLE
D
Clk
Q
edge-triggered tsetup: (
)
thold:
tC-Q: worst case ( ) D Q