Post on 06-Jul-2018
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IntroductionIntroduction
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Introduction and Basic ConceptIntroduction and Basic Concept
• What is Verilog?
– Hardware Description Language(HDL)
• Why use Verilog?
– Because 60 o! "# co$panies use it%
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Why Verilog?Why Verilog?• Why use an HDL?
– Descri&e co$ple' designs ($illions o! gates)
– nput to synthesis tools (synthesia&le su&set)
– Design e'ploration with si$ulation
• Why not use a general purpose language
– #upport !or structure and instantiation
– #upport !or descri&ing &it*le+el &eha+ior
– #upport !or ti$ing
– #upport !or concurrency
• Verilog +s% VHDL
– Verilog is relati+ely si$ple and close to ,
– VHDL is co$ple' and close to -da
– Verilog has 60 o! the world digital design $ar.et (larger share in "#)
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Why Verilog?Why Verilog?
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Why Verilog?Why Verilog?
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Verilog HDL and Verilog-XLVerilog HDL and Verilog-XL
• Verilog HDL
– Hardware design language that allows you todesign circuit.
• Verilog-XL
– High speed, eent-drien si!ulator that reads
Verilog HDL and si!ulates the "ehaior o#
hardware.
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Synthesis
Place andRoute
clb 1clb 2
Always inst1 inst2 inst3
$odern %ro&ect $ethodology$odern %ro&ect $ethodology
m a p
p i n g
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Introduction toIntroduction to
Verilog onlyVerilog only• '"&ecties
– (nderstand the design !ethodologies!ethodologies using Verilog• )arget audience
– hae "asic digital circuits design concept
– *nowledge o# VHDL #or design o# digital syste!s – Verilog description #or logic synthesis
• +') in the tal*
– a #ull coerage o# Verilog
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ContentsContents• Verilog HDL
– structured $odeling
– /L $odeling
• 1'a$ple co$&inational circuits – structured description (net*list)
– /L
• 1'a$ple se2uential circuits
– /L• 3#4
– co$&inational circuits
– se2uential circuits
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Verilog historyVerilog history
• ateway Design uto!ation
– %hil $oor"y in /01 and /02
• Verilog-XL, 3XL algorith!3, /04
– a ery e##icient !ethod #or doing gate-leel si!ulation
• Verilog logic synthesi5er, 6ynopsys, /00
– the top-down design !ethodology is #easi"le
• Cadence Design 6yste!s ac7uired ateway
– Dece!"er /0/
– a proprietary HDL
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• 'pen Verilog International 8'VI9, //
– Language :e#erence $anual 8L:$9
– !a*ing the language speci#ication as endor-
independent as possi"le.
• )he I;;;
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Hardware Description LanguagesHardware Description Languages
• he !unctionality o! hardware
– concurrency
– ti$ing controls
• he i$ple$entation o! hardware
– structure
– net*list
• #5
– ,% ordon Bell and -lan 7ewell at ,arnegie 4ellon
"ni+ersity8 9:;<
– /L (register trans!er le+el)
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Di##erent Leels o# "stractionDi##erent Leels o# "straction
• -lgorith$ic – the !unction o! the syste$
• /L
– the data !low – the control signals
– the storage ele$ent and cloc.
• ate – gate*le+el net*list
• #witch
– transistor*le+el net*list
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Verilog #or Digital 6yste! DesignVerilog #or Digital 6yste! Design
• #tructural description – net*list using pri$iti+e gates and switches
– continuous assign$ent using Verilog operators
• /L
– !unctional description
– ti$ing controls and concurrency speci!ication
– procedural &loc.s (always and initial)
– registers and latches
• , = ti$ing controls = concurrency
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Verilog %roceduralVerilog %rocedural
DescriptionsDescriptions
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Verilog Varia"lesVerilog Varia"les
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)ric*y Delay)ric*y Delay
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Initial Bloc* Initial Bloc*
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Verilog (sageVerilog (sage
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Di##erent 6tatesDi##erent 6tates
% d l% d l
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%rocedural%rocedural
6tate!ents6tate!ents
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6till a %ro"le!?6till a %ro"le!?
Hi hi l d
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Hierarchical structure andHierarchical structure and
$odules$odules• /epresent the hierarchy o! a design
– $odules
• the &asic &uilding &loc.s
– ports
• the > pins in hardware
• input8 output or inout
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;ent Drien 6i!ulation;ent Drien 6i!ulation• Verilog is really a language !or $odeling e+ent*dri+en syste$s
– 1+ent @ change in state
– #i$ulation starts at t A 0
– 5rocessing e+ents generates new e+ents
– When all e+ents at ti$e t ha+e &een processed si$ulation ti$e ad+ances to t+1
– #i$ulation stops when there are no $ore e+ents in the 2ueue
•••0 t t+1
•••Event
queue
Events
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$odeling 6tructure= $odules$odeling 6tructure= $odules• he $odule is the &asic &uilding &loc. in Verilog
– 4odules can &e interconnected to descri&e the structure o! your digital syste$
– 4odules start with .eyword module and end with .eyword endmodule
– Modules have ports for interconnection with other modules
Module AND
• • •
endmodule
Module CPU
• • •
endmodule
$ d li 6 %
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$odeling 6tructure= %orts$odeling 6tructure= %orts• 4odule 5orts
– #i$ilar to pins on a chip – 5ro+ide a way to co$$unicate with outside world
– 5orts can &e input8 output or inout
i0
i1
o
Module AND (i0, i1, o);input i0, i1;
output o;
endmodule
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Logic ValuesLogic Values
• 0@ ero8 logic low8 !alse8 ground
• 9@ one8 logic high8 power
• C@ un.nown
• @ high i$pedance8 unconnected8 tri*state
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Data )ypesData )ypes• 7ets
– 7ets are physical connections &etween de+ices
– 7ets always re!lect the logic +alue o! the dri+ing de+ice
– 4any types o! nets8 &ut all we care a&out is wire
• /egisters
– $plicit storage – unless +aria&le o! this type is
$odi!ied it retains pre+iously assigned +alue
– Does not necessarily i$ply a hardware register
– /egister type is denoted &y reg
- int is also used
V i "l D l i
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Varia"le DeclarationVaria"le Declaration
• Declaring a netwire [] [*];:ange is speci#ied as [MSb:LSb]. De#ault is one "it wide
• Declaring a registerreg [] [@A
• Declaring !e!oryreg [] [ = endaddr>@A
• ;a!plesreg r; // 1-bit reg variable
wire w1, w2; // 2 1-bit wire variable
reg [7:0] vreg; // 8-bit register
reg [7:0] memory [0:1023]; a 1 KB memory
% d D )% t d D t )
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%orts and Data )ypes%orts and Data )ypes• ,orrect data types !or ports
inout
input output
net net
net
net
Register/net register/net
Module
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6tructural $odeling6tructural $odeling
• #tructural Verilog descri&es connections o!
$odules (netlist)
• and a0(%i0(a)8 %i9(&)8 %o(out))E
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; l
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;a!ple;a!ple• G*&it adder
$odule addG (s8c8ci8a8&)
input I@0J a8& E >> port declarations
input ci E
output I@0J s @ >> +ector
output c E
wire I
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Data typesData types• 7et
– physical wire &etween de+ices
– the de!ault data type
– used in structural $odeling and continuous assign$ent – types o! nets
• wire8 tri @ de!ault
• wor8 trior @ wire*/ed
•wand8 triand @ wire*-7Ded
• trireg @ with capaciti+e storage
• tri9 @ pull high
• tri0 E pull low
• supply9 E power
• supply0 E ground
#i$pler than VHDL
nly #yntactical
Di!!erence
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Verilog 6i!ulatorVerilog 6i!ulator
CircuitDescription
Testfxture
Verilog Simulator
Simulation Result
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6a!ple Design6a!ple Design
module adder ( sum, cout, a, b , ci );
// port declaration
output sum, cout;
input a, b, ci;
reg sum, cout;
// bea!ior description
al"a#s $( a or b or ci )
begin
sum % a ^ b ^ ci;
cout % ( a&b ) ' ( b&ci ) ' ( ci&a);
end
endmodule
bit ull adderab
ci
sum
cout
#i$pler than VHDL
nly #yntactical
Di!!erence
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BasicBasicInstructionsInstructions
i C i i
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Leical Conentions inLeical Conentions in
VerilogVerilog T#pe o lexical to*ens +
-perators ( . )ite space
Comment
0umber ( . )String
1dentifer
2e#"ord ( . ) 0ote + . "ill be
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:eg and %ara!eters:eg and %ara!eters
• /eg
– +aria&les used in /L description
– a wire8 a storage de+ice or a te$porary +aria&le
– reg @ unsigned integer +aria&les o! +arying &it width
– integer @
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6pecial Language )o*ens6pecial Language )o*ens
• Kidenti!ierM@ #yste$ tas.s and !unctions
– Kti$e
– Kstop
– K!inish – K$onitor
– KpsNwa+es
– KgrNwa+es
– KgrNregs
• Odelay speci!icationM
– used in
• gate instances and procedural state$ents
• unnecessary in /L speci!ication
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# ll dd # ll dd
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#ull-adder #ull-adder•
$odule add (co8 s8 a8 &8 c)input a8 & 8c E
output co8 s E
'or (n98 a8 &) E
'or (s8 n98 c) Enand (n
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Verilog %ri!itiesVerilog %ri!ities• Basic logic gates only
– and
– or
– not – &u!
– 'or
– nand – nor
– 'nor
– &u!i!98 &u!i!0
– noti!98 noti!0
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%ri!itie %ins re ;panda"le%ri!itie %ins re ;panda"le
• ne output and +aria&le nu$&er o! inputs
• not and &u!
– +aria&le nu$&er o! outputs &ut only one input
nand (y, in1, in2) ;
nand (y, in1, in2, in3) ;
nand (y, in1, in2, in3, in4) ;
C i i
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Continuous ssign!entsContinuous ssign!ents
• Descri&e co$&inational logic• perands = operators
• Dri+e +alues to a net
– assign out A aF& E >> and gate – assign e2 A (aAA&) E >> co$parator
– wire O90 in+ A Pin E >> in+erter with delay
– wire I;@0J c A a=& E >> Q*&it adder
• -+oid logic loops
– assign a A & = a E
– asynchronous design
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Logical and Conditional 'peratorsLogical and Conditional 'perators
• Logical8 &it*wise and unary operators
a A 9099E & A 0090
logical &it*wise unary
a RR & A 9 a R & A 9099 Ra A 9
a FF & A 9 a F& A 0090 Fa A 0
• ,onditional operator
assign A (Ss98s0T AA
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'perators'perators
{}Concatenations
?:Conditional Operators>>,
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'perator %recedence'perator %recedenceI J &it*select or part*
select
( ) parentheses
8 P logical and &it*wise
negation
F8 R8 PF8 PR8 8 P8 P
reduction operators
=8 * unary arith$etic
S T concatenation
X8 >8 arith$etic
=8 * arith$etic
8 MM shi!t
M8 MA8 8 A
relational
AA8 A logical e2uality
F &it*wise -7D
8 P8 P
&it*wise C/ and C7/
R &it*wise /
FF logical -7DRR logical /
? @ conditional
' t' t
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'perators'peratorsS T concatenation
= * X >
arith$etic
$odulus
M MA A
relational
logical 7
FF logical -7DRR logical /
AA logical e2uality
A logical ine2uality
? @ conditional
P &it*wise 7
F &it*wise -7D
R &it*wise /
&it*wise C/
P P &it*wise C7/
F reduction -7D
R reduction /
PF reduction 7-7D
PR reduction 7/
reduction C/
P P reduction C7/
shi!t le!t
MM shi!t right
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+u!"ers+u!"ersFormat : ’
!ample : "’d1#
"’h1$
"’b$$$1$$$$
"’o2$
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EeywordsEeywords
8ote : 6ll 9eyords are de!ined in loer case
0a7ples :
module, endmodule
input, output, inout
reg, integer, real, time
not, and, nand, or, nor, xorparameter
begin, end
or*, 3oin
speci#, endspeci#
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$a&or Data )ype Class$a&or Data )ype Class
0ets
Registers
:arameters
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+ets+etsNet data t#pe represent p#sicalconnections bet"een structuralentities
< net must be dri!en b# a dri!er,
suc as a gate or a continuousassignment
Verilog automaticall# propagates ne"
!alues onto a net "en te dri!ers
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:egisters F %ara!eters:egisters F %ara!eters
Registers represent abstract storageelements
< register olds its !alue until a ne"!alue is assigned to it
Registers are used extensi!el# in
bea!ior modeling and in appl#ingstimuli
Parameters are not !ariables, te# are
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ssign!entsssign!ents
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ssign!ents 8 cont. 9ssign!ents 8 cont. 9
Eloc*ing procedural assignment
rega % regb F regc;0onbloc*ing procedural assignment
rega % regb . regc;
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:)L:)L
$odeling$odeling
i:)L $ d li
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:)L $odeling:)L $odeling• Descri&e the syste$ at a high le+el o! a&straction
• #peci!y a set o! concurrently acti+e procedural &loc.s – procedural &loc.s A digital circuits
• 5rocedural &loc.s – initial &loc.s
• test*!i'tures to generate test +ectors• initial conditions
– always &loc.s• can &e co$&inational circuits
• can i$ply latches or !lip*!lops
%rocedural "loc*s hae the #ollowing%rocedural "loc*s hae the #ollowing
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%rocedural "loc*s hae the #ollowing%rocedural "loc*s hae the #ollowing
co!ponentsco!ponents
• procedural assign$ent state$ents
• ti$ing controls
• high*le+el progra$$ing language constructs
initial c
c state7ent
c <
c <
c
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:)L 6tate!ents:)L 6tate!ents – 5rocedural and /L assign$ents
• reg F integer
• out A a = & E
– &egin % % % end &loc. state$ents• group state$ents
– i!% % % else state$ents
– case state$ents
– !or loops
– while loops – !ore+er loops
– disa&le state$ents• disa&le a na$ed &loc.
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6 ti l l Bl *6e7uential lways Bloc*s
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6e7uential lways Bloc*s6e7uential lways Bloc*s
• n!erred latches (nco$plete &ranch speci!ications)$odule in!erNlatch(D8 ena&le8 Z)E
input D8 ena&leE
output ZE
reg ZE
always Y (D or ena&le) &egin
i! (ena&le)
Z A DE
end
end$odule
– the Z is not speci!ied in a &ranch
• a latch li.e ;G;
C "i ti l Ci it D iCo!"inational Circuit Design
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Co!"inational Circuit DesignCo!"inational Circuit Design• utputs are !unctions o! inputs
• 1'a$ples
– 4"C
– decoder – priority encoder
– adder
co$&%
circuits
inputs utputs
$ ltiple or$ultipleor
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$ultipleor$ultipleor• 7et*list (gate*le+el)
$odule $u'
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$ lti l$ lti l
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$ultipleor$ultipleor• G*to*9 $ultiple'or
$odule $u'GN9 (out8 in08 in98 in
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$odule $u'GN9 (out8 in8 sel) E
output out E input I@0J in E
input I9@0J sel E
reg out E
always Y(sel or in) &egin
case(sel)
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DecoderDecoder• *to Q decoder with an
ena&le control$odule decoder(o8en&N8sel) E
output I;@0J o Einput en&N E
input I
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%riority ;ncoder%riority ;ncoderalways Y (d0 or d9 or d< or d)
i! (d AA 9)
S'8y8+T A [&999 E
else i! (d< AA 9)
S'8y8+T A [&909 E
else i! (d9 AA 9)
S'8y8+T A [&099 E
else i! (d0 AA 9)
S'8y8+T A [&009 E
else
S'8y8+T A [&''0 E
%arity Chec*er%arity Chec*er
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%arity Chec*er%arity Chec*er$odule parityNch.(data8 parity)E input I0@;J dataE
output parityE
reg parityE
always Y (data)
&egin@ chec.Nparity
reg partialE
integer nE
partial A dataI0JE !or ( n A 0E n A ;E n A n = 9)
&egin
partial A partial dataInJE
end parity A partialE
end
end$odule
dderdder
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dderdder
• /L $odeling$odule adder(c8s8a8&) E
output c E
output I;@0J s Einput I;@0J a8& E
assign Sc8sT A a = & E
end$odule
• Logic synthesis
– ,L- adder !or speed opti$iation
– ripple adder !or area opti$iation
)ri 6tate)ri 6tate
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)ri-6tate)ri-6tate• he +alue
always Y (sela or a)
i! (sela)out A a E
elseout A 9[& E
• -nother &loc. always Y(sel& or &)
i!(sel&)out A& E
else
out A 9[& E
assi.n ot / (sela)? a: 1= ;
:egisters 8Glip #lops9 are i!plied:egisters 8Glip #lops9 are i!plied
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:egisters 8Glip-#lops9 are i!plied:egisters 8Glip-#lops9 are i!plied
– Y(posedge cl.) or Y(negedge cl.)
– a positi+e edge*triggered D !lip*!lopalways Y (posedge cl.)
2 A d E
%rocedural ssign!ents%rocedural ssign!ents
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%rocedural ssign!ents%rocedural ssign!ents
• Bloc.ing assign$entsalways Y(posedge cl.) &egin
rega A data E
reg& A rega Eend
• 7on*&loc.ing assign$entsalways Y(posedge cl.) &egin
regc A data E
regd A regc E
end
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6e7uential6e7uentialCircuitCircuitDesignDesign
6e7uential Circuit Design6e7uential Circuit Design
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6e7uential Circuit Design6e7uential Circuit Design
– a !eed&ac. path – the state o! the se2uential circuits
– the state transition synchronous circuits
asynchronous circuits
4e$ory
ele$ents
,o$&inational
circuit
nputs utputs
Ginite 6tate $achineGinite 6tate $achine
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Ginite 6tate $achineGinite 6tate $achine• 4oore $odel
• 4ealy $odel
co$&%
circuit
inputs$e$ory
ele$ents
ne't
state co$&%
circuitoutputs
current
state
co$&%
circuit
inputs$e$ory
ele$ents
ne'tstate co$&%
circuitoutputs
currentstate
;a!ples;a!ples
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;a!ples;a!ples
– D !lip*!lop
– D latch
– register – shi!ter
– counter
– pipeline – 3#4
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:egister:egister
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:egister:egister!odule register 87,d,cl*,clr, set9 A
output =J@ 7 A
input =J@ d A
input cl*,clr, set A
reg =J@ 7 Aalways K 8posedge cl* or negedge clr or negedge set9
i# 8clr9
7 M J A
else i# 8set9
7 M 0N" A
else
7 M d A
end!odule
D LatchesD Latches
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D LatchesD Latches• D latch
always Y (ena&le or data)
i! (ena&le)
2 A data E
• D latch with gated asynchronous dataalways Y (ena&le or data or gate)
i! (ena&le)
2 A data F gate E
D LatchesD Latches
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• D latch with gated Oena"leNalways K 8ena"le or d or gate9
i# 8ena"le F gate9
7 M d A
• D latch with asynchronous resetalways K 8reset or data or gate9
i# 8reset9
7 M N"J
else i#8ena"le9
7 M data A
D LatchesD Latches
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Concept o# G6$ in VerilogConcept o# G6$ in Verilog
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Concept o# G6$ in VerilogConcept o# G6$ in Verilog
Vending $achine ;a!pleVending $achine ;a!ple
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Vending $achine ;a!pleVending $achine ;a!ple
%arity Chec*er ;a!ple%arity Chec*er ;a!ple
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%arity Chec*er ;a!ple%arity Chec*er ;a!ple
6hi#ter6hi#ter
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6hi#ter6hi#ter$odule shi!ter (so8si8d8cl.8ldN8clrN) E
output so E
input I;@0J d E
input si8cl.8ldN8clrN E >> asynchronous clear and synchronous load
reg I;@0J 2 E
assign so A 2I;J E
always Y (posedge cl. or negedge clrN)
i! (PclrN)
2 A 0 E
else i! (PldN)
2 A d E else
2I;@0J A S2I6@0J8siT E
end$odule
shi!ter socl. si
dldN
CounterCounter
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CounterCounter$odule &cdNcounter(count8rippleNout8clr8cl.) E
output I@0J count E
output rippleNout E
reg I@0J count E
input clr8cl. E
wire rippleNout A (count AA GU&9009) ? 0@9 E >> co$&inational
always Y (posedge cl. or posedge clr) >> co$&inational = se2uential
i! (clr) E
count A 0 E
else i! (count AA GU&9009)
count A 0 Eelse
count A count = 9 E
end$odule
$e!ory$e!ory
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$e!ory$e!ory$odule $e$ory (data8 addr8 read8 write)E
input read8 writeE
input IG@0J addrE
inout I;@0J dataE
reg I;@0J dataNregE
reg I;@0J $e$ory I0@QUh!!JE
para$eter loadN!ile A \cput9%t't\E
assign data A (read) ? $e$ory IaddrJ @ QUhE
always Y (posedge write)$e$oryIaddrJ A dataE
initial
Kread$e$& (loadN!ile8 $e$ory)E
end$odule
Ine##icient DescriptionIne##icient Description
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Ine##icient DescriptionIne##icient Description
$odule count (cloc.8 reset8 andN&its8 orN&its8 'orN&its)Einput cloc.8 resetE
output andN&its8 orN&its8 'orN&itsE
reg andN&its8 orN&its8 'orN&itsE
reg I
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6i i!plied registers6i i!plied registers
;##icient Description;##icient Description
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;##icient Descriptionc e esc p o
$odule count (cloc.8 reset8andN&its8 orN&its8 'orN&its)E
input cloc.8 resetE
output andN&its8 orN&its8 'orN&itsE
reg andN&its8 orN&its8 'orN&itsEreg I> co$&inational circuits
always Y(count) &egin
andN&its A F countE
orN&its A R countE'orN&its A countE
end
end$odule
#eparate co$&inational and se2uential circuits#eparate co$&inational and se2uential circuits
)hree registers are used)hree registers are used
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)hree registers are used)hree registers are used
$ealy $achine ;a!ple$ealy $achine ;a!ple
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$ealy $achine ;a!ple$ealy $achine ;a!ple$odule $ealy (in98 in> co$&inational@ ne't*state and outputs
always Y(in9 or in< or currentNstate)
case (currentNstate)
0@ &egin
ne'tNstate A 9Eout A 9U&0E
end
9@ i! (in9) &egin
ne'tNstate A 9U&0E
out A in
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%ipelines%ipelines
• -n e'a$ple
assign nNsu$ A a=&assign p A su$ X dNc
>> plus D !lip*!lops
always Y (posedge cl.)
su$ A n su$ E
!lip*
!lops
co$&%
circuits
!lip*
!lops
co$&%
circuits
!lip*
!lops
co$&%
circuits
D!!
D!!
D!!
a
&
c
out
n*su$
su$
dNc
p
G6$ ;a!ple G6$ ;a!ple
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ra!!ic Light ,ontroller
@ictre o! Ai.ayBar7road ntersection:
%igh&ay
%igh&ay
Farmroad
Farmroad
%'
%'
F'
F'
(
(
G6$ ;a!ple G6$ ;a!ple
6peci#ications6peci#ications
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ra!!ic Light ,ontroller
? Dalation o! npts and Otpts:
Input Signal resetCDSD-
Output Signal AE, AF, A'BE, BF, B'SD
Descriptionplace BSG in initial statedetect Heicle on !ar7roadsort ti7e interHal epiredlon. ti7e interHal epired
Descriptionassert .reenyellored i.ay li.tsassert .reenyellored !ar7road li.tsstart ti7in. a sort or lon. interHal
? Dalation o! &nie States: So7e li.t con!i.ration i7ply otersStateSIS1S2S3
DescriptionAi.ay .reen (!ar7road red)Ai.ay yello (!ar7road red)Bar7road .reen (i.ay red)Bar7road yello (i.ay red)
6peci#ications6peci#ications
)he "loc* diagra!)he "loc* diagra!
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)he "loc* diagra!)he "loc* diagra!
L
33[s,o$&%
circuits
,o$&%
circuits
statenNstate,
#
H/
H
H]
3/
3
3]
State transition diagramState transition diagram
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gg
SI: AE
S1: AF
S2: BE
S3: BF
Reset
)' * (
S$
)'+(,S)
)S
S1 S-
S2
)S,S)
)S,S)
)' * (,S)
)S
)' + (
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>> !lip*!lops
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>> !lip !lops
alwaysY (posedge cl. or posedge reset)
i!(reset) >> an asynchronous reset &egin
state A #0 E
#No A 0 E
endelse
&egin
state A ne'tNstate E
#No A # E
end
alwaysY (state or c or tl or ts)
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y Y ( )
case(state) >> state transition
#0@
i!(tl F c)
&egin
ne'tNstate A #9 E
# A 9 E end
else
&egin
ne'tNstate A #0 E# A 0 E
end
Reset
)' * (
S$
)'+(,S)
)S
S1 S-
S2
)S,S)
)S,S)
)' * (,S)
)S
)' + (
#9@
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i! (ts) &egin
ne'tNstate A #< E
# A 9 E
end
else &egin
ne'tNstate A #9 E
# A 0 E
end
#
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;##icient $odeling;##icient $odeling
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)echni7ues)echni7ues• #eparate co$&inational and se2uential
circuits
– always .now your target circuits• #eparate structured circuits and rando$ logic
– structured@ data path8 C/s8 4"Cs
– rando$ logic@ control logic8 decoder8 encoder
• "se parentheses control co$ple' structure
•
VV;:IL' Coding 6tyles;:IL' Coding 6tyles
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VV;:IL' Coding 6tyles;:IL' Coding 6tyles
#ynthesia&le
Beha+ioral
/egister rans!er Le+el (/L)
#tructural
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Conditional InstructionsConditional Instructions
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if ()
else
case ()
expr1: ;
expr2: ;
default: ;endcase;
casez ( considered don’t care)
casex ( and C considered don’t care)
(expression)?(true):(false)
if (a2:!"##3$%!1! && cy)
'''
case (ir:")$%!!!1: '''
$%!!1!: '''
default: '''endcase;
casex (ir:")
$%xx!1: '''
$%xx1!: '''default: '''
endcase;
acc#(ir:!"##$%!!11) ?
!:2**;
LoopsLoops
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Loopsp
for (;;)
;
w,ile ();
repeat ()
;
fore-er ;
for (i#!;i
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6u"routines
task multiplyinput [15:0] a, b;output [31:0] prod; begin...end
endtask
function [1:0] testD;input [1:0] Duab, D!ab; begin
...testD"#$b01;end
endfunction
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Behaior= Verilog 'peratorsBehaior= Verilog 'perators
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Behaior= Verilog 'peratorsg p
-rith$etic@ =8 A 8 X8 >8
Binary &itwise@ P8 F8 R8 8 P
"nary reduction@ F8 PF8 R8 PR8 8 P
Logical@ 8 FF8 RR8 AA8 AAA8 A8 AA
AA returns x i! any o! the input &its is x or z
AAA co$pares xs and zs
/elational@ % M8 A8 M=Logical shi!t@ MM8
,onditional@ ?@
,oncatenation@ ST
Behaior=Continuous ssign!entBehaior=Continuous ssign!ent
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,ontinually dri+e
wire +aria&les
"sed to $odel
co$&inational logic
or $a.e
connections
&etween wires
Module half_adder(x, y, s, c)input x, y;output s, c;
assign s = x ^ y;assign c = x & y;
endmodule
Module adder_4(a, b, ci, s, co)input [3:0] a, b;input ci;output [3:0]s;
output co;
assign {co, s} = a + b + ci;
endmodule
Behaior= Initial and lwaysBehaior= Initial and lways
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• 4ultiple state$ents per &loc. 5rocedural assign$ents
i$ing control• nitial &loc.s e'ecute once• at t = 0• -lways &loc.s e'ecute continuously• at t = 0 and repeatedly thereafter
initialbegin
• • •
end
alwaysbegin
• • •
end
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Behaior=)i!ing ControlBehaior=)i!ing Control
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• Delay #
"sed to delay state$ent &y speci!ied a$ount o! si$ulation ti$e
• 1+ent ,ontrol @
Delay e'ecution until e+ent occurs
1+ent $ay &e single signal>e'pression change
4ultiple e+ents lin.ed &y or
alwaysbegin
#10 clk = 1;#10 clk = 0;
end
always @(posedge clk)begin
q
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• If, If-Else
• ,ase
,ould also use casez (treats as don[t cares ) and casex ( treats and ' as don[t cares)
if (branch_flg) begin
PC = PCbr; end else
PC = PC + 4;
case(opcode)6’b001010: read_mem = 1;6’b100011: alu_add = 1;default:
begin$display (“Unknown opcode %h”, opcode);
endendcase
Behaior= Loop 6tate!entsBehaior= Loop 6tate!ents• Repeat
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Repeat
• While
• For
i = 0;repeat (10) begin
i = i + 1;$display( “i = %d”, i);
end
i = 0;while (i < 10) begin
i = i + 1;$display( “i = %d”, i);
end
for (i = 0; i < 10; i = i + 1) begin
i = i + 1;$display( “i = %d”, i);
end
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Verilog Coding :ules= 6e7uentialVerilog Coding :ules= 6e7uentialBloc*sBloc*s
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Bloc*sBloc*s
always @(posedge clk)begin
q = d;end
always @(posedge clk)begin
q1 = q;end
always @(posedge clk)begin
q
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coding rulescoding rules* -lways .eep in $ind what sort o! i$ple$entation your design could $ap to% !
you don[t .now8 chances are synthesis doesn[t either%
* he only allowed storage is instantiated d!!
* 7o always Y posedge state$ents
* 7o case state$ents without de!ault case* 7o i! state$ents without an else case
* ! you assign to a net in one case it $ust &e assigned to in all cases (no i$plicit storage)
* 7o loops
* 7o initial &loc.s
* Li$ited operators
* = and – are the only arith$etic operators allowed
* ry to a+oid relational operators (M8 AA) in !a+or o! si$pler logic
* "se assign state$ents when possi&le
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VerilogVerilog;a!ple= 6$;a!ple= 6$
i d l e
$1
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;a!ple= 6$;a!ple= 6$
ChartChart
i n p u t $
s 1
i n p u t
s 2
i n p u t
s -
i n p u t
1
$ 1
1$
1 $
s -
o u t p u t
i n p u t1 $
Want to match pattern1011
Verilog ;a!ple 8cont9Verilog ;a!ple 8cont9
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Verilog ;a!ple 8cont9Verilog ;a!ple 8cont9 module se%uence &data'n, found, clock, reset(;
))'nput and *utput Declarations input data'n; input clock; input reset; output found;
reg found;
))Data'nternal +ariables reg [3:0] state; reg [3:0] net-state; ire found-comb;
))/tate Declarations parameter idle " b0001; parameter s1 " b0010; parameter s# " b0100; parameter s3 " b1000;
))2et /tate ogicalays 4&state or data'n( case &state( idle:
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VerilogVerilog;a!ple;a!ple
if &data'n(net-state " s1;
else
net-state " idle; s1: if &data'n(
net-state " s1; else
net-state " s#;
s#: if &data'n(net-state " s3;
elsenet-state " idle;
s3: if &data'n(
net-state " s1; else
net-state " s#; default: net-state " idle; endcase )) case&state(
))/tate ransitionalays 4&posedge clock(if &reset "" 1(
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VerilogVerilog
;a!ple;a!ple
if &reset "" 1( state 6" idle; else
state 6" net-state;
))*utput ogicassign found-comb " &state[3] 7 data'n(;
))8egister *utput ogicalays 4&posedge clock( if &reset "" 1( found 6" 0; else found 6" found-comb;
endmodule )) se%uence
Verilog ;a!ple =Verilog ;a!ple =
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Verilog ;a!ple =g p
6i!ulation6i!ulation
Verilog ;a!ple= 6ynthesisVerilog ;a!ple= 6ynthesis
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• op Le+el
• echnology +iew (-ltera 90_)
Verilog ;a!ple Xilin GoundationVerilog ;a!ple Xilin Goundation
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Verilog ;a!ple Xilin GoundationVerilog ;a!ple Xilin Goundation
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Binary $ultiplier ;a!pleBinary $ultiplier ;a!ple
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Register B
Shift register A Shift register QC
AdderCout
IN
0
OUT
product
multiplicand
multiplier
Counter P
n-1
Behaioral !odelingBehaioral !odeling
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-earnin. eaHioral 7odelin. y eplorin. so7e ea7ples
DGG
Din
Cloc*
Dout
Reset
module DGG ( Din, Dout, Cloc*, Reset );
output Dout;
input Din, Cloc*, Reset;
reg Dout;al"a#s $( negedge Reset or posedgeCloc* )
begin
i ( HReset )
Dout % 6b5;
else
Dout % Din;
end
Behaioral !odeling 8 cont. 9Behaioral !odeling 8 cont. 9
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outIJ7
sel
9
9
i5
i
iB
iK
Bmodule IJ79 ( out, i5, i, iB, iK, sel );
output LK+5M out;
input LK+5M i5, i, iB, iK;
input L+5M sel;
assign out % ( sel %% B6b55 ) N i5 +
( sel %% B6b5 ) N i +
( sel %% B6b5 ) N iB + ( sel %% B6b ) N iK +
96bx;
endmodule
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$odule Instantiation$odule Instantiation
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out
out< E
Top
i5
iout
Data5
a
a5 b5
b
Data
DataB
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• Verilog@wire alid # 1 & 4lle0al;
wire alid25c,ed # 5c,ed6reeze+ & (alid+7 8 alid);
wire 19:!" in4das1 # 1=%1
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parameter 'D9#! /9-*8/#1 /9-9 # 5BD+F@5;
F@5 # 1; end
else if (AA+H@DDC & F@5+H@DDC &
4C@DB5+H@DDC)
'''
!odules!odules
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module e0d(J 7load cl);
parameter C # .;input CK1:!" J;output CK1:!" 7;
input load l;
alays 4( posedge cl) if (load) J # ALd, 7;
endmodule
module e0d(J 7load cl);
parameter C # .;input CK1:!" J;output CK1:!" 7;
input load l;
alays 4( posedge cl) if (load) J # ALd, 7;
endmodule
e0d re0!(M! d! l cl);
e0d A19 re01(M1 d1 l cl);
e0d re02(M2 d2 l cl);defparam re02'C # ;
e0d re0!(M! d! l cl);
e0d A19 re01(M1 d1 l cl);
e0d re02(M2 d2 l cl);defparam re02'C # ;
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Behaioral 8Q9Behaioral 8Q9
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integer sum i;
integer opcodes 31:!";real a-era0e;
initial
for (i#!; i
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Veri#ication o# Designg
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Di##erencesDi##erences
"etween )as*s"etween )as*s
and Gunctionsand Gunctions
)as*s ersus Gunctions in)as*s ersus Gunctions in
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VerilogVerilog• 5rocedures>#u&routines>3unctions in #W
progra$$ing languages
– he sa$e !unctionality8 in di!!erent places
• Verilog e2ui+alence@
– Tasks and Functions
– "sed in &eha+ioral $odeling
– 5art o! design hierarchy ⇒ Hierarchical na$e
Di##erences "etween...Di##erences "etween...
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• 3unctions
– ,an ena&le (call) ust
another !unction (not tas.)
– 1'ecute in 0 si$ulation ti$e – 7o ti$ing control state$ents
allowed
– -t lease one input
– /eturn only a single +alue
• as.s
– ,an ena&le other tas.s and
!unctions
– 4ay e'ecute in non*erosi$ulation ti$e
– 4ay contain any ti$ing
control state$ents
– 4ay ha+e ar&itrary input8output8 or inouts
– Do not return any +alue
Di##erences "etweenR 8contNd9Di##erences "etweenR 8contNd9
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• Both – are de!ined in a module
– are local to the module
– can ha+e local +aria&les (registers8 &ut not nets) and e+ents
– contain only &eha+ioral state$ents
– do not contain initial or always state$ents
– are called !ro$ initial or always state$ents or other tas.s or
!unctions
Di##erences "etweenR 8contNd9Di##erences "etweenR 8contNd9
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• as.s can &e used !or co$$on Verilog code• 3unction are used when the co$$on code
– is purely co$&inational
– e'ecutes in 0 si$ulation ti$e
– pro+ides e'actly one output
• 3unctions are typically used !or con+ersions and
co$$only used calculations
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)as*s)as*s
)as*s)as*s
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• _eywords@ task, endtask
• 4ust &e used i! the procedure has
– any ti$ing control constructs – ero or $ore than one output argu$ents
– no input argu$ents
)as*s 8contNd9)as*s 8contNd9
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• as. declaration and in+ocation – Declaration synta'
task 6task-nameC;
6')* declarationsC
6!ariable and e!ent declarationsC
begin II if more t,an one statement needed
6statement&s(C
end II if begin used
endtask
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)as* ;a!ples)as* ;a!ples (se o# input and output argu!ents(se o# input and output argu!ents
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module operation; parameter delay " 10;reg [15:0] >, ;reg [15:0] >->2D, >-*8, >-@*8;
initialBmonitor& E(;
initial begin
Eend
alays 4&> or ( begin
bitise-oper&>->2D, >-*8, >-@*8, >, (;
end
task bitise-oper;output [15:0] ab-and, ab-or,
ab-or;input [15:0] a, b; begin Adelay ab-and " a 7 b; ab-or " a F b; ab-or " a G b;end endtask
endmodule
)as* ;a!ples)as* ;a!ples (se o# !odule local aria"les(se o# !odule local aria"les
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module se%uence;
reg clock;
initial
begin
E
end
initial
init-se%uence;
alays
asymmetric-se%uence;
task init-se%uence;
begin
clock " 1b0;
end
endtask
task asymmetric-se%uence;
begin
A1# clock " 1b0;
A5 clock " 1b1;
A3 clock " 1b0; A10 clock " 1b1;
end
endtask
endmodule
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GunctionsGunctions
GunctionsGunctions
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• _eyword@ function, endfunction• ,an &e used i! the procedure
– does not ha+e any ti$ing control constructs
– returns e'actly a single +alue
– has at least one input argu$ent
Gunctions 8contNd9Gunctions 8contNd9
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• 3unction Declaration and n+ocation – Declaration synta'@
function 6range-or-typeC 6func-nameC;
6input declaration&s(C
6!ariable-declaration&s(C
begin II if more t,an one statement needed
6statementsC
end II if %e0in used
endfunction
Gunctions 8contNd9Gunctions 8contNd9
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• 3unction Declaration and n+ocation – n+ocation synta'@
6func-nameC &6argument&s(C(;
Gunctions 8contNd9Gunctions 8contNd9
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• #e$antics – $uch li.e function in Pascal
– -n internal i$plicit reg is declared inside the !unction
with the sa$e na$e
– he return +alue is speci!ied &y setting that i$plicit reg
– rangeNorNtypeM de!ines width and type o! the i$plicit
reg
• type can &e integer or real
• de!ault &it width is 9
Gunction ;a!plesGunction ;a!ples%arity enerator%arity enerator
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module parity;
reg [31:0] addr;
reg parity;
'nitial begin
E
end
alays 4&addr(
begin
parity " calc-parity&addr(; Bdisplay&STarity calculated # Q%S,
calc-parity&addr( (;
end
function calc-parity;
input [31:0] address;
begin
calc-parity " Gaddress;
end
endfunction
endmodule
Gunction ;a!plesGunction ;a!plesControlla"le 6hi#terControlla"le 6hi#ter
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Controlla"le 6hi#terControlla"le 6hi#ter
module s?ifter;
Hdefine 9-/' 1b0
Hdefine 8'I-/' 1b1
reg [31:0] addr, left-addr,rig?t-addr;
reg control;
initial
begin
E
end
alays 4&addr(begin
left-addr "s?ift&addr, H9-/'(;
rig?t-addr "s?ift&addr,H8'I-/'(;
end
function [31:0] s?ift;
input [31:0] address;
input control;
begin
s?ift " &control""H9-/'( J
&address661( : &addressCC1(;
end
endfunction
endmodule
)as*s and Gunctions 6u!!ary)as*s and Gunctions 6u!!ary
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• as.s and !unctions in &eha+ioral $odeling
– he sa$e purpose as su&routines in #W
– 5ro+ide $ore reada&ility8 easier code $anage$ent
– -re part o! design hierarchy
– as.s are $ore general than !unctions
• ,an represent al$ost any co$$on Verilog code
– 3unctions can only $odel purely co$&inational
calculations
%%-rith$etic 3unctions and-rith$etic 3unctions and
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,ircuits,ircuits
Spring 2004
Jong Won Park jwpark@crow.cnu.ac.kr
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2-Q Binary dders2-Q Binary dders
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• -rith$etic ,ircuit – a co$&inational circuit !or arith$etic operations
such as addition8 su&traction8 $ultiplication8 and
di+ision
with &inary nu$&ers or deci$al nu$&ers in a &inary
code
• -ddition o! < &inary inputs8 'alf !dder"
– 0=0A08 0=9A98 9=0A98 9=9 A 90%a&le 5-1%ru"' %a&le o (al )**er
S + , / , + , $ + ,
Figure 5-2 ogic Diagramo (al )**er
2-Q Binary dders2-Q Binary dders
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• -ddition o! &inary inputs8 'Full !dder'
%a&le 5-2%ru"' %a&le o Full )**er
Figure 5-3 ogic Diagram o (al )**er
Figure 5-4ogic Diagramo Full )**er
2-Q Binary dders2-Q Binary dders
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• Binary /ipple ,arry -dder – su$ o! two n*&it &inary nu$&ers in parallel
– G*&it parallel adder
- A 90998 B A 0099
Figure 5-5 4-Bi" ipple $arr )**er
2-Q Binary dders2-Q Binary dders
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• ,arry Loo.ahead -dder – he ripple carry adder has a long circuit delay
• the longest delay@ < n = < gate delay
#arry $ookahead !dder
• reduced delay at the price o! co$ple' hardware
– a new logic hierarchy
5i@ propagate !unction i@ generate !unction
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2-< Binary 6u"traction
10 * &
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– #u&traction
– a &orrow occurs into the $ost signi!icant position
4 * 7 AAM 4 * 7 =
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1' `*9) 09900900 * 90090990
Figure 5-7Block Diagram o Binar)**er-Su&"rac"er
2-< Binary 6u"traction
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• ,o$ple$ents – < types@
• radi' co$ple$ent@ rUs co$ple$ent
• di$inished radi' co$ple$ent@ (r*9)Us co$ple$ent
–
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–
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2-1 Binary dder-6u"tractors
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Figure 5-< )**er-Su&"rac"or $ircui"
) - B + ) / =-B; in 2> complemen" orm
wi"' e:clu>i#e-? ga"e =B⊕0+B B⊕1+B; a**er i S + 0 >u&"rac"or i S + 1
2-1 Binary dder-6u"tractors
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• #igned Binary 7u$&ers
– sign &it@ 0 !or positi+e nu$&ers
9 !or negati+e nu$&ers
– *: (A*9009) using Q &its
9) signed*$agnitude representation@ 90009009
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%a&le 5-3Signe* Binar um&er>
2-1 Binary dder-6u"tractors
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– #igned Binary -ddition and #u&traction
9: 5-5; Signe* Binar Su&"rac"ion A>ing 2> $omplemen"
9: 5-4; Signe* Binar )**ing A>ing 2> $omplemen"
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2-2 Binary $ultipliers2-2 Binary $ultipliers
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• a
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• a G*Bit &y *Bit Binary 4ultiplier
Figure 5-11 ) 4-Bi" & 3-Bi" Binar Cul"iplier
2-4 'ther rith!etic Gunctions2-4 'ther rith!etic Gunctions,ontraction
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$a.ing a si$pler circuit !or a speci!ic application
• 1' `*6) ,ontraction o! 3ull -dder 12uations
2-4 'ther rith!etic Gunctions2-4 'ther rith!etic Gunctions• 1' `*6) ,ontraction o! 3ull -dder 12uations
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• # A - = B = ,0 # A - = 99^9 = ,0
A - * 9 = ,0 (in
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• ncre$enting( 중간 0 위치 내림 8 C &ecause o! *&it incre$enter)
Figure 5-12 $on"rac"ion o )**er "o !ncremen"er
2-4 'ther rith!etic Gunctions2-4 'ther rith!etic Gunctions
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•4ultiplication &y,onstants
Figure 5-13 $on"rac"ion> o Cul"iplier=a; For 101 , B
=&; For 100 , B an*=c; For B E 100
2- HDL :epresentations-VHDL2- HDL :epresentations-VHDL• 1' `*;)Hierarchical
VHDL !
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VHDL !or
a G – Bit /ipple ,arry
-dder
• V ,() C/
,G
Figure 5-14 (ierarc'icalS"ruc"ureEDa"alow De>crip"ion? 4-Bi" Full )**er
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2- HDL :epresentations2- HDL :epresentations
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•1' `*Q) Beha+ioral VHDL !or a G – Bit /ipple ,arry-dder
Figure 5-16 Be'a#ioral De>crip"ion o 4 &i" Full )**er
2-0 HDL :epresentations-Velilog2-0 HDL :epresentations-Velilog
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Figure 5-17 (ierarc'ical Da"alowES"ruc"ure De>crip"ion o 4 &i" Full )**er
2-0 HDL :epresentations-Velilog2-0 HDL :epresentations-Velilog
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9: 5-10; Be'a#ioral G(D or a 4 Bi" ipple $arr )**er