Code Verilog

39
Báo Cáo Môn Thí Nghiệm Kĩ Thuật Số Trường Đại học Bách Khoa TP HCM TP.HCM --- 2014 Bài thí nghiệm 1 Switches, Lights, Multiplexers 1 . T h í n g h i ệ m 1 . 1 : Thực hiện mạch thí nghiệm có ngõ vào là 10 công tắc SW 9−0 , và ngõ ra là 10 đèn LED màu đỏ LEDR 9−0 dùng để đọc trạng thái của các ngõ vào. • C á c b ư ớ c cầ n t h ực h i ệ n : 1. Tạo project mới. 2. Viết chương trình Verilog cho bài TN 3. Gán chân & biên dịch project. 4. Nạp project vào kit TN. Thử mạch. Chương trình: module BAI1_1 (SW, LEDR); pg. 1 Họ Và Tên: Trần Kha MSSV: 41201568 Khoa: Điện-Điện Tử NHÓM: 01

description

code Verilog DE1

Transcript of Code Verilog

Bo CoMn Th Nghim K Thut SH V Tn: Trn Kha MSSV: 41201568Khoa: in-in T NHM: 01

Trng i hc Bch Khoa TP HCMTP.HCM --- 2014

Bi th nghim 1

Switches, Lights, Multiplexers

1. Th nghim 1.1:

Thc hin mch th nghim c ng vo l 10 cng tc SW 90 , v ng ra l 10 n LED mu LEDR90 dng c trng thi ca cc ng vo.

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog cho bi TN3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch. Chng trnh:

module BAI1_1 (SW, LEDR);input [9:0] SW;output [9:0] LEDR;assign LEDR = SW;endmodule

2. Th nghim 1.2:

Cho mch multiplexer 2 sang 1 nh hnh 2 vi ng vo chn knh s. Nu s = 0 ng ra m s bng ng vo x, v nu s = 1 th ng ra m = y.

x

m sy

a) S mch

ssm0xx0m1yy1

b) Bng s thtc) K hiu

Hnh 2. Mch multiplexer 2 sang 1. Mch c th m t dng m Verilog nh sau:assign m = (~ s&x)|(s& y);

Dng 4 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 2 sang 1 - 4 bit nh hnh 3a. Mch c 2 ng vo nh phn 4 bit X v Y, v ng ra 4 bit M. Nu s = 0 th M = X , cn s = 1 th M = Y.

pg. 13

s

x30m3y31

X03m

2s

Y31

x00m

0y01

4X04MY14

Cc bc cn thc hin:1. To project mi.2. Vit chng trnh Verilog vi:i. s = SW9 v ni vi LEDR9ii. X = SW3-0 v ni vi LEDR3-0iii. Y = SW7-4 v ni vi LEDR7-4iv. M = LEDG3-0

2. Gn chn3. Bin dch project.4. Np project vo kit TN.5. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .

Chng trnh:module BAI1_2(SW,LEDR,LEDG);input [9:0]SW;output [9:0]LEDR;output [3:0]LEDG;assign LEDR=SW;Mux2to1(SW[9],SW[0],SW[4],LEDG[0]);Mux2to1(SW[9],SW[1],SW[5],LEDG[1]);Mux2to1(SW[9],SW[2],SW[6],LEDG[2]);Mux2to1(SW[9],SW[3],SW[7],LEDG[3]);endmodulemodule Mux2to1(S,X,Y,M);input S,X,Y;output M;assign M=(~S&X)|(S&Y);endmodule

3. Th nghim 1.3:

Dng 3 b multiplexer 2 sang 1 nh hnh 2 thc hin mch multiplexer 4 sang 1 nh hnh 4a.Mch c 4 ng vo u, v, w v x; 1 ng ra m; 2 ng vo chn knh s1 s0 Tng t dng 2 mch multiplexer 4 1 nh hnh 4a thc hin mch multiplexer 4 1 - 2 bit nh hnh 5

s1s0

u0v101 m

w0x1

a) s mch

s1 s0m0 0u0 1v1 0w1 1x

s1s0

u xv0001w10m11

x

b) bng s thtc) k hiuHnh 4. Mch multiplexer 4 sang 1

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:s1 s0 = SW9-8 v ni vi LEDR9-8U-X = SW7-0 v ni vi LEDR7-0M = LEDG1-03. Gn chn4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW ri theo di cc n LED xanh, .

Chng trnh:

module BAI1_3(SW,LEDR,LEDG);input [9:0]SW;output [9:0]LEDR;output [1:0]LEDG;assign LEDR=SW;Mux4to1(SW[8],SW[9],SW[0],SW[2],SW[4],SW[6],LEDG[0]);Mux4to1(SW[8],SW[9],SW[1],SW[3],SW[5],SW[7],LEDG[1]);endmodulemodule Mux4to1(S0,S1,U,V,W,X,M);input S0,S1,U,V,W,X;output M; wire t1,t0;Mux2to1(S0,U,V,t0);Mux2to1(S0,W,X,t1);Mux2to1(S1,t0,t1,M);endmodulemodule Mux2to1(S,X,Y,M);input S,X,Y;output M;assign M=(~S&X)|(S&Y);endmodule

4. Th nghim 1.4:

Thc hin b gii m c 2 ng vo c1 c0 v 7 ng ra t 0 n 6 dng hin th cc k t trn b hin th 7 on nh hnh 6.Bng 1 lit k cc k t cn hin th (gm H,E,L v k t O) tng ng vi cc ng vo c1 c0 . Cc ng ra tch cc mc logic 0.

c17-segment decoderc0

0

561

42

3

Hnh 6. B gii m 7 on

c1 c0K t

0 0H0 1E1 0L1 1O

Bng 1. Bng m ch

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:oCc ng vo c1 c0 ni vi cc cng tc SW1-0oCc ng ra 0 6 ni vi HEX00, HEX01..HEX063. Gn chn4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.

Chng trnh:

module BAI1_4(SW,HEX0);input [1:0]SW;output [6:0]HEX0;reg [6:0] HEX0;always @ (SW[1:0])begincase (SW[1:0])2'b00: HEX0= 7'b0001001;2'b01: HEX0= 7'b0000110; 2'b10: HEX0= 7'b1000111;2'b11: HEX0= 7'b1000000;default: HEX0= 7'b1111111;endcase endendmodule

5. Th nghim 1.5:

Thc hin mch in hin th ch xoay nh hnh 7 hot ng theo bng 2.Cc cng tc SW70 dng to k t v SW 98 dng chn k t hin th.

SW9SW8

SW7 620

SW5 42

SW3 22

SW1 02

0 00 127-segment1 0decoder1 1

7561

42

3

Hnh 7. Mch c th chn & hin th 1 trong 4 k t.

SW9 SW8Hin th0 0H0 1E1 0L1 1O

Bng 2. Hin th ch xoay HELLO.

Cc bc cn thc hin:

1. To project mi.2. Vit chng trnh Verilog vi:3. Gn chn4. Bin dch project.5. Np project vo kit TN.6. Th mch bng cch thay i cc cng tc SW10 ri quan st b hin th 7 on.

Chng trnh:

Module BAI1_5(SW,HEX0,HEX1,HEX2,HEX3);input [9:0]SW;output [6:0]HEX0;output [6:0]HEX1;output [6:0]HEX2;output [6:0]HEX3;wire [1:0]A,B,C,D;Mux412b(SW[9:8],SW[1:0],SW[7:6],SW[5:4],SW[3:2],A);Mux412b(SW[9:8],SW[3:2],SW[1:0],SW[7:6],SW[5:4],B);Mux412b(SW[9:8],SW[5:4],SW[3:2],SW[1:0],SW[7:6],C);Mux412b(SW[9:8],SW[7:6],SW[5:4],SW[3:2],SW[1:0],D);ganchu(A,HEX0);ganchu(B,HEX1);ganchu(C,HEX2);ganchu(D,HEX3);endmodulemodule Mux412b(S,U,V,W,X,M);input [1:0]S,U,V,W,X;output [1:0]M;Mux4to1(S[0],S[1],U[0],V[0],X[0],W[0],M[0]);Mux4to1(S[0],S[1],U[1],V[1],X[1],W[1],M[1]);endmodulemodule Mux4to1(S0,S1,U,V,W,X,M);input S0,S1,U,V,W,X;output M; wire t1,t0;Mux2to1(S0,U,V,t0);Mux2to1(S0,W,X,t1);Mux2to1(S1,t0,t1,M);endmodulemodule Mux2to1(S,X,Y,M);input S,X,Y;output M;assign M=(~S&X)|(S&Y);endmodulemodule ganchu(S,HE);input [1:0]S;output [6:0]HE;reg [6:0] HE;always @ (S[1:0])begincase (S[1:0])2'b00: HE= 7'b0001001;2'b01: HE= 7'b0000110; 2'b10: HE= 7'b1000111;2'b11: HE= 7'b1000000;default: HE= 7'b1111111;endcase endendmodule

Bi th nghim 2

Numbers & Displays

y l bi th nghim thit k mch t hp thc hin b bin i s nh phn sang s thp phn v mch cng hai s BCD.

1. Th nghim 2.1:

Dng cc n 7 on HEX1 v HEX0 hin th cc s thp phn t 0 n 9. Gi tr hin th thay i c bng cc cng tc S W74 v S W30 tng ng.

Cc bc cn thc hin:1. To project mi.2. Vit chng trnh Verilog cho bi TN3. Gn chn & bin dch project.4. Np project vo kit TN. Th mch bng cch thay i cc cng tc v quan st cc n hin th. Chng trnh:

module BAI2_1(SW,HEX0,HEX1);input [7:0]SW;output [6:0]HEX0,HEX1;assign HEX1=(SW[7:4]==4'b0000)?7'b011_1111:(SW[7:4]==4'b0001)?7'b111_1001:(SW[7:4]==4'b0010)?7'b010_0100:(SW[7:4]==4'b0011)?7'b011_0000:(SW[7:4]==4'b0100)?7'b001_1001:(SW[7:4]==4'b0101)?7'b001_0010:(SW[7:4]==4'b0110)?7'b000_0010:(SW[7:4]==4'b0111)?7'b111_1000:(SW[7:4]==4'b1000)?7'b000_0000:7'b001_0000;

assign HEX0=(SW[3:0]==4'b0000)?7'b011_1111:(SW[3:0]==4'b0001)?7'b111_1001:(SW[3:0]==4'b0010)?7'b010_0100:(SW[3:0]==4'b0011)?7'b011_0000:(SW[3:0]==4'b0100)?7'b001_1001:(SW[3:0]==4'b0101)?7'b001_0010:(SW[3:0]==4'b0110)?7'b000_0010:(SW[3:0]==4'b0111)?7'b111_1000:(SW[3:0]==4'b1000)?7'b000_0000:7'b001_0000;endmodule

2. Th nghim 2.2:

Thc hin 1 phn ca mch chuyn i s nh phn 4 bit V = v 3 v2 v1 v0 thnh s thp phn D = d1 d0 n h hnh 1, b n g 1. Mch bao gm mch so snh ( kim tra V > 9), mch multiplexer v mch A (cha cn thc hin mch B v b gii m 7 on). Mch s c ng vo V 4 bit, ng ra M 4 bit v ng ra z.

Binary value

Decimal digits

000000

000101

001002

. . .. . .. . .

100109

101010

101111

110012

110113

111014

111115

Bng 1. Bng gi tr chuyn i nh phn thp phn.

Cc bc cn thc hin:1.To project mi. Vit chng trnh2.Bin dch project v thc hin m phng3.Vit thm on chng trnh cho mch B v mch gii m 7 on. Dng cc cng tc S W30 nhp s nh phn V v cc n 7 on HEX1, HEX0 hin th s thp phn d 1 d04.Bin dch li ri np project vo kit TN.5.Th mch: thay i gi tr V v quan st cc n hin th.

zComparator

Circuit B

d1

0

7561

42

v30m3301

v20m21

7-segment7decoder

d0

0

561

v101m1

v00m01

42

3

Circuit A

Hnh 1. Mch chuyn i nh phn-thp phn. Chng trnh:

module BAI2_2(SW,LEDR,HEX0,HEX1);input [3:0]SW;output [3:0]LEDR;output [6:0]HEX0,HEX1;assign LEDR=SW;wire [3:0]M,N;ss4bvoi9(SW,M,N);ganso(M,HEX0);ganso(N,HEX1);endmodulemodule ss4bvoi9(B,M,N);input [3:0]B;output [3:0]M,N;reg [3:0]M;reg [3:0]N;always@(B[3:0] or M or N)if (B[3:0]


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