MeG Timing CounterAmplifier – Splitter
Proposal
Pv
•
PMT fan-out for LXe
Calorimeter and Timing Counters
in:
-
single ended
signal on 50 Ω
coaxial
cableout:
-
high quality
signal to the digitizing electronic (Domino output)-
output for control and debugging (Monitor output)-
50 MHz
bandwidth limited
differential signal
to the
Type1
trigger board (Differential output)-
4 to 1
fan in capability
for lateral faces (Adder output)
-
a gain
to
compensate for
magfield
effects- disable control
Basic
requestsPv
Fan Out Fan Out
A1A1-
1° StageIn
(from
PMT) 50Ω
A2A2
A3A3
A4A4
2° Stage :to the Domino
2° Stage : for Monitor
2° Stage : to Trigger Board Type 1
Tst
In ?
+
+
OPA695
OPA695
OPA695
OPA695
Baseline
shift
?
Disable
control
Directlythe input
Σ Four channels OROPA684 ; not required for the TC
+
Pv
SelectedDevices
SelectedDevices
Preliminary
results
Pavia Jun
27th, 2003
+5.2
-5.2
+5.2
-5.2
+5.2
-5.2
+5.2
-5.2
+5.2
-5.2
GND
"Switch Off" Chip(Disable)
Output to Dmino(a positive signal in the range of 0-2V)
Monitor Output
N_Inv Out
Inv Out
to the ADC Diff_In
local pws filtersfor every chip
negative Inputfrom PMT
43
50
390
50
100nF
330
50
330
50
50
100
22
470
50
50
COAX
COAX
50
1K
1K
510
510
50
50
10uF
10uF
100nF
100nF
1nF
1nF
+
-
U?AD8138
8
1 43
6
52
+
-
U?OPA685
3
26
74 8
+
-
U?OPA685
3
26
74 8
+
-
U?OPA685
3
26
74 8
A1 A2
A3
A4
SchematicsSchematics
PreAmpBox
PreAmpBox
50Ω-20dB
ch1 ch2
InLin.Out
PulseOut
Pulse Generator
-5.2 +5.2
PwS
2.0ns Lead2.0ns Trail
15 ns Width
LeCroy
9210
LeCroy
Lt 365 500MHz1GS/s
9211
Scope
Test SetUpTest SetUp
Test BoardsTest Boards
+5.2
-5.2
"Switch Off" Chip(Disable)
negative Inputfrom PMT
43
50
390
50
100nF
+
-
U?OPA685
3
26
74 8
1° Stage1° Stage
A1 Non_Inverting
configuration
;Gain
( loaded) : +5
On channel
#1, Pulse
Gen
complementary
Output ;On channel
#2, Ampli Out
+5.2
-5.2
+5.2
-5.2 Output to Dmino(a positive signal in the range of 0-2V)
Monitor Output330
50
330
5050
100
22
470
5050
COAX
COAX
+
-
U?OPA685
3
26
74 8
+
-
U?OPA685
3
26
74 8
2° Stage+ Monitor Buffer
2° Stage+ Monitor Buffer
A2
A3
A2 : Inverting
conf. ; Gain
: -2 (on load) ;A3 : N_Inv
conf. ; Gain
: +1
Ch
#2: “Domino”
Output ( A2 ) ;Ch
#3: “Monitor”
Output ( A3 )
+5.2
-5.2
N_Inv Out
Inv Out
to the ADC Diff_In
50
1K
1K
510
510
50
50+
-
U?AD8138
8
1 43
6
52
Differential BufferDifferential Buffer
A4
A1A1
A2A2
A4A4
to
Ch2
to
Ch3
to
Ch4
Single-Ended
to
DifferentialConversion
; Gain
: 2
With this arrangenement we havea total Gain, on the first branch( A1-A2 ), of about 10 with a –3dB BW of about 350MHz anda monitor (if required) of the effective signal to the Domino
A1 A2
to
Ch#1
to
Ch#2
-20 dB
9211
A new breadboard comprehensive of all the component,including the Summing Amplifier ( OPA684 ), is under development and should be ready for the beginning ofJuly
ConclusionsConclusions
New prototype breadbordJuly 2003
R151K
From otherInputs
-+
U4AD-8138
1 4
5
63
28
-6
R23510
MeG Bd1/03 1.1
Timing Counter Amplifier-Splitter
A4
1 1Friday, July 04, 2003
SERV.EL. DFNT v. Bassi 6 ; Pavia
Title
Size Document Number Rev
Date: Sheet of
R450
+6
R6470
J3
1
2
C5100n
R2550
C21n
W2COAX
R2550
R2850
+
-
OPA-685U1
3
26
74
8
+6
+6
R2450
R23510
-6
R740.5
R1086.7
C710uF
R1650
J1
1
2
JP?
1 2
R1150
C4100n
+6
+6
R1950
W1COAX
R2450
R5116
R350
+6
R13330
DIS\
J4
1
2
R1850
R8360
R221K
GND
R17510
C1
0,1
R150
R2150
R23510
J51
2
J2
1
2
R20510
R2550
C31n
-6
R2550
R2450
+
-
OPA-685U2
3
26
74
8
-6
R2450
R14330
+
-
OPA-685U3
3
26
74
8
R222
R261K
-6
+6
+
-
U5OPA684
3
26
74
8
C610uF
J61
2
-6
C10100n
Su tutti gliintegrati
-6
R950
R23510
R1250
BreadBoard PicBreadBoard Pic
Ch
#1 : Vgen
compl. Out
Ch
#2 : Out “Domino”
Ch
#3 : Out “Monitor”
Ch
#4 : Out “
Σ
”
G -20dB-20dB AA
Lead
& Trail
: 2nsWidth
: 15ns
AG
: 50mV
Preliminary
test results
Timing tests
using
a 15 nsec
width
pulse
as
input.
Domino and test output:
dynamic
output range: 0 –
1.8 Vrise time:
Timing CounterAmplifier – Splitter
Actual situation
Sept. 2003
V-U3
from DAC
J7
1
C3210uF
-+
U5AD-8138
1 4
5
63
28
V+U2
R1350
R1940.5
Pedestal adj
Tst In
R1122
V+U3
Out toDOMINO
C21100n
R2186.7
J3
1
V-U3
R21K
C30100n
V-U3
L7
C24100n
( Remote BaseLine adj )
VCC
C710uF
C221n
R91K2
C1110uF
L6
VEE
R14K7
J8
1
V+U2
VCC
V-U4
GND
R83K3
R27510
VEE
C35CAP ?
C41n
C15100n
C1710uF
C341n
R2950
R1550
V+U5
V+U4
C61n
C2910uF
to the Adder
R622
CH IN
V+U2
C3100n
L2
R321K
C91n
C25100n
Out toMONITOR
V+U4
L8
V-U2
C5100n
MeG Bd1/03 1.2
Timing Counter Amplifier-Splitter
A4
1 1Thursday, August 21, 2003
SERV.EL. DFNT v. Bassi 6 ; Pavia
Title
Size Document Number Rev
Date: Sheet of
R2250
VCC
VCC
V-U2
VCC
V-U4
R42K
R2850
GND
R1650
R18470
R24330
+
-U1OPA27
3
26
7148
+
-
OPA-685U4
3
26
74
8
L1
C2610uF
GND
C281n
GND
V+U5
50 ohm strip line
V+U4
V-U2
J1
1
C12100n
V+U3
R1250
V+U3
V-U2
C1410uF
C311n
Disable
V-U5
R17116
+
-
OPA-685U2
3
26
74
8
R25330
J2
1
VEE
R722
R3150
V+U2
+
-
OPA-685U3
3
26
74
8
C33100n
VEE
L3
L5
Channel Disable In
Out to ADC
VEE
VCC
C191n
C131n
C10100n
Q1NPN
J4
1
R20360
L4
R261K
GND
C20,1
R2350
V-U4
C23100n
R1450
C8100n
VCC
R30510
R34K7
VEE
J6
12
C2010uF
Offset adj
OPA27
V-U5
R1050
V+U5
C161n
R5R
C1CAP NP
V-U5
C27100n
C18100n
J5
1
Single Channel Timig Counter Amlifier – Splitter : Schematic
Single Channel
Splitter
Daughter
Board
PCB
Timing Counter Aplifier – SplitterTiming Counter Aplifier – Splitter
A1 A2
to
Ch#1
to
Ch#2
-20 dB
9211
A3 to
Ch#3
to
Ch#4
A
A Input Signal
to
1st
Ampli Stage
Bench Test ResponseBench Test Response
Σ
D
M
ref.
A1A1
A2A2
A4A4
to
Ch2
to
Ch3
to
Ch4
Differential Outputs
0,0200,0
400,0600,0
800,01000,01200,0
1400,01600,0
1800,02000,0
0,0 500,0 1000,0 1500,0 2000,0 2500,0
Input(x10) mV
DO
MIN
O O
utpu
t mV
0,0200,0
400,0600,0
800,01000,01200,0
1400,01600,0
1800,02000,0
0,0 500,0 1000,0 1500,0 2000,0 2500,0
Input(x10) mV
DO
MIN
O O
utpu
t mV
1891
1911
LinearityLinearity
Expan
1500
1600
1700
1800
1900
2000
1500 1750 2000 2250
In mV
Out
mV
Series1
(1891, 1911)
Expan
1500
1600
1700
1800
1900
2000
1500 1750 2000 2250
In mV
Out
mV
Series1
(1891, 1911)
Max Vout LimitMax Vout Limit
Performance
Input : single ended 50 ohm coaxGain: 10xRise time : 1 nsBandWidth : 350 MHzOut 1 : max V out 1,8 V into 50 ohm full bandOut 2 : max V out 1,8 V into 50 ohm full bandOut 3 : full band (to 4 input analog adder)Out 4 : bandWidth limited differential (to trigger board)
Power requirement:
+ 6V , 65 mA
; - 6V , 65 mA
Ch2 Ch3 Ex T
PMT Test ResponsePMT Test Response
Scope
PMTA
PMT :Hamamatsu
Fine mesh1.5”
; 19 dynodeHV : –2100V
Ch
#2 : PMT Out ;Ch
#3 : Splitter, Domino Out .
LED
Latest version
Dec. ‘03
1st Prototype :Six channelsNIM module( without SlowControl bd )
Pv
Measurement SetUp
Pulse Generator
LeCroy
9210
9212
ch1 ch2
ScopeTektronix TDS7254B
TCAMPLISPLITT
Leading
& Trailing
Edge
: 300 psWidth
: 20 ns
Splitter50 Ω2GHz
Attenuator20 db50 Ω
Trig
Out
In
Out 1
Pv
Vin(mV) Vout(mV) Gain2,5 25,0 10,005,0 50,5 10,107,5 75,5 10,07
10,0 100,6 10,0615,0 150,8 10,0520,0 201,0 10,0530,0 302,0 10,0740,0 402,0 10,0550,0 504,0 10,0860,0 604,5 10,0870,0 708,0 10,1180,0 808,0 10,1090,0 912,0 10,13
100,0 1008,0 10,08120,0 1223,0 10,19140,0 1420,0 10,14160,0 1615,0 10,09180,0 1820,0 10,11185,0 1870,0 10,11190,0 1920,0 10,11195,0 1968,0 10,09200,0 2019,0 10,10205,0 2085,0 10,17210,0 2130,0 10,14215,0 2185,0 10,16220,0 2239,0 10,18225,0 2285,0 10,16230,0 2290,0 9,96240,0 2295,0 9,56250,0 2300,0 9,20
Gain
0
500
1000
1500
2000
2500
0 50 100 150 200 250 300
Vin (mV)
Vout
(mV)
Linearity Evavuation
Pv
Stabilità Termica
T °C Vin(mV) Vout(mV)
24° 100 1016
50° 100 1024
Pv
8 mV di variazione nel range24 ÷ 50 °C . Quindi : ≈ 30 μV
/ °C
Leading Edge
1.1 ns(10 –
90 %)
Pv
BW
0,00
2,00
4,00
6,00
8,00
10,00
12,00
0 50 100 150 200 250 300 350 400
freq (MHz)
Vo/V
i
BandWidth
340 MHz
Pv
In – Out Delay
Dal valore misuratovanno sottratti 5nsdel cavetto di outputverso lo Scope.Quindi :
ΔT ≈
4.4 ns
Lo Spread temporale (Jitter) delSegnale di Uscita (rispetto al segnaledi trigger del generatore)risulta : ≤
30 ps(misurato con un analizzatore multicanalecon una risoluzione di 12.2 ps / ch )
Pv
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