1
LT1575/LT1577
Ultrafast Transient Response,Low Dropout Regulators
Adjustable and Fixed
TYPICAL APPLICATION
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1
2
3
4
8
7
6
5
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMP
C2 1µF
C5 220µF
5V
GND1575/77 TA01
VOUT 3.3V 5A
R2 5Ω
R1 7.5k
12V LT1575-3.3
C4 1000pF
FOR T > 45°C: C6 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS. PLACE C6 IN THE MICROPROCESSOR SOCKET CAVITY
FOR T < 45°C: C6 = 24 × 1µF Y5V CERAMIC SURFACE MOUNT CAPACITORS.
*Q1 IRFZ24
+
C3 10pF
C6* 24µF
Ultrafast Transient Response 5V to 3.3V Low Dropout Regulator(For Schematic Including Current Limit, See Typical Applications)
50mV/DIV
2A/DIV
100µs/DIV1575/77 TA02
Transient Response for0.2A to 5A Output Load Step
Pentium® Processor Supplies PowerPCTM Supplies 5V to 3.XXV or 3.3V to 2.XXV Microprocessor Supplies GTL Termination Low Voltage Logic SuppliesLT1575CN8/LT1575CS8 AdjustableLT1575CN8-1.5/LT1575CS8-1.5 1.5V FixedLT1575CN8-2.8/LT1575CS8-2.8 2.8V FixedLT1575CN8-3.3/LT1575CS8-3.3 3.3V FixedLT1575CN8-3.5/LT1575CS8-3.5 3.5V FixedLT1575CN8-5/LT1575CS8-5 5V FixedLT1577CS-ADJ/ADJ Adjustable, AdjustableLT1577CS-3.3/ADJ 3.3V Fixed, AdjustableLT1577CS-3.3/2.8 3.3V Fixed, 2.8V Fixed
Consult factory for additional output voltage combinations availablein the LT1577.
APPLICATIONSU
DESCRIPTION
U
UltraFastTM Transient Response EliminatesTantalum and Electrolytic Output Capacitors
FET RDS(ON) Defines Dropout Voltage 1% Reference/Output Voltage Tolerance Over
Temperature Typical Load Regulation: 1mV High Side Sense Current Limit Multifunction Shutdown Pin with Latchoff
FEATURESThe LT®1575/LT1577 are single/dual controller ICs thatdrive low cost external N-channel MOSFETs as sourcefollowers to produce ultrafast transient response, lowdropout voltage regulators.
The LT1575/LT1577 achieve unprecedented transient-load performance by eliminating expensive tantalum orbulk electrolytic output capacitors in the most demandingmodern microprocessor applications. Precision-trimmedadjustable and fixed output voltage versions accommo-date any required microprocessor power supply voltage.Selection of the N-channel MOSFET RDS(ON) allows verylow dropout voltages to be achieved.
Unique protection features include a high side currentlimit amplifier that activates a fault protection timercircuit. A multifunction Shutdown pin provides eithercurrent limit time-out with latchoff, overvoltage protec-tion, thermal shutdown or a combination of these func-tions. The LT1575 is available in 8-pin SO or PDIP and theLT1577 is available in 16-pin narrow body SO.
UltraFast is a trademark of Linear Technology Corporation.Pentium is a registered trademark of Intel Corporation.PowerPC is a trademark of IBM Corporation.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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LT1575/LT1577
A
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G
W
A
W
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ARBSOLUTE XI TI S(Note 1)VIN, IPOS, INEG ...................................................... 22VSHDN....................................................................... VINOperating Ambient Temperature Range ..... 0°C to 70°C
Junction Temperature (Note 2) ................ 0°C to 100°CStorage Temperature Range ................ –65°C to 150°CLead Temperature (Soldering, 10 sec) ................. 300°C
WU U
PACKAGE/ORDER I FOR ATIO
1
2
3
4
8
7
6
5
TOP VIEW
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMP
S8 PACKAGE 8-LEAD PLASTIC SO
N8 PACKAGE 8-LEAD PDIP
TJMAX = 100°C, θJA = 100°C/ W (N8)TJMAX = 100°C, θJA = 130°C/ W (S8)
LT1575CN8-1.5LT1575CS8-1.5LT1575CN8-2.8LT1575CS8-2.8LT1575CN8-3.3
ORDER PART NUMBERORDER PART NUMBER
LT1575CS8-3.3LT1575CN8-3.5LT1575CS8-3.5LT1575CN8-5LT1575CS8-5
15753515755
157515157528157533
ORDER PART NUMBER
LT1577CS-ADJ/ADJ
TJMAX = 100°C, θJA = 100°C/ W
TOP VIEW
S PACKAGE 16-LEAD PLASTIC NARROW SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN1
VIN1
GND1
FB1
SHDN2
VIN2
GND2
FB2
IPOS1
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
1
2
3
4
8
7
6
5
TOP VIEW
SHDN
VIN
GND
FB
IPOS
INEG
GATE
COMP
S8 PACKAGE 8-LEAD PLASTIC SO
N8 PACKAGE 8-LEAD PDIP
TJMAX = 100°C, θJA = 100°C/ W (N8)TJMAX = 100°C, θJA = 130°C/ W (S8)
LT1575CN8LT1575CS8
1575
S8 PART MARKING S8 PART MARKING
Consult factory for Industrial and Military grade parts.
ORDER PART NUMBER
LT1577CS-3.3/ADJ
TJMAX = 100°C, θJA = 100°C/ W
TOP VIEW
S PACKAGE 16-LEAD PLASTIC NARROW SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN1
VIN1
GND1
OUT-3.3
SHDN2
VIN2
GND2
FB
IPOS1
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
ORDER PART NUMBER
LT1577CS-3.3/2.8
TJMAX = 100°C, θJA = 100°C/ W
TOP VIEW
S PACKAGE 16-LEAD PLASTIC NARROW SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHDN1
VIN1
GND1
OUT-3.3
SHDN2
VIN2
GND2
OUT-2.8
IPOS1
INEG1
GATE1
COMP1
IPOS2
INEG2
GATE2
COMP2
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LT1575/LT1577
ELECTRICAL CHARACTERISTICSTA = 25°C, VIN = 12V, GATE = 6V, IPOS = INEG = 5V, SHDN = 0.75V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IQ Supply Current 5 12 19 mA
VFB LT1575 Reference Voltage –0.6 1.210 0.6 % –1.0 1.210 1.0 %
VOUT LT1575-1.5 Output Voltage –0.6 1.500 0.6 % –1.0 1.500 1.0 %
LT1575-2.8 Output Voltage –0.6 2.800 0.6 % –1.0 2.800 1.0 %
LT1575-3.3 Output Voltage –0.6 3.300 0.6 % –1.0 3.300 1.0 %
LT1575-3.5 Output Voltage –0.6 3.500 0.6 % –1.0 3.500 1.0 %
LT1575-5 Output Voltage –0.6 5.000 0.6 % –1.0 5.000 1.0 %
Line Regulation 10V ≤ VIN ≤ 20V 0.01 0.03 %/V
IFB FB Input Bias Current FB = VFB –0.6 –4.0 µA
IOUT OUT Divider Current OUT = VOUT 0.5 1.0 1.5 mA
AVOL LT1575 Large-Signal Voltage Gain VGATE = 3V to 10V 69 84 dB
LT1575-1.5 Large-Signal Voltage Gain VGATE = 3V to 10V 67 82 dB
LT1575-2.8 Large-Signal Voltage Gain VGATE = 3V to 10V 60 76 dB
LT1575-3.3 Large-Signal Voltage Gain VGATE = 3V to 10V 60 75 dB
LT1575-3.5 Large-Signal Voltage Gain VGATE = 3V to 10V 60 74 dB
LT1575-5 Large-Signal Voltage Gain VGATE = 3V to 10V 56 71 dB
VOL GATE Output Swing Low (Note 3) IGATE = 0mA 2.5 3.0 V
VOH GATE Output Swing High IGATE = 0mA VIN – 1.6 VIN – 1 V
IPOS + INEG Supply Current 3V ≤ IPOS ≤ 20V 0.3 0.625 1.0 mA
Current Limit Threshold Voltage 42 50 58 mV 37 50 63 mV
Current Limit Threshold Voltage 3V ≤ IPOS ≤ 20V –0.20 –0.50 %/VLine Regulation
SHDN Sink Current Current Flows Into Pin 2.5 5.0 8.0 µA
SHDN Source Current Current Flows Out of Pin – 8 –15 –23 µA
SHDN Low Clamp Voltage 0.1 0.25 V
SHDN High Clamp Voltage 1.50 1.85 2.20 V
SHDN Threshold Voltage 1.18 1.21 1.240 V
SHDN Threshold Hysteresis 50 100 150 mV
The denotes specifications which apply over the full operatingtemperature range.Note 1: Absolute Maximum Ratings are those values beyond which the lifeof the device may be impaired.Note 2: TJ is calculated from the ambient temperature TA and powerdissipation PD according to the following formulas:
LT1575CN8: TJ = TA + (PD • 100°CW)LT1575CS8: TJ = TA + (PD • 130°CW)LT1577CS: TJ = TA + (PD • 100°CW)
Because the LT1577 consists of two regulators in the package, the totalLT1577 power dissipation must be used for its junction temperaturecalculation. The total LT1577 PD = PD (Regulator 1) + PD (Regulator 2).Note 3: The VGS(th) of the external MOSFET must be greater than3V – VOUT.
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LT1575/LT1577
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Quiescent Current vs TemperatureFB Input Bias Currentvs Temperature
Adjustable LT1575 VREFvs Temperature
TEMPERATURE (°C)–75
5
QUIE
SCEN
T CU
RREN
T (m
A)
7
9
11
19
15
–25 25 50 150
17
13
6
8
10
18
14
16
12
–50 0 75 100 125 175
1575/77 G01
VIN = 8V
VIN = 12V VIN = 20V
TEMPERATURE (°C)–75
REFE
RENC
E VO
LTAG
E (V
)
1.210
1.214
1.218
1.222
125
1575/77 G02
1.206
1.202
1.208
1.212
1.216
1.220
1.204
1.200
1.198–25 25 75–50 1500 50 100 175
TEMPERATURE (°C)–75
FB IN
PUT
BIAS
CUR
RENT
(µA)
3.0
4.0
125
1575/77 G03
2.0
1.0
2.5
3.5
1.5
0.5
0–25 25 75–50 1500 50 100 175
VIN = 20V
VIN = 12V VIN = 8V
LT1575-3.5 VOUT vs Temperature
LT1575-1.5 VOUT vs Temperature LT1575-2.8 VOUT vs Temperature LT1575-3.3 VOUT vs Temperature
TEMPERATURE (°C)–75
OUTP
UT V
OLTA
GE (V
)3.303
3.315
3.327
3.333
125
1575/77 G06
3.291
3.279
3.297
3.309
3.321
3.285
3.273
3.267–25 25 75–50 1500 50 100 175
TEMPERATURE (°C)–75
OUT
DIVI
DER
CURR
ENT
(mA)
1.1
1.3
1.5
125
1575/77 G09
0.9
0.7
1.0
1.2
1.4
0.8
0.6
0.5–25 25 75–50 1500 50 100 175
OUT Divider Currentvs Temperature
TEMPERATURE (°C)–75
REFE
RENC
E VO
LTAG
E (V
)
1.503
1.509
1.515
125
1575/77 G04
1.500
1.497
1.494
1.491
1.488
1.485
1.506
1.512
–25 25 75–50 1500 50 100 175TEMPERATURE (°C)
–75
OUTP
UT V
OLTA
GE (V
)
2.828
–25 25 50 150
2.8242.8002.8162.8122.8082.8042.8002.7962.7922.7882.7842.7802.7762.772
–50 0 75 100 125 175
1575/77 G05
TEMPERATURE (°C)–75
OUTP
UT V
OLTA
GE (V
)
3.535
–25 25 50 150
3.5303.5253.5203.5153.5103.5053.5003.4953.4903.4853.4803.4753.4703.465
–50 0 75 100 125 175
1575/77 G07
LT1575-5 VOUT vs Temperature
TEMPERATURE (°C)–75
OUTP
UT V
OLTA
GE (V
)
5.010
5.030
5.050
125
1575/77 G08
4.990
4.970
5.000
5.020
5.040
4.980
4.960
4.950–25 25 75–50 1500 50 100 175
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LT1575/LT1577
TYPICAL PERFORMANCE CHARACTERISTICS
UW
Error Amplifier Large-SignalVoltage Gain vs Temperature Gain and Phase vs Frequency
TEMPERATURE (°C)
0
LINE
REG
ULAT
ION
(%/V
)
0.010
0.020
0.030
0.005
0.015
0.025
–25 25 75 125
1575/77 G10
175–50–75 0 50 100 150
VREF/VOUT Line Regulationvs Temperature
TEMPERATURE (°C)–75
LARG
E-SI
GNAL
VOL
TAGE
GAI
N (d
B)
105
115
125
1575/77 G11
95
85
100
110
120
90
80
75
70–25 25 75–50 1500 50 100 175
Gate Output Swing Highvs Temperature
IPOS + INEG Supply Currentvs Temperature
TEMPERATURE (°C)–75
GATE
OUT
PUT
SWIN
G LO
W (V
)
2.50
3.00
125
1575/77 G13
2.00
1.50
2.25
2.75
1.75
1.25
1.00–25 25 75–50 1500 50 100 175
ILOAD = 50mA
NO LOAD
Gate Output Swing Lowvs Temperature
TEMPERATURE (°C)
0
GATE
OUT
PUT
SWIN
G HI
GH (V
)
1.0
2.0
3.0
0.5
1.5
2.5
–25 25 75 125
1575/77 G14
175–50–75 0 50 100 150
NO LOAD
ILOAD = 50mA
TEMPERATURE (°C)–75
300
I POS
+ I N
EG S
UPPL
Y CU
RREN
T (µ
A)
400
600
700
800
1000
–50 50 100
1575/77 G15
500
900
25 150 175–25 0 75 125
IPOS = INEG = 3V
IPOS = INEG = 5V IPOS = INEG = 12V IPOS = INEG = 20V
FREQUENCY (Hz)
50
100
ERRO
R AM
PLIF
IER
GAIN
AND
PHA
SE
150
200
1k 100k 1M 100M
1575/77 G12
010k 10M
PHASE
GAIN
Current Limit Threshold Voltagevs Temperature
TEMPERATURE (°C)
35
CURR
ENT
LIM
IT T
HRES
HOLD
VOL
TAGE
(mV)
45
55
65
40
50
60
–25 25 75 125
1575/77 G16
175–50–75 0 50 100 150
IPOS = 5V IPOS = 3V
IPOS = 20V
Current Limit Threshold VoltageLine Regulation vs Temperature
TEMPERATURE (°C)–75
CURR
ENT
LIM
IT T
HRES
HOLD
VO
LTAG
E LI
NE R
EGUL
ATIO
N (%
/V)
–0.2
–0.1
0
125
1575/77 G17
–0.3
–0.4
–0.5–25 25 75–50 1500 50 100 175
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LT1575/LT1577
TYPICAL PERFORMANCE CHARACTERISTICS
UW
SHDN Sink Currentvs Temperature
TEMPERATURE (°C)–75
SHDN
SIN
K CU
RREN
T (µ
A)
5.5
6.5
7.5
125
1575/77 G18
4.5
3.5
5.0
6.0
7.0
4.0
3.0
2.5–25 25 75–50 1500 50 100 175
SHDN Low Clamp Voltagevs Temperature
TEMPERATURE (°C)–75
SHDN
LOW
CLA
MP
VOLT
AGE
(V)
0.15
0.20
0.25
125
1575/77 G20
0.10
0.05
0–25 25 75–50 1500 50 100 175
SHDN Source Currentvs Temperature
TEMPERATURE (°C)–75
SHDN
SOU
RCE
CURR
ENT
(µA)
–15
–13
–11
125
1575/77 G19
–17
–19
–16
–14
–12
–18
–20
–10
–25 25 75–50 1500 50 100 175
SHDN Hysteresis vs Temperature
TEMPERATURE (°C)–75
SHDN
HYS
TERE
SIS
(mV)
110
130
150
125
1575/77 G22
90
70
100
120
140
80
60
50–25 25 75–50 1500 50 100 175
SHDN High Clamp Voltagevs Temperature
TEMPERATURE (°C)
1.5
SHDN
HIG
H CL
AMP
VOLT
AGE
(V)
1.7
1.9
2.1
1.6
1.8
2.0
–25 25 75 125
1575/77 G21
175–50–75 0 50 100 150
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LT1575/LT1577
PIN FUNCTIONS
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SHDN (Pin 1): This is a multifunction shutdown pin thatprovides GATE drive latchoff capability. A 15µA currentsource, that turns on when current limit is activated,charges a capacitor placed in series with SHDN to GNDand performs a current limit time-out function. The pin isalso the input to a comparator referenced to VREF (1.21V).When the pin pulls above VREF, the comparator latches thegate drive to the external MOSFET off. The comparatortypically has 100mV of hysteresis and the Shutdown pincan be pulled low to reset the latchoff function. This pinprovides overvoltage protection or thermal shutdownprotection when driven from various resistor dividerschemes.
VIN (Pin 2): This is the input supply for the IC that powersthe majority of internal circuitry and provides sufficientgate drive compliance for the external N-channel MOSFET.The typical supply voltage is 12V with 12.5mA of quiescentcurrent. The maximum operating VIN is 20V and theminimum operating VIN is set by VOUT + VGS of theMOSFET at max. IOUT + 1.6V (worst-case VIN to GATEoutput swing).
GND (Pin 3): Analog Ground. This pin is also the negativesense terminal for the internal 1.21V reference. Connectexternal feedback divider networks that terminate to GNDand frequency compensation components that terminateto GND directly to this pin for best regulation and perfor-mance.
FB (Pin 4): This is the inverting input of the error amplifierfor the adjustable voltage LT1575. The noninverting inputis tied to the internal 1.21V reference. Input bias currentfor this pin is typically 0.6µA flowing out of the pin. This pinis normally tied to a resistor divider network to set outputvoltage. Tie the top of the external resistor divider directlyto the output voltage for best regulation performance.
OUT (Pin 4): This is the inverting input of the erroramplifier for the fixed voltage LT1575. The fixed voltageparts contain a precision resistor divider network to setoutput voltage. The typical resistor divider current is 1mAinto the pin. Tie this pin directly to the output voltage forbest regulation performance.
COMP (Pin 5): This is the high impedance gain node of theerror amplifier and is used for external frequency compen-
sation. The transconductance of the error amplifier is 15millimhos and open-loop voltage gain is typically 84dB.Frequency compensation is generally performed with aseries RC network to ground.
GATE (Pin 6): This is the output of the error amplifier thatdrives N-channel MOSFETs with up to 5000pF of “effec-tive” gate capacitance. The typical open-loop outputimpedance is 2Ω. When using low input capacitanceMOSFETs (<1500pF), a small gate resistor of 2Ω to 10Ωdampens high frequency ringing created by an LC reso-nance that is created by the MOSFET gate’s lead induc-tance and input capacitance. The GATE pin delivers up to50mA for a few hundred nanoseconds when slewing thegate of the N-channel MOSFET in response to output loadcurrent transients.
INEG (Pin 7): This is the negative sense terminal of thecurrent limit amplifier. A small sense resistor is connectedin series with the drain of the external MOSFET and isconnected between the IPOS and INEG pins. A 50mVthreshold voltage in conjunction with the sense resistorvalue sets the current limit level. The current sense resis-tor can be a low value shunt or can be made from a pieceof PC board trace. If the current limit amplifier is not used,tie the INEG pin to IPOS to defeat current limit. Analternative is to ground the INEG pin. This action disablesthe current limit amplifier and additional internal circuitryactivates the timer circuit on the SHDN pin if the GATE pinswings to the VIN rail. This option provides the user witha “sense-less” current limit function.
IPOS (Pin 8): This is the positive sense terminal of thecurrent limit amplifier. Tie this pin directly to the maininput voltage from which the output voltage is regulated.The typical input voltage is a 5V logic supply. This pin isalso the input to a comparator on the fixed voltage ver-sions that monitors the input/output differential voltage ofthe external MOSFET. If this differential voltage is less than0.5V, then the SHDN timer is not allowed to start even if theGATE is at the VIN rail. This allows the regulator to start upnormally as the input voltage is ramping up, even with veryslow ramp rates.
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LT1575/LT1577
BLOCK DIAGRAM
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LT1575 Adjustable Voltage
SW2NORMALLY CLOSED
I2 5µA
–
+ERROR AMP
COMP
1575/77 BD1
–
+COMP1
Q6
SHDN
VIN
GND
FB
R2 5k
SW1NORMALLY OPEN
100mV HYSTERESIS
I1 15µA
I3 100µA
–
+ILIM AMP
VTH1 50mV
+–
VTH2 1V
+–
D1
IPOS
INEG
GATE
D2 –
+COMP2
–
+
COMP3
OR2
START-UP VREF1.21V
R1 50k
OR1
Q4
Q3Q2Q1
Q5
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LT1575/LT1577
BLOCK DIAGRAM
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LT1575 Fixed Voltage
SW2NORMALLY CLOSED
I2 5µA
–
+ERROR AMP
COMP
1575/77 BD2
–
+COMP1
Q6
SHDN
VIN
GND
OUT
R2 5k
SW1NORMALLY OPEN
100mV HYSTERESIS
I1 15µA
I3 100µA
–
+ILIM AMP VTH1
50mV
+–
VTH3 500mV
+–
VTH2 1V
+–
D1
IPOS
INEG
GATE
D2 –
+
–
+COMP2
COMP4
–
+
COMP3
OR2
START-UP VREF1.21V
R1 50k
OR1
Q4
Q3Q2Q1
Q5
R3*
*VOUT = (1 + R3/R4)VREF
R4*
Q7
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LT1575/LT1577
APPLICATIONS INFORMATION
WU UU
Introduction
The current generation of microprocessors place strin-gent demands on the power supply that powers theprocessor core. These microprocessors cycle load cur-rent from near zero to amps in tens of nanoseconds.Output voltage tolerances as low as ±100mV includetransient response as part of the specification. Somemicroprocessors require only a single output voltage fromwhich the core and I/O circuitry operate. Other higherperformance processors require a separate power supplyvoltage for the processor core and the I/O circuitry. Theserequirements mandate the need for very accurate, veryhigh speed regulator circuits.
Previously employed solutions included monolithic3-terminal linear regulators, PNP transistors driven by lowcost control circuits and simple buck converter switchingregulators. The 3-terminal regulator achieves a high levelof integration, the PNP driven regulator achieves very lowdropout performance and the switching regulator achieveshigh electrical efficiency.
However, the common trait manifested by these solutionsis that transient response is measured in many microsec-onds. This fact translates to a regulator output decouplingcapacitor scheme that requires several hundred microfar-ads of very low ESR bulk capacitance using multiplecapacitors surrounding the CPU. This required bulk ca-pacitance is in addition to the ceramic decoupling capaci-tor network that handles the transient load responseduring the first few hundred nanoseconds as well asproviding microprocessor clock frequency noise immu-nity. The combined cost of all capacitors is a significantpercentage of the total power supply cost.
The LT1575/LT1577 family of single/dual controller ICsare unique, easy to use devices that drive externalN-channel MOSFETs as source followers and permit a userto realize an extremely low dropout, ultrafast transientresponse regulator. These circuits achieve superior regu-lator bandwidth and transient load performance by com-pletely eliminating expensive tantalum or bulk electrolyticcapacitors in the most modern and demanding micropro-cessor applications. For example, a 200MHz Pentiumprocessor can operate with only the recommended 24 1µFceramic capacitors. Users benefit directly by saving sig-
nificant cost as all additional bulk capacitance is removed.The additional savings of insertion cost, purchasing/in-ventory cost and board space are readily apparent.
Precision-trimmed adjustable and fixed output voltageversions accommodate any required microprocessorpower supply voltage. Proper selection of the N-channelMOSFET RDS(ON) allows user-settable dropout voltageperformance. The only output capacitors required are thehigh frequency ceramic decoupling capacitors. This regu-lator design provides ample bandwidth and responds totransient load changes in a few hundred nanosecondsversus regulators that respond in many microseconds.The ceramic capacitor network generally consists of 10 to24 1uF capacitors for individual microprocessor require-ments. The LT1575/LT1577 family also incorporates cur-rent limiting for no additional system cost, provides on/offcontrol and overvoltage protection or thermal shutdownwith simple external components.
Therefore, the unique design of these new ICs combinesthe benefits of low dropout voltage, high functional inte-gration, precision performance and ultrafast transientresponse, as well as providing significant cost savings onthe output capacitance needed in fast load transient appli-cations. As lower input/output differential voltage applica-tions become increasingly prevalent, an LT1575-basedsolution achieves comparable efficiency performance witha switching regulator at an appreciable cost savings.
The new LT1575/LT1577 family of low dropout regulatorcontroller ICs step to the next level of performance re-quired by system designers for the latest generationmotherboards and microprocessors. The simple versatil-ity and benefits derived from these circuits allow thepower supply needs of today’s high performance micro-processors to be met with ease.
Block Diagram Operation
The primary block diagram elements consist of a simplefeedback control loop and the secondary block diagramelements consist of multiple protection functions. Exam-ining the block diagram for the LT1575, a start-up circuitprovides controlled start-up for the IC, including theprecision-trimmed bandgap reference, and establishes allinternal current and voltage biasing.
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APPLICATIONS INFORMATION
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Because the MOSFET pass transistor is connected as asource follower, the power path gain is much more pre-dictable than designs that employ a discrete PNP transis-tor as the pass device. This is due to the significantproduction variations encountered with PNP Beta.MOSFETs are also very high speed devices which enhancethe ability to produce a stable wide bandwidth controlloop. An additional advantage of the follower topology isinherently good line rejection. Input supply disturbancesdo not propagate through to the output. The feedback loopfor a regulator circuit is completed by providing an errorsignal to the FB pin in the adjustable voltage version andthe OUT pin in the fixed voltage version. In both cases, aresistor divider network senses the output voltage andsets the regulated DC bias point. In general, the LT1575regulator feedback loop permits a loop crossover fre-quency on the order of 1MHz while maintaining goodphase and gain margins. This unity-gain frequency is afactor of 20 to 30 times the bandwidth of currentlyimplemented regulator solutions for microprocessor powersupplies. This significant performance benefit is whatpermits the elimination of all bulk output capacitance.
Several other unique features are included in the designthat increase its functionality and robustness. These func-tions comprise the remainder of the block diagram.
A high side sense, current limit amplifier provides activecurrent limiting for the regulator. The current limit ampli-fier uses an external low value shunt resistor connected inseries with the external MOSFET’s drain. This resistor canbe a discrete shunt resistor or can be manufactured froma Kelvin-sensed section of “free” PC board trace. All loadcurrent flows through the MOSFET drain and thus, throughthe sense resistor. The advantage of using high sidecurrent sensing in this topology is that the MOSFET’s gainand the main feedback loop’s gain remain unaffected. Thesense resistor develops a voltage equal to IOUT(RSENSE).The current limit amplifier’s 50mV threshold voltage is agood compromise between power dissipation in the senseresistor, dropout voltage impact and noise immunity.Current limit activates when the sense resistor voltageequals the 50mV threshold.
Two events occur when current limit activates: the first isthat the current limit amplifier drives Q2 in the block
Reference voltage accuracy for the adjustable version andoutput voltage accuracy for the fixed voltage versions arespecified as ±0.6% at room temperature and as ±1% overthe full operating temperature range. This places theLT1575/LT1577 family among a select group of regulatorswith a very tightly specified output voltage tolerance. Theaccurate 1.21V reference is tied to the noninverting inputof the main error amplifier in the feedback control loop.
The error amplifier consists of a single high gain gm stagewith a transconductance equal to 15 millimhos. Theinverting terminal is brought out as the FB pin in theadjustable voltage version and as the OUT pin in fixedvoltage versions. The gm stage provides differential-to-single ended conversion at the COMP pin. The outputimpedance of the gm stage is about 1MΩ and thus, 84dBof typical DC error amplifier open-loop gain is realizedalong with a typical 75MHz uncompensated unity-gaincrossover frequency. Note that the overall feedbackloop’s DC gain decreases from the gain provided by theerror amplifier by the attenuation factor in the resistordivider network which sets the DC output voltage. Theseattenuation factors are already built into the Open-LoopVoltage Gain specifications for the LT1575 fixed voltageversions in the Electrical Characteristics table to simplifyuser calculations. External access to the high impedancegain node of the error amplifier permits typical loopcompensation to be accomplished with a series RCnetwork to ground.
A high speed, high current output stage buffers the COMPnode and drives up to 5000pF of “effective” MOSFET gatecapacitance with almost no change in load transient per-formance. The output stage delivers up to 50mA peakwhen slewing the MOSFET gate in response to loadcurrent transients. The typical output impedance of theGATE pin is typically 2Ω. This pushes the pole due to theerror amplifier output impedance and the MOSFET inputcapacitance well beyond the loop crossover frequency. Ifthe capacitance of the MOSFET used is less than 1500pF,it may be necessary to add a small value series gateresistor of 2Ω to 10Ω. This gate resistor helps damp theLC resonance created by the MOSFET gate’s lead induc-tance and input capacitance. In addition, the pole formedby this resistance and the MOSFET input capacitance canbe fine tuned.
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APPLICATIONS INFORMATION
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diagram and clamps the positive swing of the COMP nodein the main error amplifier to a voltage that provides anoutput load current of 50mV/RSENSE. This action contin-ues as long as the output current overload persists. Thesecond event is that a timer circuit activates at the SHDNpin. This pin is normally held low by a 5µA active pull-downthat limits to ≈ 100mV above ground. When current limitactivates, the 5µA pull-down turns off and a 15µA pull-upcurrent source turns on. Placing a capacitor in series withthe SHDN pin to ground generates a programmable timeramp voltage.
The SHDN pin is also the positive input of COMP1. Thenegative input is tied to the internal 1.21V reference. Whenthe SHDN pin ramps above VREF, the comparator drivesQ4 and Q5. This action pulls the COMP and GATE pins lowand latches the external MOSFET drive off. This conditionreduces the MOSFET power dissipation to zero. The timeperiod until the latched-off condition occurs is typicallyequal to CSHUT(1.11V)/15µA. For example, a 1µF capacitoron the SHDN pin yields a 74ms ramp time. In short, thisunique circuit block performs a current limit time-outfunction that latches off the regulator drive after a pre-defined time period. The time-out period selected is afunction of system requirements including start-up andsafe operating area. The SHDN pin is internally clamped totypically 1.85V by Q6 and R2. The comparator tied to theSHDN pin has 100mV of typical hysteresis to providenoise immunity. The hysteresis is especially useful whenusing the SHDN pin for thermal shutdown.
Restoring normal operation after the load current fault iscleared is accomplished in two ways. One option is torecycle the nominal 12V LT1575 supply voltage as long asan external bleed path for the Shutdown pin capacitor isprovided. The second option is to provide an active resetcircuit that pulls the SHDN pin below VREF. Pulling theSHDN pin below VREF turns off the 15µA pull-up currentsource and reactivates the 5µA pull-down. If the SHDN pinis held below VREF during a fault condition, the regulatorcontinues to operate in current limit into a short. Thisaction requires being able to sink 15µA from the SHDN pinat less than 1V. The 5µA pull-down current source and the15µA pull-up current source are designed low enough invalue so that an external resistor divider network can drivethe SHDN pin to provide overvoltage protection or to
provide thermal shutdown with the use of a thermistor inthe divider network. Diode-ORing these functions to-gether is simple to accomplish and provides multiplefunctionality for one pin.
If the current limit amplifier is not used, two choicespresent themselves. The simplest choice is to tie the INEGpin directly to the IPOS pin. This action defeats currentlimit and provides the simplest, no frills circuit. An appli-cation in which the current limit amplifier is not used iswhere an extremely low dropout voltage must be achievedand the 50mV threshold voltage cannot be tolerated.
However, a second available choice permits a user toprovide short-circuit protection with no external sensing.This technique is activated by grounding the INEG pin.This action disables the current limit amplifier becauseSchottky diode D1 clamps the amplifier’s output andprevents Q2 from pulling down the COMP node. In addi-tion, Schottky diode D2 turns off pull-down transistor Q1.Q1 is normally on and holds internal comparator COMP3’soutput low. This comparator circuit, now enabled, moni-tors the GATE pin and detects saturation at the positive rail.When a saturated condition is detected, COMP3 activatesthe shutdown timer. Once the time-out period occurs, theoutput is shut down and latched off. The operation ofresetting the latch remains the same. Note that this tech-nique does not limit the FET current during the time-outperiod. The output current is only limited by the inputpower supply and the input/output impedance. Setting thetimer to a short period in this mode of operation keeps theexternal MOSFET within its SOA (safe operating area)boundary and keeps the MOSFET’s temperature rise undercontrol.
Unique circuit design incorporated into the LT1575 allevi-ates all concerns about power supply sequencing. Theissue of power supply sequencing is an important topic asthe typical LT1575 application has inputs from two sepa-rate power supply voltages. If the typical 12V VIN supplyvoltage is slow in ramping up, insufficient MOSFET gatedrive is present and therefore, the output voltage doesnot come up. If the VIN supply voltage is present, but thetypical 5V supply voltage tied to the IPOS pin has notstarted yet, then the feedback loop wants to drive theGATE pin to the positive VIN rail. This would result in a
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APPLICATIONS INFORMATION
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very large current spike as soon as the 5V supply startedto ramp up. However, undervoltage lockout circuit COMP2,which monitors the IPOS supply voltage, holds Q3 on andpulls the COMP pin low until the IPOS voltage increasesto greater than the internal 1.21 reference voltage. Theundervoltage lockout circuit then smoothly releases theCOMP pin and allows the output voltage to come up indropout from the input supply voltage. An additionalbenefit derived from the speed of the LT1575 feedbackloop is that turn-on overshoot is virtually nonexistent ina properly compensated system.
An additional circuit feature is built-in to the LT1575 fixedvoltage versions. When the regulator circuit starts up, itmust charge up the output capacitors. The output voltagetypically tracks the input voltage supply as it ramps up withthe difference in input/output voltage defined by the drop-out voltage. Until the feedback loop comes into regulation,the circuit operation results in the GATE pin being at thepositive VIN rail, which starts the timer at the SHDN pin ifthe current limit amplifier is disabled. However, internalcomparator COMP4 monitors the input/output voltagedifferential. This comparator does not permit the shut-down timer to start until the differential voltage is greaterthan 500mV. This permits normal start-up to occur.
One final benefit is derived in using an LT1575 fixedvoltage version. Today’s highest performance micropro-
cessors dictate that precision resistors must be used withcurrently available adjustable voltage regulators to meetthe initial set point tolerance. The LT1575 fixed voltageversions incorporate the precision resistor divider into theIC and still maintain a 1% output voltage tolerance overtemperature. Thus, the LT1575 fixed voltage versionscompletely eliminate the requirement for precision resis-tors and this results in additional system cost savings.
Applications Support
Linear Technology invests an enormous amount of time,resources and technical expertise in understanding, de-signing and evaluating microprocessor power supply so-lutions for system designers. As processor speeds andpower increase, the power supply challenges presented tothe motherboard designer increase as well. ApplicationNote 69, “Using the LT1575 Linear Regulator Controller,”has been written and serves as an extremely useful guidefor this new family of ICs. This Application Note coverstopics including PC board layout for the LT1575/LT1577family, MOSFET selection criteria, external componentselection (capacitors) and loop compensation. LinearTechnology welcomes the opportunity to discuss, design,evaluate and optimize a microprocessor power supplysolution with a customer. For additional information,consult the factory.
UltraFast Transient Response 5V to 3.5V Low Dropout Regulatorwith Current Limit and Timer Latchoff
1
2
3
4
8
7
6
5
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMP
C2 1µF
C5 220µF
5V
GND
1575/77 TA11
VOUT 3.5V 5A
R2 5Ω
R3* 0.007Ω
R1 7.5k
12V LT1575-3.5
C4 1000pF
C1 1µFRESET
R3 IS MADE FROM “FREE” PC BOARD TRACE C6 = 24 × 1µF X7R CERAMIC SURFACE MOUNT CAPACITORS. PLACE C6 IN THE MICROPROCESSOR SOCKET CAVITY
*
**
Q2 VN2222L
Q1 IRFZ24
+
C3 10pF
C6** 24µF
TYPICAL APPLICATIONS N
U
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TYPICAL APPLICATIONS N
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Setting Output Voltage with the Adjustable LT1575
FB
1575 TA03
R2
VOUT = 1.21V(1 + R2/R1)
VOUT
R1
Using “Sense-Less” Current Limit
C1 10µFCT
R3 10Ω
IPOSSHDN VCC
1575 TA04VOUT
Q1
INEG
GATE
Shutdown Time-Out with Reset Overvoltage Protection
R3 100k
R2 100k
C2*
1575 TA09
*C2 = 15µA(t)/1.11V t = SHUTDOWN LATCH-OFF TIME
SHDN
Q2 2N3904
RESET 0V TO 5V
SHDN
1575 TA10
VOUT
R5
R6
VOUT(uth) = 1.21(R6/R5) + 5µA(R6) VOUT(lth) = 1.11(R6/R5) – 15µA(R6)
Shutdown Time-Out with Reset Basic Thermal Shutdown
R1 100k
C1*
1575 TA07
*C1 = 15µA(t)/1.11V t = SHUTDOWN LATCHOFF TIME
SHDN
Q1 VN2222L
RESET 0V TO 5V
SHDN
1575 TA08
RT1 10k NTC
5V
R4 549Ω
RT1 = DALE NTHS-1206N02 THERMALLY MOUNT RT1 IN CLOSE PROXIMITY TO THE EXTERNAL N-CHANNEL MOSFET
Setting Current Limit
IPOS VCC
RSENSE*
*ILIM = 50mV/RSENSE RSENSE = DISCRETE SHUNT RESISTOR OR RSENSE = KELVIN-SENSED PC BOARD TRACE ACTIVATING CURRENT LIMIT ALSO ACTIVATES THE SHDN PIN TIMER 1575 TA05
VOUT
Q2
INEG
GATE
Setting Current Limit with Foldback Limiting
IPOS VCC
R4
D1 1N4148D2 1N4148
R5 10Ω
1575 TA06VOUT
Q3
INEG
GATER6 1.2k
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TYPICAL APPLICATIONS N
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1
2
3
4
8
7
6
5
+
LT1575-1.5
R2 3.9Ω
R1 0.005Ω
R5 150Ω
R4 75Ω R8
100ΩR9 100Ω
VTT 1.5V
R10 100Ω
R6 75Ω
R7 150Ω
R3 4.99k
C5 1000pF
C8 TO C23 1µF CERAMIC 0805 CASE
C6 0.1µF
C7 0.1µF
VREF VREF
Q1 IRFZ24
C3 1µF
C4 10pF
C2 0.22µF
RESET
12VVIN
3.3V C1 220µF 6.3V
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMPRX
TX
• • •
RX
TX
RX
TX
RX
TXQ4
Q2 Q3
Q5
1575/77 TA12142 TOTAL SIGNAL LINES
NOTE: LTC RECOMMENDS CENTRALLY LOCATING THE LT1575-1.5 OUTPUT TO MINIMIZE VTT DISTRIBUTION DROPS AND USING SEPARATE VREF GENERATORS AT EACH BUS END
R11 100Ω
Pentium® II Processor GTL+ Power Supply
Generating 12V Gate Drive from a 5V Power Supply
1
2
3
4
8
7
6
5
LT1262
C1 0.22µF
C3 4.7µF
C8 390pF
R1 2k
74HC14
D6 BAT85
D3 BAT85
C9 0.22µF
C7 100µF
10V
1575/77 TA13
C6 10µF 25V
C5 100µF
10V
D1 1N5818
L1 33µH
C4 4.7µF
12V 25mA
12V 25mA
12V 25mA
VCC 4.75V TO 5.5V
VCC 4.75V TO 5.5V
VCC 4.75V TO 5.5V
C1–
C1+
C2–
C2+
SHDN
GND
VOUT
VCC
+
+
+
+
C11 0.22µF
C12 0.22µF
C10 0.22µF
C2 0.22µF
SW
2
1
3LT1109CZ-12
VOUT
GND
+
D2 BAT85
D4 BAT85
D5 BAT85
×5
Pentium is a registered trademark of Intel Corporation.
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TYPICAL APPLICATIONS N
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12V to 3.3V/9A (14A Peak) Hybrid Regulator
Transient Response to a 10A Load Step
50m
V/DI
V
200µs/DIV1575/77 TA17
+
+ + + +
1575/77 TA16
TG
SW
BOOST
INTVCC
BG
S+
S–
EXTVCC
COSC
RUN/SS
ITH
SFB
SGND
VOS
9
1
2
3
4
5
6
16
14
15
12
11
8
7
13
10C4, 4.7µF
C5 0.1µF
D2 MBRS330T3
R8 15K
R3 100
R4 100
C18 1000µF 10V
C20 1000µF
10V
C19 1000µF 10V
R6 0.0075Ω
L1 4µH
C2, 1000pF
VIN
LTC1435
C21, 10pF
C22, 1000pF
R2 1.21k
1%
C1, 470pF
R9 2k
Q1 IRLZ44
R1 2.1k, 1% VCORE
3.3V
1
2
3
4
8
7
6
5
PGND
D1, CMDSH-3 Q3
Q2
C16 1µF
C14 150µF 16V
C15 1µF
C17 1µF
12V
C11 150µF 16V
C12 150µF 16V
C13 150µF 16V
C3, 0.1µF
C9 1500pF
R5 16.5k
C10, 1000pF
C8, 68pF
C7, 0.1µF
R7 35.7k
+ C23 1µF
C6 0.1µF
12V
1µF X7R
CERAMIC 0805 CASE
×40
+
+
L1=COILTRONICS CTX02-13199 Q2, Q3 =SILICONIX SUD50N03-10
LT1575
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMP
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TYPICAL APPLICATIONS N
U
3.3V to 2.8V ±100mV at 5.7A with Sense-Less Current Limit and Timer Latchoff
+
+
1
2
3
4
8
7
6
5
C2 330µF 6.3V
C3 680pF
C7 10µF
C4 1000pF
R1 4.7k
R2 10Ω
C8 TO C31* 1µF
Q1 IRL3303
VCORE 2.8V
C5 22pF
1575/77 TA14
FAULT RESET
C6 0.1µF
12V
C1 330µF 6.3V
INPUT 3.3V
RTN
+
*X7R CERAMIC 0805 CASE
LT1575-2.8
SHDN
VIN
GND
OUT
IPOS
INEG
GATE
COMP
N8 1197
0.100 ± 0.010 (2.540 ± 0.254)
0.065 (1.651)
TYP
0.045 – 0.065 (1.143 – 1.651)
0.130 ± 0.005 (3.302 ± 0.127)
0.020 (0.508)
MIN0.018 ± 0.003
(0.457 ± 0.076)
0.125 (3.175)
MIN
1 2 3 4
8 7 6 5
0.255 ± 0.015* (6.477 ± 0.381)
0.400* (10.160)
MAX
0.009 – 0.015 (0.229 – 0.381)
0.300 – 0.325 (7.620 – 8.255)
0.325+0.035 –0.015+0.889 –0.3818.255( )
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
N8 Package8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
Dimensions in inches (millimeters) unless otherwise noted.PACKAGE DESCRIPTIONU
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LT1575/LT1577
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
1 2 3 4
0.150 – 0.157** (3.810 – 3.988)
8 7 6 5
0.189 – 0.197* (4.801 – 5.004)
0.228 – 0.244 (5.791 – 6.197)
0.016 – 0.050 0.406 – 1.270
0.010 – 0.020 (0.254 – 0.508)
× 45°
0°– 8° TYP0.008 – 0.010
(0.203 – 0.254)
SO8 0996
0.053 – 0.069 (1.346 – 1.752)
0.014 – 0.019 (0.355 – 0.483)
0.004 – 0.010 (0.101 – 0.254)
0.050 (1.270)
TYPDIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
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LT1575/LT1577
PACKAGE DESCRIPTION
U
Dimensions in inches (millimeters) unless otherwise noted.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S Package16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.016 – 0.050 0.406 – 1.270
0.010 – 0.020 (0.254 – 0.508)
× 45°
0° – 8° TYP0.008 – 0.010
(0.203 – 0.254)
1 2 3 4 5 6 7 8
0.150 – 0.157** (3.810 – 3.988)
16 15 14 13
0.386 – 0.394* (9.804 – 10.008)
0.228 – 0.244 (5.791 – 6.197)
12 11 10 9
S16 0695
0.053 – 0.069 (1.346 – 1.752)
0.014 – 0.019 (0.355 – 0.483)
0.004 – 0.010 (0.101 – 0.254)
0.050 (1.270)
TYPDIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
*
**
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LT1575/LT1577
LINEAR TECHNOLOGY CORPORATION 1996
15757f LT/TP 0598 4K • PRINTED IN THE USA
LT1577 Split Plane System
TYPICAL APPLICATION
U
+ C2 330µF 6.3V
C3 0.33µF
C6 1500pF
R2 3.9k
R1 3.9Ω
R5 3.9Ω
C9 TO C20* 1µF
Q1 IRFZ24
VI/O 3.3V
C5 10pF C8
1000pF
R6 7.5kC7
10pF
1575/77 TA15
FAULT RESET
C4 1µF
12V
C1 330µF
6.3V
INPUT 5V
+
Q2 IRFZ24
*X7R CERAMIC 0805 CASE
C21 TO C44* 1µF
VCORE 2.8V
1
2
3
4
16
15
14
13
IPOS1
INEG1
GATE1
COMP1
SHDN1
VIN1
GND1
OUT-3.3
1/2 LT15775
6
7
8
12
11
10
9
IPOS2
INEG2
GATE2
COMP2
SHDN2
VIN2
GND2
OUT-2.8
1/2 LT1577
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com
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