Current mirror design
In AMIS CMOS 07
by Roman Prokop
Simple current mirror
mV200drecommende,
GSMIN
GSDS
VVV
GSTGS VVV 0
2)(2.
/
GSp
D
VKI
LW
ncalculatioLW
Saturace
20 )(
.2.
TGSp
D VVLWK
I
AMIS CMOS 07 paramVT0 & KP = f (T, process) graphs
• NMOS
Process VT0 [V] Kp [A/V2] Temp [°C]
Typ 0.75 9. 10-5 27
Fast 0.7 1.75 .10-4 -50
Fast 0.45 7 .10-5 150
Slow 1.00 1.25 .10-4 -50
Slow 0.75 5 .10-5 150
W/L calculation for typ parameters
20 )(
.2.
TGSp
D VVLWK
I
711.7)(
2.2
_
GStypp
D
VKI
LW
Choose ∆VGS= 250 mV & ID= 20 μA
Ideal Vds1=Vds2
solution- Decrease the Vds influence large L- cascoda
simplifiedVVVLWK
I DSTGSp
D ).1.()(.2. 2
0
min. ∆VGS max. ∆VGS
mVWKpLIVmV
WKpLIV D
GSMAXD
GSMIN 335..2.179
..2.
minmax
VVVV
VVVVVVV
slowGSfastGS
slowGSfastGS
GSTGS
212.1212.000.1733.028.045.0
085.1335.075.0879.0179.07.0casesworstthe
50_150_
150_50_
0
Then input current can vary between (even for fix (dummy) resistor R)
Ak
IAk
I
Ak
IRVVccI
ININ
INtypGSM
IN
94.18200
212.15335.21200
733.05
20200
)25.075.0(5;
maxmax
1
150°C hipo(min)IIN ↑ -50°C hipo(max)IIN ↓
How to get fixed voltage for current mirror biasing ?
How to get fixed voltage for current mirror biasing ?
NR
UrefINRUrefUccI mirrmirr ..
better – doesn’t depend on Ucc
Premise- 2 transistors in common centroid (crossquad)- ideal surrounding
Instructions in:“Electrical parameters CMOS07” manual (ds13291.pdf)
Matching hand calculation
Exemplary calculation – choose W/L=7 W/L= 35u/5uquite small MOS
A1 A2 B1 B2
A1
A2
B1
B2
Matching
222
20
20
20
22
0
20
2
/)/(
/)(
where
)/()(
4.)()/(
CWLA
CWLAV
VVVII
VTVTT
TGSTdd
Error in VT0 Error in β
For good matching (small current difference)- larger MOS high WL- higher (VGS – VT0)
Statistical errors –- count under square root
Matching
Table is valid for NMOS, PMOS parameters in electrical parameters
Carefully: units mV, μm, %
Matching
sigma11495.0)(
sigma1148.020.399.7.)/(
399.7)/(
47.582.3)25.0(
4.957.7
)/()(
4.)()/(
95.1)/(
82.3)05.0()355/()5.2(/)/(
892.0)(
957.7)2.0()355/()5.11(/)(
3
3
562
7
22
0
20
2
3
62222222
0
27232320
20
20
forAresultcadenceI
forAAeIIII
eII
eee
VVVII
e
eeeCWLA
mVV
VeeeCWLAV
d
dddd
dd
TGSTdd
T
VTVTT
MatchingCadence matching tool output file
Biasing currentsUsually use buffered band-gap reference voltage
1 - External resistor - accurate resistance value, almost temperature
independent
2 – Hipo internal resistor- hipo resistance 2000 Ω (1600 Ω - 2400 Ω)- temperature dependence - viz. parameterFile
3 – other CMOS resistor types- not used because of small sheet resistance
One chip can combine both types of bias currents
Biasing currents
NRRUUbias
refout .. 2 22 .. UN
RRUUbias
refout
Hipo internal resistor bias current advantages- temperature dependent current can help with
stability of some circuits
- quite accurate voltage level shifter
2_2 .. MDSbias
refout VNRRUU
Current mirror and resistor MATCHING !!!!MATCHING !!!!
Cascoded mirror output resistanceCascoded mirror output resistance
424 .. rorogmRocasc
24
4
444
.where
)(.
roivro
vvvgmi
tgs
tgst
express It
42424
44
224
4
2
424
..
)1..(
).(
rorororogmiv
rov
rororogmi
roroi
rovroigmi
t
t
tt
tt
tt
negligible
Good luck !!!Good luck !!!
Top Related